From 6fa300aa1e602136046198ae8bb076d2e577cec8 Mon Sep 17 00:00:00 2001
From: Nico Weber <nicolasweber@gmx.de>
Date: Tue, 20 Aug 2019 23:49:12 +0000
Subject: [PATCH] gn build: Merge r369467

llvm-svn: 369476
---
 llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
index 7a0610e..7df0713 100644
--- a/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
@@ -20,17 +20,31 @@ tablegen("RISCVGenDAGISel") {
   td_file = "RISCV.td"
 }
 
+tablegen("RISCVGenGlobalISel") {
+  visibility = [ ":LLVMRISCVCodeGen" ]
+  args = [ "-gen-global-isel" ]
+  td_file = "RISCV.td"
+}
+
 tablegen("RISCVGenMCPseudoLowering") {
   visibility = [ ":LLVMRISCVCodeGen" ]
   args = [ "-gen-pseudo-lowering" ]
   td_file = "RISCV.td"
 }
 
+tablegen("RISCVGenRegisterBank") {
+  visibility = [ ":LLVMRISCVCodeGen" ]
+  args = [ "-gen-register-bank" ]
+  td_file = "RISCV.td"
+}
+
 static_library("LLVMRISCVCodeGen") {
   deps = [
     ":RISCVGenCompressInstEmitter",
     ":RISCVGenDAGISel",
+    ":RISCVGenGlobalISel",
     ":RISCVGenMCPseudoLowering",
+    ":RISCVGenRegisterBank",
     "MCTargetDesc",
     "TargetInfo",
     "Utils",
@@ -46,13 +60,17 @@ static_library("LLVMRISCVCodeGen") {
   include_dirs = [ "." ]
   sources = [
     "RISCVAsmPrinter.cpp",
+    "RISCVCallLowering.cpp",
     "RISCVExpandPseudoInsts.cpp",
     "RISCVFrameLowering.cpp",
     "RISCVISelDAGToDAG.cpp",
     "RISCVISelLowering.cpp",
     "RISCVInstrInfo.cpp",
+    "RISCVInstructionSelector.cpp",
+    "RISCVLegalizerInfo.cpp",
     "RISCVMCInstLower.cpp",
     "RISCVMergeBaseOffset.cpp",
+    "RISCVRegisterBankInfo.cpp",
     "RISCVRegisterInfo.cpp",
     "RISCVSubtarget.cpp",
     "RISCVTargetMachine.cpp",
-- 
2.7.4