From 6f3a756998b3f8dde7d330878d3c0a78624bd87e Mon Sep 17 00:00:00 2001 From: Dmitry Bushev Date: Fri, 17 Feb 2023 15:03:40 +0300 Subject: [PATCH] [RISCV][NFC] Add missing immediate operand types. Some immediate types in RISCV target description lack operand type field. This leads them being listed as OPERAND_UNKNOWN in MCOperandInfo. This patch adds this fields. This is NFC because it does not affect flow of any current tools implementation. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D144105 --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 3 +++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 10 ++++++++++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 6 ++++++ 3 files changed, 19 insertions(+) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 2ec13d1..c7a6fa6 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -247,6 +247,8 @@ enum OperandType : unsigned { OPERAND_UIMM7_LSB00, OPERAND_UIMM8_LSB00, OPERAND_UIMM8_LSB000, + OPERAND_UIMM9_LSB000, + OPERAND_UIMM10_LSB00_NONZERO, OPERAND_UIMM12, OPERAND_ZERO, OPERAND_SIMM5, @@ -259,6 +261,7 @@ enum OperandType : unsigned { OPERAND_UIMM20, OPERAND_UIMMLOG2XLEN, OPERAND_UIMMLOG2XLEN_NONZERO, + OPERAND_CLUI_IMM, OPERAND_VTYPEI10, OPERAND_VTYPEI11, OPERAND_RVKRNUM, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index ee50d35f..1185d5e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1660,9 +1660,15 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, case RISCVOp::OPERAND_UIMM8_LSB000: Ok = isShiftedUInt<5, 3>(Imm); break; + case RISCVOp::OPERAND_UIMM9_LSB000: + Ok = isShiftedUInt<6, 3>(Imm); + break; case RISCVOp::OPERAND_SIMM10_LSB0000_NONZERO: Ok = isShiftedInt<6, 4>(Imm) && (Imm != 0); break; + case RISCVOp::OPERAND_UIMM10_LSB00_NONZERO: + Ok = isShiftedUInt<8, 2>(Imm) && (Imm != 0); + break; case RISCVOp::OPERAND_ZERO: Ok = Imm == 0; break; @@ -1697,6 +1703,10 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, Ok = STI.is64Bit() ? isUInt<6>(Imm) : isUInt<5>(Imm); Ok = Ok && Imm != 0; break; + case RISCVOp::OPERAND_CLUI_IMM: + Ok = (isUInt<5>(Imm) && Imm != 0) || + (Imm >= 0xfffe0 && Imm <= 0xfffff); + break; case RISCVOp::OPERAND_RVKRNUM: Ok = Imm >= 0 && Imm <= 10; break; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index 4cf6568..9b3e142 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -93,6 +93,8 @@ def c_lui_imm : Operand, let ParserMatchClass = CLUIImmAsmOperand; let EncoderMethod = "getImmOpValue"; let DecoderMethod = "decodeCLUIImmOperand"; + let OperandType = "OPERAND_CLUI_IMM"; + let OperandNamespace = "RISCVOp"; let MCOperandPredicate = [{ int64_t Imm; if (MCOp.evaluateAsConstantImm(Imm)) @@ -173,6 +175,8 @@ def uimm9_lsb000 : Operand, let ParserMatchClass = UImmAsmOperand<9, "Lsb000">; let EncoderMethod = "getImmOpValue"; let DecoderMethod = "decodeUImmOperand<9>"; + let OperandType = "OPERAND_UIMM9_LSB000"; + let OperandNamespace = "RISCVOp"; let MCOperandPredicate = [{ int64_t Imm; if (!MCOp.evaluateAsConstantImm(Imm)) @@ -189,6 +193,8 @@ def uimm10_lsb00nonzero : Operand, let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">; let EncoderMethod = "getImmOpValue"; let DecoderMethod = "decodeUImmNonZeroOperand<10>"; + let OperandType = "OPERAND_UIMM10_LSB00_NONZERO"; + let OperandNamespace = "RISCVOp"; let MCOperandPredicate = [{ int64_t Imm; if (!MCOp.evaluateAsConstantImm(Imm)) -- 2.7.4