From 6f28b0bb0ab3323c1c5c375db56b35c4933837e4 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Amaury=20S=C3=A9chet?= Date: Thu, 18 May 2023 14:44:53 +0000 Subject: [PATCH] [NFC] Flatten the logic in RISCVTargetLowering::decomposeMulByConstant --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 52 ++++++++++++++++------------- 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9d954c7..c823792 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -15891,31 +15891,35 @@ bool RISCVTargetLowering::decomposeMulByConstant(LLVMContext &Context, EVT VT, // Check integral scalar types. const bool HasExtMOrZmmul = Subtarget.hasStdExtM() || Subtarget.hasStdExtZmmul(); - if (VT.isScalarInteger()) { - // Omit the optimization if the sub target has the M extension and the data - // size exceeds XLen. - if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen()) - return false; - if (auto *ConstNode = dyn_cast(C.getNode())) { - // Break the MUL to a SLLI and an ADD/SUB. - const APInt &Imm = ConstNode->getAPIntValue(); - if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() || - (1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2()) - return true; - // Optimize the MUL to (SH*ADD x, (SLLI x, bits)) if Imm is not simm12. - if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(12) && - ((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2() || - (Imm - 8).isPowerOf2())) + if (!VT.isScalarInteger()) + return false; + + // Omit the optimization if the sub target has the M extension and the data + // size exceeds XLen. + if (HasExtMOrZmmul && VT.getSizeInBits() > Subtarget.getXLen()) + return false; + + if (auto *ConstNode = dyn_cast(C.getNode())) { + // Break the MUL to a SLLI and an ADD/SUB. + const APInt &Imm = ConstNode->getAPIntValue(); + if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2() || + (1 - Imm).isPowerOf2() || (-1 - Imm).isPowerOf2()) + return true; + + // Optimize the MUL to (SH*ADD x, (SLLI x, bits)) if Imm is not simm12. + if (Subtarget.hasStdExtZba() && !Imm.isSignedIntN(12) && + ((Imm - 2).isPowerOf2() || (Imm - 4).isPowerOf2() || + (Imm - 8).isPowerOf2())) + return true; + + // Break the MUL to two SLLI instructions and an ADD/SUB, if Imm needs + // a pair of LUI/ADDI. + if (!Imm.isSignedIntN(12) && Imm.countr_zero() < 12 && + ConstNode->hasOneUse()) { + APInt ImmS = Imm.ashr(Imm.countr_zero()); + if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() || + (1 - ImmS).isPowerOf2()) return true; - // Break the MUL to two SLLI instructions and an ADD/SUB, if Imm needs - // a pair of LUI/ADDI. - if (!Imm.isSignedIntN(12) && Imm.countr_zero() < 12 && - ConstNode->hasOneUse()) { - APInt ImmS = Imm.ashr(Imm.countr_zero()); - if ((ImmS + 1).isPowerOf2() || (ImmS - 1).isPowerOf2() || - (1 - ImmS).isPowerOf2()) - return true; - } } } -- 2.7.4