From 6f12fc2b82abafcc7c8a92550baabb8e24da98f8 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 5 Dec 2022 21:15:02 +0000 Subject: [PATCH] [InstCombine] Regenerate select-masked_load.ll test checks --- .../Transforms/InstCombine/select-masked_load.ll | 58 +++++++++++++--------- 1 file changed, 34 insertions(+), 24 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/select-masked_load.ll b/llvm/test/Transforms/InstCombine/select-masked_load.ll index 10ee77e..0e82def 100644 --- a/llvm/test/Transforms/InstCombine/select-masked_load.ll +++ b/llvm/test/Transforms/InstCombine/select-masked_load.ll @@ -1,10 +1,12 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -passes=instcombine -S | FileCheck %s ; Fold zeroing of inactive lanes into the load's passthrough parameter. define <4 x float> @masked_load_and_zero_inactive_1(ptr %ptr, <4 x i1> %mask) { ; CHECK-LABEL: @masked_load_and_zero_inactive_1( -; CHECK: %load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x float> zeroinitializer) -; CHECK-NEXT: ret <4 x float> %load +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK:%.*]], <4 x float> zeroinitializer) +; CHECK-NEXT: ret <4 x float> [[LOAD]] +; %load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x float> undef) %masked = select <4 x i1> %mask, <4 x float> %load, <4 x float> zeroinitializer ret <4 x float> %masked @@ -13,8 +15,9 @@ define <4 x float> @masked_load_and_zero_inactive_1(ptr %ptr, <4 x i1> %mask) { ; As above but reuse the load's existing passthrough. define <4 x i32> @masked_load_and_zero_inactive_2(ptr %ptr, <4 x i1> %mask) { ; CHECK-LABEL: @masked_load_and_zero_inactive_2( -; CHECK: %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> zeroinitializer) -; CHECK-NEXT: ret <4 x i32> %load +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK:%.*]], <4 x i32> zeroinitializer) +; CHECK-NEXT: ret <4 x i32> [[LOAD]] +; %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> zeroinitializer) %masked = select <4 x i1> %mask, <4 x i32> %load, <4 x i32> zeroinitializer ret <4 x i32> %masked @@ -23,9 +26,10 @@ define <4 x i32> @masked_load_and_zero_inactive_2(ptr %ptr, <4 x i1> %mask) { ; No transform when the load's passthrough cannot be reused or altered. define <4 x i32> @masked_load_and_zero_inactive_3(ptr %ptr, <4 x i1> %mask, <4 x i32> %passthrough) { ; CHECK-LABEL: @masked_load_and_zero_inactive_3( -; CHECK: %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> %passthrough) -; CHECK-NEXT: %masked = select <4 x i1> %mask, <4 x i32> %load, <4 x i32> zeroinitializer -; CHECK-NEXT: ret <4 x i32> %masked +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK:%.*]], <4 x i32> [[PASSTHROUGH:%.*]]) +; CHECK-NEXT: [[MASKED:%.*]] = select <4 x i1> [[MASK]], <4 x i32> [[LOAD]], <4 x i32> zeroinitializer +; CHECK-NEXT: ret <4 x i32> [[MASKED]] +; %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> %passthrough) %masked = select <4 x i1> %mask, <4 x i32> %load, <4 x i32> zeroinitializer ret <4 x i32> %masked @@ -34,9 +38,10 @@ define <4 x i32> @masked_load_and_zero_inactive_3(ptr %ptr, <4 x i1> %mask, <4 x ; Remove redundant select when its mask doesn't overlap with the load mask. define <4 x i32> @masked_load_and_zero_inactive_4(ptr %ptr, <4 x i1> %inv_mask) { ; CHECK-LABEL: @masked_load_and_zero_inactive_4( -; CHECK: %mask = xor <4 x i1> %inv_mask, -; CHECK-NEXT: %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> zeroinitializer) -; CHECK-NEXT: ret <4 x i32> %load +; CHECK-NEXT: [[MASK:%.*]] = xor <4 x i1> [[INV_MASK:%.*]], +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK]], <4 x i32> zeroinitializer) +; CHECK-NEXT: ret <4 x i32> [[LOAD]] +; %mask = xor <4 x i1> %inv_mask, %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> undef) %masked = select <4 x i1> %inv_mask, <4 x i32> zeroinitializer, <4 x i32> %load @@ -46,9 +51,10 @@ define <4 x i32> @masked_load_and_zero_inactive_4(ptr %ptr, <4 x i1> %inv_mask) ; As above but reuse the load's existing passthrough. define <4 x i32> @masked_load_and_zero_inactive_5(ptr %ptr, <4 x i1> %inv_mask) { ; CHECK-LABEL: @masked_load_and_zero_inactive_5( -; CHECK: %mask = xor <4 x i1> %inv_mask, -; CHECK-NEXT: %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> zeroinitializer) -; CHECK-NEXT: ret <4 x i32> %load +; CHECK-NEXT: [[MASK:%.*]] = xor <4 x i1> [[INV_MASK:%.*]], +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK]], <4 x i32> zeroinitializer) +; CHECK-NEXT: ret <4 x i32> [[LOAD]] +; %mask = xor <4 x i1> %inv_mask, %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> zeroinitializer) %masked = select <4 x i1> %inv_mask, <4 x i32> zeroinitializer, <4 x i32> %load @@ -58,10 +64,11 @@ define <4 x i32> @masked_load_and_zero_inactive_5(ptr %ptr, <4 x i1> %inv_mask) ; No transform when the load's passthrough cannot be reused or altered. define <4 x i32> @masked_load_and_zero_inactive_6(ptr %ptr, <4 x i1> %inv_mask, <4 x i32> %passthrough) { ; CHECK-LABEL: @masked_load_and_zero_inactive_6( -; CHECK: %mask = xor <4 x i1> %inv_mask, -; CHECK-NEXT: %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> %passthrough) -; CHECK-NEXT: %masked = select <4 x i1> %inv_mask, <4 x i32> zeroinitializer, <4 x i32> %load -; CHECK-NEXT: ret <4 x i32> %masked +; CHECK-NEXT: [[MASK:%.*]] = xor <4 x i1> [[INV_MASK:%.*]], +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK]], <4 x i32> [[PASSTHROUGH:%.*]]) +; CHECK-NEXT: [[MASKED:%.*]] = select <4 x i1> [[INV_MASK]], <4 x i32> zeroinitializer, <4 x i32> [[LOAD]] +; CHECK-NEXT: ret <4 x i32> [[MASKED]] +; %mask = xor <4 x i1> %inv_mask, %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask, <4 x i32> %passthrough) %masked = select <4 x i1> %inv_mask, <4 x i32> zeroinitializer, <4 x i32> %load @@ -71,9 +78,10 @@ define <4 x i32> @masked_load_and_zero_inactive_6(ptr %ptr, <4 x i1> %inv_mask, ; No transform when select and load masks have no relation. define <4 x i32> @masked_load_and_zero_inactive_7(ptr %ptr, <4 x i1> %mask1, <4 x i1> %mask2) { ; CHECK-LABEL: @masked_load_and_zero_inactive_7( -; CHECK: %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask1, <4 x i32> zeroinitializer) -; CHECK-NEXT: %masked = select <4 x i1> %mask2, <4 x i32> zeroinitializer, <4 x i32> %load -; CHECK-NEXT: ret <4 x i32> %masked +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[MASK1:%.*]], <4 x i32> zeroinitializer) +; CHECK-NEXT: [[MASKED:%.*]] = select <4 x i1> [[MASK2:%.*]], <4 x i32> zeroinitializer, <4 x i32> [[LOAD]] +; CHECK-NEXT: ret <4 x i32> [[MASKED]] +; %load = call <4 x i32> @llvm.masked.load.v4i32.p0(ptr %ptr, i32 4, <4 x i1> %mask1, <4 x i32> zeroinitializer) %masked = select <4 x i1> %mask2, <4 x i32> zeroinitializer, <4 x i32> %load ret <4 x i32> %masked @@ -83,10 +91,11 @@ define <4 x i32> @masked_load_and_zero_inactive_7(ptr %ptr, <4 x i1> %mask1, <4 ; load's inactive lanes and thus the load's passthrough takes effect. define <4 x float> @masked_load_and_zero_inactive_8(ptr %ptr, <4 x i1> %inv_mask, <4 x i1> %cond) { ; CHECK-LABEL: @masked_load_and_zero_inactive_8( -; CHECK: %mask = xor <4 x i1> %inv_mask, -; CHECK-NEXT: %pg = and <4 x i1> %mask, %cond -; CHECK-NEXT: %load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %ptr, i32 4, <4 x i1> %pg, <4 x float> zeroinitializer) -; CHECK-NEXT: ret <4 x float> %load +; CHECK-NEXT: [[MASK:%.*]] = xor <4 x i1> [[INV_MASK:%.*]], +; CHECK-NEXT: [[PG:%.*]] = and <4 x i1> [[MASK]], [[COND:%.*]] +; CHECK-NEXT: [[LOAD:%.*]] = call <4 x float> @llvm.masked.load.v4f32.p0(ptr [[PTR:%.*]], i32 4, <4 x i1> [[PG]], <4 x float> zeroinitializer) +; CHECK-NEXT: ret <4 x float> [[LOAD]] +; %mask = xor <4 x i1> %inv_mask, %pg = and <4 x i1> %mask, %cond %load = call <4 x float> @llvm.masked.load.v4f32.p0(ptr %ptr, i32 4, <4 x i1> %pg, <4 x float> undef) @@ -100,6 +109,7 @@ define <8 x float> @masked_load_and_scalar_select_cond(ptr %ptr, <8 x i1> %mask, ; CHECK-NEXT: [[TMP0:%.*]] = call <8 x float> @llvm.masked.load.v8f32.p0(ptr [[PTR:%.*]], i32 32, <8 x i1> [[MASK:%.*]], <8 x float> undef) ; CHECK-NEXT: [[TMP1:%.*]] = select i1 [[COND:%.*]], <8 x float> zeroinitializer, <8 x float> [[TMP0]] ; CHECK-NEXT: ret <8 x float> [[TMP1]] +; entry: %0 = call <8 x float> @llvm.masked.load.v8f32.p0(ptr %ptr, i32 32, <8 x i1> %mask, <8 x float> undef) %1 = select i1 %cond, <8 x float> zeroinitializer, <8 x float> %0 -- 2.7.4