From 6ebd55b3bba383e0523b0c014f17c97f3ce80708 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Mon, 12 Jun 2023 19:13:36 +0200 Subject: [PATCH] arm64: dts: rockchip: add combo PHYs to rk3588 Add all 3 combo PHYs that can be found in RK3588. They are used for SATA, PCIe or USB3. Signed-off-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230612171337.74576-5-sebastian.reichel@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3588.dtsi | 21 ++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi index 8be7555..5a5fe3a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi @@ -7,6 +7,11 @@ #include "rk3588-pinctrl.dtsi" / { + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -123,4 +128,20 @@ queue1 {}; }; }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + status = "disabled"; + }; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 1576f9b..fce1ebe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -407,6 +407,16 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; }; + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,rk3588-pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>; @@ -1943,6 +1953,38 @@ #dma-cells = <1>; }; + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "ref", "apb", "pipe"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + #phy-cells = <1>; + resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>; + reset-names = "phy", "apb"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + status = "disabled"; + }; + system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>; -- 2.7.4