From 6e9d554fa6e481a848358c215f129432262123c0 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Mon, 12 Dec 2011 16:09:28 +0100 Subject: [PATCH] can: flexcan: fix irq flooding by clearing all interrupt sources MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit As pointed out by Reuben Dowle and Lothar Waßmann, the TWRN_INT, RWRN_INT, BOFF_INT interrupt sources need to be cleared as well to avoid interrupt flooding, at least for the Flexcan on i.MX28 SOCs. Furthermore, the interrupts are only cleared, if really one of those interrupt sources are pending (which is not the case for rx and tx done). Cc: Reuben Dowle Cc: Lothar Waßmann Signed-off-by: Wolfgang Grandegger Signed-off-by: Marc Kleine-Budde --- drivers/net/can/flexcan.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index 7fd8089..96d2357 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -118,6 +118,9 @@ (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) #define FLEXCAN_ESR_ERR_ALL \ (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) +#define FLEXCAN_ESR_ALL_INT \ + (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ + FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) /* FLEXCAN interrupt flag register (IFLAG) bits */ #define FLEXCAN_TX_BUF_ID 8 @@ -577,7 +580,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id) reg_iflag1 = flexcan_read(®s->iflag1); reg_esr = flexcan_read(®s->esr); - flexcan_write(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */ + /* ACK all bus error and state change IRQ sources */ + if (reg_esr & FLEXCAN_ESR_ALL_INT) + flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); /* * schedule NAPI in case of: -- 2.7.4