From 6e7cc49d5cb31ee09b07252b6641d7c94977fd12 Mon Sep 17 00:00:00 2001 From: Joerg Sonnenberger Date: Tue, 23 Apr 2019 15:15:33 +0000 Subject: [PATCH] [SPARC] Use the correct register set for the "r" asm constraint. 64bit mode must use 64bit registers, otherwise assumptions about the top half of the registers are made. Problem found by Takeshi Nakayama in NetBSD. llvm-svn: 358998 --- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 2 ++ llvm/test/CodeGen/SPARC/reg64.ll | 10 ++++++++++ 2 files changed, 12 insertions(+) create mode 100644 llvm/test/CodeGen/SPARC/reg64.ll diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 05c6cce1..a6d440f 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -3258,6 +3258,8 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'r': if (VT == MVT::v2i32) return std::make_pair(0U, &SP::IntPairRegClass); + else if (Subtarget->is64Bit()) + return std::make_pair(0U, &SP::I64RegsRegClass); else return std::make_pair(0U, &SP::IntRegsRegClass); case 'f': diff --git a/llvm/test/CodeGen/SPARC/reg64.ll b/llvm/test/CodeGen/SPARC/reg64.ll new file mode 100644 index 0000000..74f4d46 --- /dev/null +++ b/llvm/test/CodeGen/SPARC/reg64.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -march=sparcv9 | FileCheck %s + +define dso_local zeroext i32 @f() local_unnamed_addr { +entry: + %0 = tail call i64 asm "", "=r"() + %shr = lshr i64 %0, 32 + %conv = trunc i64 %shr to i32 + ret i32 %conv +} +; CHECK: srlx -- 2.7.4