From 6e58c6d86d6bd6f6e1f9805285e905f40773b029 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Mon, 21 Jan 2013 20:42:16 +0000 Subject: [PATCH] Add instruction encoding / disassembly support for ru6 / lru6 instructions. llvm-svn: 173085 --- .../XCore/Disassembler/XCoreDisassembler.cpp | 10 ++ llvm/lib/Target/XCore/XCoreInstrFormats.td | 18 ++- llvm/lib/Target/XCore/XCoreInstrInfo.td | 163 +++++++++------------ llvm/test/MC/Disassembler/XCore/xcore.txt | 80 ++++++++++ 4 files changed, 177 insertions(+), 94 deletions(-) diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index d24d947..e6861bf 100644 --- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -92,6 +92,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder); + static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -192,6 +195,13 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, return MCDisassembler::Success; } +static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val, + uint64_t Address, const void *Decoder) { + Inst.addOperand(MCOperand::CreateImm(Val)); + Inst.addOperand(MCOperand::CreateImm(0)); + return MCDisassembler::Success; +} + static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) { unsigned Combined = fieldFromInstruction(Insn, 6, 5); diff --git a/llvm/lib/Target/XCore/XCoreInstrFormats.td b/llvm/lib/Target/XCore/XCoreInstrFormats.td index 01ed5cb..fa5c0a2 100644 --- a/llvm/lib/Target/XCore/XCoreInstrFormats.td +++ b/llvm/lib/Target/XCore/XCoreInstrFormats.td @@ -85,12 +85,26 @@ class _FL2RUSBitp opc, dag outs, dag ins, string asmstr, let DecoderMethod = "DecodeL2RUSBitpInstruction"; } -class _FRU6 pattern> +class _FRU6 opc, dag outs, dag ins, string asmstr, list pattern> : InstXCore<2, outs, ins, asmstr, pattern> { + bits<4> a; + bits<6> b; + + let Inst{15-10} = opc; + let Inst{9-6} = a; + let Inst{5-0} = b; } -class _FLRU6 pattern> +class _FLRU6 opc, dag outs, dag ins, string asmstr, list pattern> : InstXCore<4, outs, ins, asmstr, pattern> { + bits<4> a; + bits<16> b; + + let Inst{31-26} = opc; + let Inst{25-22} = a; + let Inst{21-16} = b{5-0}; + let Inst{15-10} = 0b111100; + let Inst{9-0} = b{15-6}; } class _FU6 pattern> diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index 20bdad2..5ca2b0f 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -182,6 +182,7 @@ def ADDRcpii : ComplexPattern { let PrintMethod = "printMemOperand"; + let DecoderMethod = "DecodeMEMiiOperand"; let MIOperandInfo = (ops i32imm, i32imm); } @@ -265,26 +266,25 @@ class FL3R opc, string OpcStr, SDNode OpNode> : // Register - U6 // Operand register - U6 -multiclass FRU6_LRU6_branch { - def _ru6: _FRU6< - (outs), (ins GRRegs:$cond, brtarget:$dest), - !strconcat(OpcStr, " $cond, $dest"), - []>; - def _lru6: _FLRU6< - (outs), (ins GRRegs:$cond, brtarget:$dest), - !strconcat(OpcStr, " $cond, $dest"), - []>; +multiclass FRU6_LRU6_branch opc, string OpcStr> { + def _ru6: _FRU6; + def _lru6: _FLRU6; } -multiclass FRU6_LRU6_cp { - def _ru6: _FRU6< - (outs GRRegs:$dst), (ins i32imm:$a), - !strconcat(OpcStr, " $dst, cp[$a]"), - []>; - def _lru6: _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$a), - !strconcat(OpcStr, " $dst, cp[$a]"), - []>; +multiclass FRU6_LRU6_backwards_branch opc, string OpcStr> { + def _ru6: _FRU6; + def _lru6: _FLRU6; +} + +multiclass FRU6_LRU6_cp opc, string OpcStr> { + def _ru6: _FRU6; + def _lru6: _FLRU6; } // U6 @@ -537,113 +537,92 @@ def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), //let Uses = [DP] in ... let neverHasSideEffects = 1, isReMaterializable = 1 in -def LDAWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), - "ldaw $dst, dp[$a]", - []>; +def LDAWDP_ru6: _FRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b), + "ldaw $a, dp[$b]", []>; let isReMaterializable = 1 in -def LDAWDP_lru6: _FLRU6< - (outs GRRegs:$dst), (ins MEMii:$a), - "ldaw $dst, dp[$a]", - [(set GRRegs:$dst, ADDRdpii:$a)]>; +def LDAWDP_lru6: _FLRU6<0b011000, (outs GRRegs:$a), (ins MEMii:$b), + "ldaw $a, dp[$b]", + [(set GRRegs:$a, ADDRdpii:$b)]>; let mayLoad=1 in -def LDWDP_ru6: _FRU6<(outs GRRegs:$dst), (ins MEMii:$a), - "ldw $dst, dp[$a]", - []>; - -def LDWDP_lru6: _FLRU6< - (outs GRRegs:$dst), (ins MEMii:$a), - "ldw $dst, dp[$a]", - [(set GRRegs:$dst, (load ADDRdpii:$a))]>; +def LDWDP_ru6: _FRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b), + "ldw $a, dp[$b]", []>; + +def LDWDP_lru6: _FLRU6<0b010110, (outs GRRegs:$a), (ins MEMii:$b), + "ldw $a, dp[$b]", + [(set GRRegs:$a, (load ADDRdpii:$b))]>; let mayStore=1 in -def STWDP_ru6 : _FRU6<(outs), (ins GRRegs:$val, MEMii:$addr), - "stw $val, dp[$addr]", - []>; +def STWDP_ru6 : _FRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b), + "stw $a, dp[$b]", []>; -def STWDP_lru6 : _FLRU6<(outs), (ins GRRegs:$val, MEMii:$addr), - "stw $val, dp[$addr]", - [(store GRRegs:$val, ADDRdpii:$addr)]>; +def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins GRRegs:$a, MEMii:$b), + "stw $a, dp[$b]", + [(store GRRegs:$a, ADDRdpii:$b)]>; //let Uses = [CP] in .. let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in -defm LDWCP : FRU6_LRU6_cp<"ldw">; +defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">; let Uses = [SP] in { let mayStore=1 in { -def STWSP_ru6 : _FRU6< - (outs), (ins GRRegs:$val, i32imm:$index), - "stw $val, sp[$index]", - [(XCoreStwsp GRRegs:$val, immU6:$index)]>; - -def STWSP_lru6 : _FLRU6< - (outs), (ins GRRegs:$val, i32imm:$index), - "stw $val, sp[$index]", - [(XCoreStwsp GRRegs:$val, immU16:$index)]>; +def STWSP_ru6 : _FRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b), + "stw $a, sp[$b]", + [(XCoreStwsp GRRegs:$a, immU6:$b)]>; + +def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins GRRegs:$a, i32imm:$b), + "stw $a, sp[$b]", + [(XCoreStwsp GRRegs:$a, immU16:$b)]>; } let mayLoad=1 in { -def LDWSP_ru6 : _FRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldw $dst, sp[$b]", - []>; +def LDWSP_ru6 : _FRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b), + "ldw $a, sp[$b]", []>; -def LDWSP_lru6 : _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldw $dst, sp[$b]", - []>; +def LDWSP_lru6 : _FLRU6<0b010111, (outs GRRegs:$a), (ins i32imm:$b), + "ldw $a, sp[$b]", []>; } let neverHasSideEffects = 1 in { -def LDAWSP_ru6 : _FRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; +def LDAWSP_ru6 : _FRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b), + "ldaw $a, sp[$b]", []>; -def LDAWSP_lru6 : _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; +def LDAWSP_lru6 : _FLRU6<0b011001, (outs GRRegs:$a), (ins i32imm:$b), + "ldaw $a, sp[$b]", []>; -def LDAWSP_ru6_RRegs : _FRU6< - (outs RRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; +let isCodeGenOnly = 1 in +def LDAWSP_ru6_RRegs : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), + "ldaw $a, sp[$b]", []>; -def LDAWSP_lru6_RRegs : _FLRU6< - (outs RRegs:$dst), (ins i32imm:$b), - "ldaw $dst, sp[$b]", - []>; +let isCodeGenOnly = 1 in +def LDAWSP_lru6_RRegs : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b), + "ldaw $a, sp[$b]", []>; } } let isReMaterializable = 1 in { -def LDC_ru6 : _FRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldc $dst, $b", - [(set GRRegs:$dst, immU6:$b)]>; - -def LDC_lru6 : _FLRU6< - (outs GRRegs:$dst), (ins i32imm:$b), - "ldc $dst, $b", - [(set GRRegs:$dst, immU16:$b)]>; +def LDC_ru6 : _FRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b), + "ldc $a, $b", [(set GRRegs:$a, immU6:$b)]>; + +def LDC_lru6 : _FLRU6<0b011010, (outs GRRegs:$a), (ins i32imm:$b), + "ldc $a, $b", [(set GRRegs:$a, immU16:$b)]>; } -def SETC_ru6 : _FRU6<(outs), (ins GRRegs:$r, i32imm:$val), - "setc res[$r], $val", - [(int_xcore_setc GRRegs:$r, immU6:$val)]>; +def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), + "setc res[$a], $b", + [(int_xcore_setc GRRegs:$a, immU6:$b)]>; -def SETC_lru6 : _FLRU6<(outs), (ins GRRegs:$r, i32imm:$val), - "setc res[$r], $val", - [(int_xcore_setc GRRegs:$r, immU16:$val)]>; +def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b), + "setc res[$a], $b", + [(int_xcore_setc GRRegs:$a, immU16:$b)]>; // Operand register - U6 let isBranch = 1, isTerminator = 1 in { -defm BRFT: FRU6_LRU6_branch<"bt">; -defm BRBT: FRU6_LRU6_branch<"bt">; -defm BRFF: FRU6_LRU6_branch<"bf">; -defm BRBF: FRU6_LRU6_branch<"bf">; +defm BRFT: FRU6_LRU6_branch<0b011100, "bt">; +defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">; +defm BRFF: FRU6_LRU6_branch<0b011110, "bf">; +defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">; } // U6 diff --git a/llvm/test/MC/Disassembler/XCore/xcore.txt b/llvm/test/MC/Disassembler/XCore/xcore.txt index 7b5d5123..507c762 100644 --- a/llvm/test/MC/Disassembler/XCore/xcore.txt +++ b/llvm/test/MC/Disassembler/XCore/xcore.txt @@ -312,3 +312,83 @@ # CHECK: ldaw r8, r2[-9] 0x09 0xfd 0xec 0xa7 + +# ru6 / lru6 instructions + +# CHECK: bt r6, -5 +0x85 0x75 + +# CHECK: bt r10, -451 +0x07 0xf0 0x83 0x76 + +# CHECK: bt r8, 10 +0x0a 0x72 + +# CHECK: bt r1, 6451 +0x64 0xf0 0x73 0x70 + +# CHECK: bf r5, 8 +0x48 0x79 + +# CHECK: bf r6, 65 +0x01 0xf0 0x81 0x79 + +# CHECK: bf r1, 53 +0x75 0x78 + +# CHECK: bf r10, 101 +0x01 0xf0 0xa5 0x7a + +# CHECK: ldaw r11, dp[63] +0xff 0x62 + +# CHECK: ldaw r1, dp[456] +0x07 0xf0 0x48 0x60 + +# CHECK: ldaw r3, sp[2] +0xc2 0x64 + +# CHECK: ldaw r8, sp[65535] +0xff 0xf3 0x3f 0x66 + +# CHECK: ldc r3, 30 +0xde 0x68 + +# CHECK: ldc r11, 1000 +0x0f 0xf0 0xe8 0x6a + +# CHECK: ldw r0, cp[4] +0x04 0x6c + +# CHECK: ldw r1, cp[32345] +0xf9 0xf1 0x59 0x6c + +# CHECK: ldw r10, dp[16] +0x90 0x5a + +# CHECK: ldw r10, dp[76] +0x01 0xf0 0x8c 0x5a + +# CHECK: ldw r8, sp[51] +0x33 0x5e + +# CHECK: ldw r8, sp[1225] +0x13 0xf0 0x09 0x5e + +# CHECK: setc res[r5], 36 +0x64 0xe9 + +# CHECK: setc res[r2], 40312 +0x75 0xf2 0xb8 0xe8 + +# CHECK: stw r8, dp[14] +0x0e 0x52 + +# CHECK: stw r9, dp[654] +0x0a 0xf0 0x4e 0x52 + +# CHECK: stw r1, sp[32] +0x60 0x54 + +# CHECK: stw r0, sp[8761] +0x88 0xf0 0x39 0x54 -- 2.7.4