From 6e4f7e14af9135a9e680f3915002dbb8cb7a0beb Mon Sep 17 00:00:00 2001 From: =?utf8?q?J=C3=A9r=C3=B4me=20Glisse?= Date: Thu, 9 Aug 2018 15:32:01 -0400 Subject: [PATCH] nouveau: add support for SVM migrate MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit v2 (Ralph): don't allign address as the kernel handles that already support migration from GPU to system RAM v3 (Karol): use DIV_ROUND_UP for sizes not being page aligned Signed-off-by: Jérôme Glisse Signed-off-by: Karol Herbst Reviewed-by: Francisco Jerez Part-of: --- .../drivers/nouveau/nvc0/nvc0_context.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c index 5f184e57fcb..8bae491e526 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.c @@ -28,6 +28,53 @@ #include "nvc0/nvc0_screen.h" #include "nvc0/nvc0_resource.h" + +#include "xf86drm.h" +#include "nouveau_drm.h" + + +static void +nvc0_svm_migrate(struct pipe_context *pipe, unsigned num_ptrs, + const void* const* ptrs, const size_t *sizes, + bool to_device, bool mem_undefined) +{ + struct nvc0_context *nvc0 = nvc0_context(pipe); + struct nouveau_screen *screen = &nvc0->screen->base; + int fd = screen->drm->fd; + unsigned i; + + for (i = 0; i < num_ptrs; i++) { + struct drm_nouveau_svm_bind args; + uint64_t cmd, prio, target; + + args.va_start = (uint64_t)(uintptr_t)ptrs[i]; + if (sizes && sizes[i]) { + args.va_end = (uint64_t)(uintptr_t)ptrs[i] + sizes[i]; + args.npages = DIV_ROUND_UP(args.va_end - args.va_start, 0x1000); + } else { + args.va_end = 0; + args.npages = 0; + } + args.stride = 0; + + args.reserved0 = 0; + args.reserved1 = 0; + + prio = 0; + cmd = NOUVEAU_SVM_BIND_COMMAND__MIGRATE; + target = to_device ? NOUVEAU_SVM_BIND_TARGET__GPU_VRAM : 0; + + args.header = cmd << NOUVEAU_SVM_BIND_COMMAND_SHIFT; + args.header |= prio << NOUVEAU_SVM_BIND_PRIORITY_SHIFT; + args.header |= target << NOUVEAU_SVM_BIND_TARGET_SHIFT; + + /* This is best effort, so no garanty whatsoever */ + drmCommandWrite(fd, DRM_NOUVEAU_SVM_BIND, + &args, sizeof(args)); + } +} + + static void nvc0_flush(struct pipe_context *pipe, struct pipe_fence_handle **fence, @@ -408,6 +455,8 @@ nvc0_create(struct pipe_screen *pscreen, void *priv, unsigned ctxflags) pipe->launch_grid = (nvc0->screen->base.class_3d >= NVE4_3D_CLASS) ? nve4_launch_grid : nvc0_launch_grid; + pipe->svm_migrate = nvc0_svm_migrate; + pipe->flush = nvc0_flush; pipe->texture_barrier = nvc0_texture_barrier; pipe->memory_barrier = nvc0_memory_barrier; -- 2.34.1