From 6e4be7e12a0010c09c56c781d9c3d6118cea69ac Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 27 Jun 2023 09:39:05 -0700 Subject: [PATCH] [RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines. Make Zcf/Zcd depend on Zca. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D153826 --- llvm/lib/Target/RISCV/RISCVFeatures.td | 6 ++-- llvm/test/CodeGen/RISCV/attributes.ll | 6 ++-- llvm/test/CodeGen/RISCV/compress-double.ll | 40 ++++++++++++++++++++++++++ llvm/test/CodeGen/RISCV/compress-float.ll | 45 +++++++++++++++++++----------- 4 files changed, 76 insertions(+), 21 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/compress-double.ll diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index d5f2c16..806268e 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -344,7 +344,8 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, def FeatureStdExtZcd : SubtargetFeature<"zcd", "HasStdExtZcd", "true", - "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; + "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", + [FeatureStdExtZca]>; def HasStdExtCOrZcd : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcd()">, @@ -354,7 +355,8 @@ def HasStdExtCOrZcd def FeatureStdExtZcf : SubtargetFeature<"zcf", "HasStdExtZcf", "true", - "'Zcf' (Compressed Single-Precision Floating-Point Instructions)">; + "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", + [FeatureStdExtZca]>; def HasStdExtCOrZcf : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf()">, diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 0c35be0..5911e27 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -219,8 +219,8 @@ ; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0" ; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0" ; RV32ZCB: .attribute 5, "rv32i2p1_zca1p0_zcb1p0" -; RV32ZCD: .attribute 5, "rv32i2p1_zcd1p0" -; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0" +; RV32ZCD: .attribute 5, "rv32i2p1_zca1p0_zcd1p0" +; RV32ZCF: .attribute 5, "rv32i2p1_zca1p0_zcf1p0" ; RV32ZCMP: .attribute 5, "rv32i2p1_zca1p0_zcmp1p0" ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0" @@ -306,7 +306,7 @@ ; RV64ZTSO: .attribute 5, "rv64i2p1_ztso0p1" ; RV64ZCA: .attribute 5, "rv64i2p1_zca1p0" ; RV64ZCB: .attribute 5, "rv64i2p1_zca1p0_zcb1p0" -; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0" +; RV64ZCD: .attribute 5, "rv64i2p1_zca1p0_zcd1p0" ; RV64ZCMP: .attribute 5, "rv64i2p1_zca1p0_zcmp1p0" ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0" ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0" diff --git a/llvm/test/CodeGen/RISCV/compress-double.ll b/llvm/test/CodeGen/RISCV/compress-double.ll new file mode 100644 index 0000000..e212bc0 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/compress-double.ll @@ -0,0 +1,40 @@ +; This test is designed to run three times, once with function attributes, once +; with all target attributes added on the command line, and once with compress +; added with the command line and float added via function attributes, all +; three of these should result in the same output. +; +; RUN: cat %s > %t.tgtattr +; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zcd,+d -filetype=obj \ +; RUN: -disable-block-placement < %t.tgtattr \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s +; +; RUN: cat %s > %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcd,+d" }' >> %t.fnattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \ +; RUN: -disable-block-placement < %t.fnattr \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s +; +; RUN: cat %s > %t.mixedattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+d" }' >> %t.mixedattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zcd -filetype=obj \ +; RUN: -disable-block-placement < %t.mixedattr \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcd,+d -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s + +; This acts as a basic correctness check for the codegen instruction compression +; path, verifying that the assembled file contains compressed instructions when +; expected. Handling of the compressed ISA is implemented so the same +; transformation patterns should be used whether compressing an input .s file or +; compressing codegen output. This file contains basic functionality tests using +; instructions which also require one of the floating point extensions. + +define double @double_load(ptr %a) #0 { +; RV32IFDC-LABEL: : +; RV32IFDC: c.fld fa0, 0(a0) +; RV32IFDC-NEXT: c.jr ra + %1 = load volatile double, ptr %a + ret double %1 +} diff --git a/llvm/test/CodeGen/RISCV/compress-float.ll b/llvm/test/CodeGen/RISCV/compress-float.ll index 3ff4f74..4e0ecaf 100644 --- a/llvm/test/CodeGen/RISCV/compress-float.ll +++ b/llvm/test/CodeGen/RISCV/compress-float.ll @@ -5,23 +5,44 @@ ; ; RUN: cat %s > %t.tgtattr ; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d -filetype=obj \ +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c,+f -filetype=obj \ ; RUN: -disable-block-placement < %t.tgtattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; ; RUN: cat %s > %t.fnattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f,+d" }' >> %t.fnattr -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -filetype=obj \ +; RUN: echo 'attributes #0 = { nounwind "target-features"="+c,+f" }' >> %t.fnattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \ ; RUN: -disable-block-placement < %t.fnattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; ; RUN: cat %s > %t.mixedattr -; RUN: echo 'attributes #0 = { nounwind "target-features"="+f,+d" }' >> %t.mixedattr -; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c -filetype=obj \ +; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+c -filetype=obj \ ; RUN: -disable-block-placement < %t.mixedattr \ -; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f,+d -M no-aliases - \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+c,+f -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s +; +; RUN: cat %s > %t.tgtattr +; RUN: echo 'attributes #0 = { nounwind }' >> %t.tgtattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf,+f -filetype=obj \ +; RUN: -disable-block-placement < %t.tgtattr \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s +; +; RUN: cat %s > %t.fnattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+zcf,+f" }' >> %t.fnattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -filetype=obj \ +; RUN: -disable-block-placement < %t.fnattr \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \ +; RUN: | FileCheck -check-prefix=RV32IFDC %s +; +; RUN: cat %s > %t.mixedattr +; RUN: echo 'attributes #0 = { nounwind "target-features"="+f" }' >> %t.mixedattr +; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zcf -filetype=obj \ +; RUN: -disable-block-placement < %t.mixedattr \ +; RUN: | llvm-objdump -d --triple=riscv32 --mattr=+zcf,+f -M no-aliases - \ ; RUN: | FileCheck -check-prefix=RV32IFDC %s ; This acts as a basic correctness check for the codegen instruction compression @@ -38,11 +59,3 @@ define float @float_load(ptr %a) #0 { %1 = load volatile float, ptr %a ret float %1 } - -define double @double_load(ptr %a) #0 { -; RV32IFDC-LABEL: : -; RV32IFDC: c.fld fa0, 0(a0) -; RV32IFDC-NEXT: c.jr ra - %1 = load volatile double, ptr %a - ret double %1 -} -- 2.7.4