From 6e339418a721467043d42b1ebb98df0201391535 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 29 Sep 2020 17:05:57 +0200 Subject: [PATCH] radv/llvm: lower GS IO The LLVM bakend expects 64-bit IO to be lowered to 32-bit but it's unclear if we want to do that for ACO at this point. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_nir_to_llvm.c | 10 +++++----- src/amd/vulkan/radv_shader.c | 11 +++++++++-- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 328a8d2..414383f 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -741,18 +741,18 @@ load_gs_input(struct ac_shader_abi *abi, vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param], LLVMConstInt(ctx->ac.i32, 4, false), ""); - param = shader_io_get_unique_index(location); + param = shader_io_get_unique_index(driver_location / 4); for (unsigned i = component; i < num_components + component; i++) { if (ctx->ac.chip_class >= GFX9) { LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param]; dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, - LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), ""); + LLVMConstInt(ctx->ac.i32, param * 4 + i, 0), ""); value[i] = ac_lds_load(&ctx->ac, dw_addr); if (ac_get_type_size(type) == 8) { dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, - LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), ""); + LLVMConstInt(ctx->ac.i32, param * 4 + i + 1, 0), ""); LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr); value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp); @@ -760,7 +760,7 @@ load_gs_input(struct ac_shader_abi *abi, } else { LLVMValueRef soffset = LLVMConstInt(ctx->ac.i32, - (param * 4 + i + const_index) * 256, + (param * 4 + i) * 256, false); value[i] = ac_build_buffer_load(&ctx->ac, @@ -771,7 +771,7 @@ load_gs_input(struct ac_shader_abi *abi, if (ac_get_type_size(type) == 8) { soffset = LLVMConstInt(ctx->ac.i32, - (param * 4 + i + const_index + 1) * 256, + (param * 4 + i + 1) * 256, false); LLVMValueRef tmp = diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index d464daa..78c9eb9 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -761,7 +761,9 @@ radv_lower_io(struct radv_device *device, nir_shader *nir) return; /* TODO: Lower IO for all stages with LLVM. */ - if (nir->info.stage != MESA_SHADER_FRAGMENT && + if ((nir->info.stage == MESA_SHADER_VERTEX || + nir->info.stage == MESA_SHADER_TESS_CTRL || + nir->info.stage == MESA_SHADER_TESS_EVAL) && radv_use_llvm_for_stage(device, nir->info.stage)) return; @@ -771,7 +773,12 @@ radv_lower_io(struct radv_device *device, nir_shader *nir) MESA_SHADER_FRAGMENT); } - NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4, 0); + /* The RADV/LLVM backend expects 64-bit IO to be lowered. */ + nir_lower_io_options options = + radv_use_llvm_for_stage(device, nir->info.stage) ? nir_lower_io_lower_64bit_to_32 : 0; + + NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out, + type_size_vec4, options); /* This pass needs actual constants */ nir_opt_constant_folding(nir); -- 2.7.4