From 6de128380fd6fe3db99ee655f003ab109f6a2048 Mon Sep 17 00:00:00 2001 From: rth Date: Mon, 23 Jul 2001 21:16:02 +0000 Subject: [PATCH] * config/i386/i386.c (ix86_expand_setcc): Don't use method 0 before CSE. * config/i386/i386.md: New setcc+movzbl peephole2. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@44279 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 6 ++++++ gcc/config/i386/i386.c | 7 +++++-- gcc/config/i386/i386.md | 19 +++++++++++++++++++ 3 files changed, 30 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 697b11a..e2437a2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2001-07-23 Richard Henderson + + * config/i386/i386.c (ix86_expand_setcc): Don't use method 0 + before CSE. + * config/i386/i386.md: New setcc+movzbl peephole2. + 2001-07-23 Neil Booth * objc/Make-lang.in (objc-act.o): Depend on debug.h. diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 821daa6..725a984 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -6357,9 +6357,12 @@ ix86_expand_setcc (code, dest) emit subreg setcc, zero extend. 2 -- destination is in QImode: emit setcc only. - */ - type = 0; + We don't use mode 0 early in compilation because it confuses CSE. + There are peepholes to turn mode 1 into mode 0 if things work out + nicely after reload. */ + + type = cse_not_expected ? 0 : 1; if (GET_MODE (dest) == QImode) type = 2; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index d2ff08b..7f84549 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -13133,6 +13133,25 @@ (match_dup 0) (pc)))] "") + +;; Convert setcc + movzbl to xor + setcc if operands don't overlap. + +(define_peephole2 + [(set (reg 17) (match_operand 0 "" "")) + (set (match_operand:QI 1 "register_operand" "") + (match_operator:QI 2 "ix86_comparison_operator" + [(reg 17) (const_int 0)])) + (set (match_operand 3 "q_regs_operand" "") + (zero_extend (match_dup 1)))] + "peep2_reg_dead_p (3, operands[1]) + && ! reg_overlap_mentioned_p (operands[3], operands[0])" + [(parallel [(set (match_dup 3) (const_int 0)) + (clobber (reg:CC 17))]) + (set (match_dup 4) (match_dup 0)) + (set (strict_low_part (match_dup 5)) + (match_dup 2))] + "operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17); + operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));") ;; Call instructions. -- 2.7.4