From 6dd5b4ca5f1ba405cc210b9800c5f7db592e4309 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 6 Mar 2023 10:35:22 -0800 Subject: [PATCH] freedreno/registers: Fix nameless fields Originally if we had an anonymous field (ie. field declared as part of the register definition itself) the name in the generated field struct would include the gen prefix (ie. .a6xx_rb_stencil_buffer_pitch), but this doesn't work for variants because the variant regs would have different gen prefixes. Fix this by using reg name instead of the full_name. Signed-off-by: Rob Clark Part-of: --- src/freedreno/registers/gen_header.py | 19 ++++++++++--------- src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc | 25 +++++++++++-------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/src/freedreno/registers/gen_header.py b/src/freedreno/registers/gen_header.py index 354f380..4c2e431 100644 --- a/src/freedreno/registers/gen_header.py +++ b/src/freedreno/registers/gen_header.py @@ -108,11 +108,13 @@ def tab_to(name, value): def mask(low, high): return ((0xffffffffffffffff >> (64 - (high + 1 - low))) << low) -def field_name(prefix, f): +def field_name(reg, f): if f.name: name = f.name.lower() else: - name = prefix.lower() + # We hit this path when a reg is defined with no bitset fields, ie. + # + name = reg.name.lower() if (name in [ "double", "float", "int" ]) or not (name[0].isalpha()): name = "_" + name @@ -136,30 +138,29 @@ class Bitset(object): return None def dump_regpair_builder(self, reg): - prefix = reg.full_name print("#ifndef NDEBUG") known_mask = 0 for f in self.fields: known_mask |= mask(f.low, f.high) if f.type in [ "boolean", "address", "waddress" ]: continue - type, val = f.ctype("fields.%s" % field_name(prefix, f)) + type, val = f.ctype("fields.%s" % field_name(reg, f)) print(" assert((%-40s & 0x%08x) == 0);" % (val, 0xffffffff ^ mask(0 , f.high - f.low))) print(" assert((%-40s & 0x%08x) == 0);" % ("fields.unknown", known_mask)) print("#endif\n") print(" return (struct fd_reg_pair) {") if reg.array: - print(" .reg = REG_%s(__i)," % prefix) + print(" .reg = REG_%s(__i)," % reg.full_name) else: - print(" .reg = REG_%s," % prefix) + print(" .reg = REG_%s," % reg.full_name) print(" .value =") for f in self.fields: if f.type in [ "address", "waddress" ]: continue else: - type, val = f.ctype("fields.%s" % field_name(prefix, f)) + type, val = f.ctype("fields.%s" % field_name(reg, f)) print(" (%-40s << %2d) |" % (val, f.low)) value_name = "dword" if reg.bit_size == 64: @@ -190,7 +191,7 @@ class Bitset(object): tab_to(" __bo_type", "bo;") tab_to(" uint32_t", "bo_offset;") continue - name = field_name(prefix, f) + name = field_name(reg, f) type, val = f.ctype("var") @@ -575,7 +576,7 @@ class Parser(object): bit_size = reg.bit_size array = reg.array for f in reg.bitset.fields: - fld_name = field_name(reg.full_name, f) + fld_name = field_name(reg, f) if fld_name in seen_fields: continue seen_fields.append(fld_name) diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc index a8c5c06..bfa7014 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc +++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc @@ -129,10 +129,10 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb, ring, A6XX_RB_MRT_BUF_INFO(i, .color_format = format, .color_tile_mode = tile_mode, .color_swap = swap), - A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride), - A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = array_stride), + A6XX_RB_MRT_PITCH(i, stride), + A6XX_RB_MRT_ARRAY_PITCH(i, array_stride), A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset), - A6XX_RB_MRT_BASE_GMEM(i, .unknown = base)); + A6XX_RB_MRT_BASE_GMEM(i, base)); OUT_REG(ring, A6XX_SP_FS_MRT_REG(i, .color_format = format, .color_sint = sint, .color_uint = uint)); @@ -170,11 +170,10 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf, OUT_REG( ring, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt), - A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride), - A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = - array_stride), + A6XX_RB_DEPTH_BUFFER_PITCH(stride), + A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(array_stride), A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset), - A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base)); + A6XX_RB_DEPTH_BUFFER_BASE_GMEM(base)); OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt)); @@ -211,12 +210,10 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf, fd_resource_offset(rsc->stencil, zsbuf->u.tex.level, zsbuf->u.tex.first_layer); OUT_REG(ring, A6XX_RB_STENCIL_INFO(.separate_stencil = true), - A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = - stride), - A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH( - .a6xx_rb_stencil_buffer_array_pitch = array_stride), + A6XX_RB_STENCIL_BUFFER_PITCH(stride), + A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(array_stride), A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo, .bo_offset = offset), - A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base)); + A6XX_RB_STENCIL_BUFFER_BASE_GMEM(base)); } else { OUT_REG(ring, A6XX_RB_STENCIL_INFO(0)); } @@ -1034,8 +1031,8 @@ emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring, uint32_t base, .color_format = format, ), A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset), - A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride), - A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = array_stride)); + A6XX_RB_BLIT_DST_PITCH(stride), + A6XX_RB_BLIT_DST_ARRAY_PITCH(array_stride)); OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base)); -- 2.7.4