From 6d06971da12fb1b8730257abbd49447760baed8d Mon Sep 17 00:00:00 2001 From: Kyrylo Tkachov Date: Thu, 16 Mar 2017 10:03:11 +0000 Subject: [PATCH] [AArch64] Use 'x' constraint for vector HFmode multiplication by indexed element instructions * config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF. * config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup): Use h_con constraint for operand 1. (*aarch64_fnma4_elt_from_dup): Likewise. (*aarch64_mulx_elt_from_dup): Likewise for operand 2. From-SVN: r246189 --- gcc/ChangeLog | 8 ++++++++ gcc/config/aarch64/aarch64-simd.md | 6 +++--- gcc/config/aarch64/iterators.md | 4 ++-- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 82ab3d7..e2e1015 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2017-03-16 Kyrylo Tkachov + + * config/aarch64/iterators.md (h_con): Return "x" for V4HF and V8HF. + * config/aarch64/aarch64-simd.md (*aarch64_fma4_elt_from_dup): + Use h_con constraint for operand 1. + (*aarch64_fnma4_elt_from_dup): Likewise. + (*aarch64_mulx_elt_from_dup): Likewise for operand 2. + 2017-03-15 Jeff Law PR tree-optimization/71437 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 7ad3a76..8a3a551 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1647,7 +1647,7 @@ [(set (match_operand:VMUL 0 "register_operand" "=w") (fma:VMUL (vec_duplicate:VMUL - (match_operand: 1 "register_operand" "w")) + (match_operand: 1 "register_operand" "")) (match_operand:VMUL 2 "register_operand" "w") (match_operand:VMUL 3 "register_operand" "0")))] "TARGET_SIMD" @@ -1726,7 +1726,7 @@ (neg:VMUL (match_operand:VMUL 2 "register_operand" "w")) (vec_duplicate:VMUL - (match_operand: 1 "register_operand" "w")) + (match_operand: 1 "register_operand" "")) (match_operand:VMUL 3 "register_operand" "0")))] "TARGET_SIMD" "fmls\t%0., %2., %1.[0]" @@ -3178,7 +3178,7 @@ (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand" "w") (vec_duplicate:VHSDF - (match_operand: 2 "register_operand" "w"))] + (match_operand: 2 "register_operand" ""))] UNSPEC_FMULX))] "TARGET_SIMD" "fmulx\t%0., %1., %2.[0]"; diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 1ddf6ad..43be7fd 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -749,11 +749,11 @@ (DF "to_128") (V2DF "to_64")]) ;; For certain vector-by-element multiplication instructions we must -;; constrain the HI cases to use only V0-V15. This is covered by +;; constrain the 16-bit cases to use only V0-V15. This is covered by ;; the 'x' constraint. All other modes may use the 'w' constraint. (define_mode_attr h_con [(V2SI "w") (V4SI "w") (V4HI "x") (V8HI "x") - (V4HF "w") (V8HF "w") + (V4HF "x") (V8HF "x") (V2SF "w") (V4SF "w") (V2DF "w") (DF "w")]) -- 2.7.4