From 6cda10c9503e7754feed72346c9dee7ef73a72d5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 7 Sep 2016 06:16:45 +0000 Subject: [PATCH] Remove unnecessary call to getAllocatableRegClass This reapplies r252565 and r252674, effectively reverting r252956. This allows VS_32/VS_64 to be unallocatable like they should be. llvm-svn: 280783 --- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 24 +++++++++++++++--------- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 7 ------- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 6 ++++-- 3 files changed, 19 insertions(+), 18 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index c8af73a..d760a70 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -330,16 +330,22 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, // shrink VReg's register class within reason. For example, if VReg == GR32 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. if (II) { - const TargetRegisterClass *DstRC = nullptr; + const TargetRegisterClass *OpRC = nullptr; if (IIOpNum < II->getNumOperands()) - DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); - assert((!DstRC || TargetRegisterInfo::isVirtualRegister(VReg)) && - "Expected VReg"); - if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { - unsigned NewVReg = MRI->createVirtualRegister(DstRC); - BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), - TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); - VReg = NewVReg; + OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); + + if (OpRC) { + const TargetRegisterClass *ConstrainedRC + = MRI->constrainRegClass(VReg, OpRC, MinRCSize); + if (!ConstrainedRC) { + unsigned NewVReg = MRI->createVirtualRegister(OpRC); + BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), + TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); + VReg = NewVReg; + } else { + assert(ConstrainedRC->isAllocatable() && + "Constraining an allocatable VReg produced an unallocatable class?"); + } } } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 59cec85..59952b4 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -107,13 +107,6 @@ public: /// \returns true if this class contains VGPR registers. bool hasVGPRs(const TargetRegisterClass *RC) const; - /// returns true if this is a pseudoregister class combination of VGPRs and - /// SGPRs for operand modeling. FIXME: We should set isAllocatable = 0 on - /// them. - static bool isPseudoRegClass(const TargetRegisterClass *RC) { - return RC == &AMDGPU::VS_32RegClass || RC == &AMDGPU::VS_64RegClass; - } - /// \returns A VGPR reg class with the same width as \p SRC const TargetRegisterClass *getEquivalentVGPRClass( const TargetRegisterClass *SRC) const; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td index adce99b..9332666 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.td +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.td @@ -346,10 +346,12 @@ def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> { let Size = 32; } -def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>; +def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)> { + let isAllocatable = 0; +} def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { - let CopyCost = 2; + let isAllocatable = 0; } //===----------------------------------------------------------------------===// -- 2.7.4