From 6cd780ff2143656df213359b7a6df9a5a9237e17 Mon Sep 17 00:00:00 2001 From: Benjamin Kramer Date: Tue, 17 Feb 2015 15:29:18 +0000 Subject: [PATCH] Prefer SmallVector::append/insert over push_back loops. Same functionality, but hoists the vector growth out of the loop. llvm-svn: 229500 --- llvm/lib/Analysis/ScalarEvolution.cpp | 3 +-- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 19 ++++++------------- llvm/lib/CodeGen/InlineSpiller.cpp | 4 ++-- llvm/lib/CodeGen/RegAllocPBQP.cpp | 3 +-- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++------ .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 8 ++------ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 20 +++++--------------- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 +--- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 3 +-- llvm/lib/IR/ConstantFold.cpp | 3 +-- llvm/lib/IR/DIBuilder.cpp | 13 +++++-------- llvm/lib/IR/DebugInfo.cpp | 14 +++++--------- llvm/lib/IR/Verifier.cpp | 3 +-- llvm/lib/Linker/LinkModules.cpp | 12 ++++-------- llvm/lib/Option/Arg.cpp | 12 ++++-------- llvm/lib/Option/ArgList.cpp | 4 ++-- llvm/lib/ProfileData/CoverageMapping.cpp | 8 ++++---- llvm/lib/Support/CommandLine.cpp | 4 +--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 10 ++-------- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 4 +--- llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 6 ++---- llvm/lib/Target/R600/R600ISelLowering.cpp | 9 ++------- llvm/lib/Target/R600/SIISelLowering.cpp | 20 ++++++-------------- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 7 ++----- llvm/lib/Target/X86/X86ISelLowering.cpp | 16 ++++------------ .../Transforms/Instrumentation/DataFlowSanitizer.cpp | 11 ++++------- llvm/lib/Transforms/Utils/LoopSimplify.cpp | 3 +-- 27 files changed, 72 insertions(+), 159 deletions(-) diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp index 9aefe8c..6edd862 100644 --- a/llvm/lib/Analysis/ScalarEvolution.cpp +++ b/llvm/lib/Analysis/ScalarEvolution.cpp @@ -2194,8 +2194,7 @@ static bool containsConstantSomewhere(const SCEV *StartExpr) { if (isa(*CurrentExpr) || isa(*CurrentExpr)) { const auto *CurrentNAry = cast(CurrentExpr); - for (const SCEV *Operand : CurrentNAry->operands()) - Ops.push_back(Operand); + Ops.append(CurrentNAry->op_begin(), CurrentNAry->op_end()); } } return false; diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp index 0a3c57e..c3b0dc8 100644 --- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -1099,8 +1099,7 @@ static void WriteMDExpression(const MDExpression *N, const ValueEnumerator &, Record.reserve(N->getElements().size() + 1); Record.push_back(N->isDistinct()); - for (uint64_t I : N->getElements()) - Record.push_back(I); + Record.append(N->elements_begin(), N->elements_end()); Stream.EmitRecord(bitc::METADATA_EXPRESSION, Record, Abbrev); Record.clear(); @@ -1395,14 +1394,12 @@ static void WriteConstants(unsigned FirstVal, unsigned LastVal, // Add the asm string. const std::string &AsmStr = IA->getAsmString(); Record.push_back(AsmStr.size()); - for (unsigned i = 0, e = AsmStr.size(); i != e; ++i) - Record.push_back(AsmStr[i]); + Record.append(AsmStr.begin(), AsmStr.end()); // Add the constraint string. const std::string &ConstraintStr = IA->getConstraintString(); Record.push_back(ConstraintStr.size()); - for (unsigned i = 0, e = ConstraintStr.size(); i != e; ++i) - Record.push_back(ConstraintStr[i]); + Record.append(ConstraintStr.begin(), ConstraintStr.end()); Stream.EmitRecord(bitc::CST_CODE_INLINEASM, Record); Record.clear(); continue; @@ -1691,8 +1688,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID, Code = bitc::FUNC_CODE_INST_EXTRACTVAL; PushValueAndType(I.getOperand(0), InstID, Vals, VE); const ExtractValueInst *EVI = cast(&I); - for (const unsigned *i = EVI->idx_begin(), *e = EVI->idx_end(); i != e; ++i) - Vals.push_back(*i); + Vals.append(EVI->idx_begin(), EVI->idx_end()); break; } case Instruction::InsertValue: { @@ -1700,8 +1696,7 @@ static void WriteInstruction(const Instruction &I, unsigned InstID, PushValueAndType(I.getOperand(0), InstID, Vals, VE); PushValueAndType(I.getOperand(1), InstID, Vals, VE); const InsertValueInst *IVI = cast(&I); - for (const unsigned *i = IVI->idx_begin(), *e = IVI->idx_end(); i != e; ++i) - Vals.push_back(*i); + Vals.append(IVI->idx_begin(), IVI->idx_end()); break; } case Instruction::Select: @@ -2037,9 +2032,7 @@ static void WriteUseList(ValueEnumerator &VE, UseListOrder &&Order, else Code = bitc::USELIST_CODE_DEFAULT; - SmallVector Record; - for (unsigned I : Order.Shuffle) - Record.push_back(I); + SmallVector Record(Order.Shuffle.begin(), Order.Shuffle.end()); Record.push_back(VE.getValueID(Order.V)); Stream.EmitRecord(Code, Record); } diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index 631b42c..f0d407f 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -576,8 +576,8 @@ MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI, std::tie(SVI, Inserted) = SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI))); // Add all the PHIs as dependents of NonPHI. - for (unsigned pi = 0, pe = PHIs.size(); pi != pe; ++pi) - SVI->second.Deps.push_back(PHIs[pi]); + SVI->second.Deps.insert(SVI->second.Deps.end(), PHIs.begin(), + PHIs.end()); // This is the first time we see NonPHI, add it to the worklist. if (Inserted) WorkList.push_back(std::make_pair(Reg, NonPHI)); diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index bdc669c..77a42b3 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -545,8 +545,7 @@ void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, if (VRegAllowed.empty()) { SmallVector NewVRegs; spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller); - for (auto NewVReg : NewVRegs) - Worklist.push_back(NewVReg); + Worklist.insert(Worklist.end(), NewVRegs.begin(), NewVRegs.end()); continue; } diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index c4a1a1f..92164e9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6913,8 +6913,7 @@ ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { - for (unsigned j = 0; j != NumOutputsPerInput; ++j) - Ops.push_back(DAG.getUNDEF(DstEltVT)); + Ops.append(NumOutputsPerInput, DAG.getUNDEF(DstEltVT)); continue; } @@ -11754,10 +11753,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { // constants directly. const SDValue &Splatted = V->getOperand(SVN->getSplatIndex()); if (isa(Splatted) || isa(Splatted)) { - SmallVector Ops; - for (unsigned i = 0; i != NumElts; ++i) { - Ops.push_back(Splatted); - } + SmallVector Ops(NumElts, Splatted); SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), V->getValueType(0), Ops); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index a4e44cc..5507c70 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -3017,17 +3017,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) { EVT VT = N->getValueType(0); SDLoc dl(N); - unsigned NumElts = VT.getVectorNumElements(); - SmallVector NewMask; - for (unsigned i = 0; i != NumElts; ++i) { - NewMask.push_back(SV->getMaskElt(i)); - } + ArrayRef NewMask = SV->getMask().slice(0, VT.getVectorNumElements()); SDValue V0 = GetPromotedInteger(N->getOperand(0)); SDValue V1 = GetPromotedInteger(N->getOperand(1)); EVT OutVT = V0.getValueType(); - return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]); + return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask); } diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index f2b18fc..3853ada 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -137,13 +137,9 @@ static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, } // Helper for AddGlue to clone node operands. -static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, - SmallVectorImpl &VTs, +static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, ArrayRef VTs, SDValue ExtraOper = SDValue()) { - SmallVector Ops; - for (unsigned I = 0, E = N->getNumOperands(); I != E; ++I) - Ops.push_back(N->getOperand(I)); - + SmallVector Ops(N->op_begin(), N->op_end()); if (ExtraOper.getNode()) Ops.push_back(ExtraOper); @@ -165,7 +161,6 @@ static void CloneNodeWithValues(SDNode *N, SelectionDAG *DAG, } static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { - SmallVector VTs; SDNode *GlueDestNode = Glue.getNode(); // Don't add glue from a node to itself. @@ -179,9 +174,7 @@ static bool AddGlue(SDNode *N, SDValue Glue, bool AddGlue, SelectionDAG *DAG) { // Don't add glue to something that already has a glue value. if (N->getValueType(N->getNumValues() - 1) == MVT::Glue) return false; - for (unsigned I = 0, E = N->getNumValues(); I != E; ++I) - VTs.push_back(N->getValueType(I)); - + SmallVector VTs(N->value_begin(), N->value_end()); if (AddGlue) VTs.push_back(MVT::Glue); @@ -197,11 +190,8 @@ static void RemoveUnusedGlue(SDNode *N, SelectionDAG *DAG) { !N->hasAnyUseOfValue(N->getNumValues() - 1)) && "expected an unused glue value"); - SmallVector VTs; - for (unsigned I = 0, E = N->getNumValues()-1; I != E; ++I) - VTs.push_back(N->getValueType(I)); - - CloneNodeWithValues(N, DAG, VTs); + CloneNodeWithValues(N, DAG, + makeArrayRef(N->value_begin(), N->getNumValues() - 1)); } /// ClusterNeighboringLoads - Force nearby loads together by "gluing" them. diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index e443dcc..1e0e196 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1586,9 +1586,7 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, if (AllSame && SameNumElts) { const SDValue &Splatted = BV->getOperand(MaskVec[0]); if (isa(Splatted) || isa(Splatted)) { - SmallVector Ops; - for (unsigned i = 0; i != NElts; ++i) - Ops.push_back(Splatted); + SmallVector Ops(NElts, Splatted); SDValue NewBV = getNode(ISD::BUILD_VECTOR, dl, BV->getValueType(0), Ops); diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 4c26d37..139ba3b 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7264,8 +7264,7 @@ void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS, // Push the arguments from the call instruction up to the register mask. SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1; - for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i) - Ops.push_back(*i); + Ops.append(Call->op_begin() + 2, e); // Push live variables for the stack map. addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this); diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp index 16ecf1c..a915d28 100644 --- a/llvm/lib/IR/ConstantFold.cpp +++ b/llvm/lib/IR/ConstantFold.cpp @@ -2079,8 +2079,7 @@ static Constant *ConstantFoldGetElementPtrImpl(Constant *C, if (PerformFold) { SmallVector NewIndices; NewIndices.reserve(Idxs.size() + CE->getNumOperands()); - for (unsigned i = 1, e = CE->getNumOperands()-1; i != e; ++i) - NewIndices.push_back(CE->getOperand(i)); + NewIndices.append(CE->op_begin() + 1, CE->op_end() - 1); // Add the last index of the source with the first index of the new GEP. // Make sure to handle the case when they are actually different types. diff --git a/llvm/lib/IR/DIBuilder.cpp b/llvm/lib/IR/DIBuilder.cpp index 35583db..7ff7c38 100644 --- a/llvm/lib/IR/DIBuilder.cpp +++ b/llvm/lib/IR/DIBuilder.cpp @@ -94,9 +94,8 @@ void DIBuilder::finalize() { for (unsigned i = 0, e = SPs.getNumElements(); i != e; ++i) { DISubprogram SP(SPs.getElement(i)); if (MDNode *Temp = SP.getVariablesNodes()) { - SmallVector Variables; - for (Metadata *V : PreservedVariables.lookup(SP)) - Variables.push_back(V); + const auto &PV = PreservedVariables.lookup(SP); + SmallVector Variables(PV.begin(), PV.end()); DIArray AV = getOrCreateArray(Variables); DIType(Temp).replaceAllUsesWith(AV); } @@ -105,9 +104,8 @@ void DIBuilder::finalize() { DIArray GVs = getOrCreateArray(AllGVs); DIType(TempGVs).replaceAllUsesWith(GVs); - SmallVector RetainValuesI; - for (unsigned I = 0, E = AllImportedModules.size(); I < E; I++) - RetainValuesI.push_back(AllImportedModules[I]); + SmallVector RetainValuesI(AllImportedModules.begin(), + AllImportedModules.end()); DIArray IMs = getOrCreateArray(RetainValuesI); DIType(TempImportedModules).replaceAllUsesWith(IMs); @@ -758,8 +756,7 @@ static DIType createTypeWithFlags(LLVMContext &Context, DIType Ty, assert(N && "Unexpected input DIType!"); // Update header field. Elts.push_back(setTypeFlagsInHeader(Ty.getHeader(), FlagsToSet).get(Context)); - for (unsigned I = 1, E = N->getNumOperands(); I != E; ++I) - Elts.push_back(N->getOperand(I)); + Elts.append(N->op_begin() + 1, N->op_end()); return DIType(MDNode::get(Context, Elts)); } diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index deeaae7..76b21d8 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -344,9 +344,7 @@ void DIDescriptor::replaceAllUsesWith(LLVMContext &VMContext, DIDescriptor D) { // itself. const MDNode *DN = D; if (DbgNode == DN) { - SmallVector Ops(DbgNode->getNumOperands()); - for (size_t i = 0; i != Ops.size(); ++i) - Ops[i] = DbgNode->getOperand(i); + SmallVector Ops(DbgNode->op_begin(), DbgNode->op_end()); DN = MDNode::get(VMContext, Ops); } @@ -884,9 +882,8 @@ DIVariable llvm::createInlinedVariable(MDNode *DV, MDNode *InlinedScope, return cleanseInlinedVariable(DV, VMContext); // Insert inlined scope. - SmallVector Elts; - for (unsigned I = 0, E = DIVariableInlinedAtIndex; I != E; ++I) - Elts.push_back(DV->getOperand(I)); + SmallVector Elts(DV->op_begin(), + DV->op_begin() + DIVariableInlinedAtIndex); Elts.push_back(InlinedScope); DIVariable Inlined(MDNode::get(VMContext, Elts)); @@ -900,9 +897,8 @@ DIVariable llvm::cleanseInlinedVariable(MDNode *DV, LLVMContext &VMContext) { return DIVariable(DV); // Remove inlined scope. - SmallVector Elts; - for (unsigned I = 0, E = DIVariableInlinedAtIndex; I != E; ++I) - Elts.push_back(DV->getOperand(I)); + SmallVector Elts(DV->op_begin(), + DV->op_begin() + DIVariableInlinedAtIndex); DIVariable Cleansed(MDNode::get(VMContext, Elts)); assert(Cleansed.Verify() && "Expected to create a DIVariable"); diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 0b9f678..865b187 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -518,8 +518,7 @@ void Verifier::visitGlobalVariable(const GlobalVariable &GV) { continue; if (const User *U = dyn_cast(V)) { - for (unsigned I = 0, N = U->getNumOperands(); I != N; ++I) - WorkStack.push_back(U->getOperand(I)); + WorkStack.append(U->op_begin(), U->op_end()); } if (const ConstantExpr *CE = dyn_cast(V)) { diff --git a/llvm/lib/Linker/LinkModules.cpp b/llvm/lib/Linker/LinkModules.cpp index 9585fba..b55fe48 100644 --- a/llvm/lib/Linker/LinkModules.cpp +++ b/llvm/lib/Linker/LinkModules.cpp @@ -1417,10 +1417,8 @@ bool ModuleLinker::linkModuleFlagsMetadata() { MDNode *SrcValue = cast(SrcOp->getOperand(2)); SmallVector MDs; MDs.reserve(DstValue->getNumOperands() + SrcValue->getNumOperands()); - for (unsigned i = 0, e = DstValue->getNumOperands(); i != e; ++i) - MDs.push_back(DstValue->getOperand(i)); - for (unsigned i = 0, e = SrcValue->getNumOperands(); i != e; ++i) - MDs.push_back(SrcValue->getOperand(i)); + MDs.append(DstValue->op_begin(), DstValue->op_end()); + MDs.append(SrcValue->op_begin(), SrcValue->op_end()); replaceDstValue(MDNode::get(DstM->getContext(), MDs)); break; @@ -1429,10 +1427,8 @@ bool ModuleLinker::linkModuleFlagsMetadata() { SmallSetVector Elts; MDNode *DstValue = cast(DstOp->getOperand(2)); MDNode *SrcValue = cast(SrcOp->getOperand(2)); - for (unsigned i = 0, e = DstValue->getNumOperands(); i != e; ++i) - Elts.insert(DstValue->getOperand(i)); - for (unsigned i = 0, e = SrcValue->getNumOperands(); i != e; ++i) - Elts.insert(SrcValue->getOperand(i)); + Elts.insert(DstValue->op_begin(), DstValue->op_end()); + Elts.insert(SrcValue->op_begin(), SrcValue->op_end()); replaceDstValue(MDNode::get(DstM->getContext(), makeArrayRef(Elts.begin(), Elts.end()))); diff --git a/llvm/lib/Option/Arg.cpp b/llvm/lib/Option/Arg.cpp index 4c8da58..af632d6 100644 --- a/llvm/lib/Option/Arg.cpp +++ b/llvm/lib/Option/Arg.cpp @@ -83,15 +83,13 @@ void Arg::renderAsInput(const ArgList &Args, ArgStringList &Output) const { return; } - for (unsigned i = 0, e = getNumValues(); i != e; ++i) - Output.push_back(getValue(i)); + Output.append(Values.begin(), Values.end()); } void Arg::render(const ArgList &Args, ArgStringList &Output) const { switch (getOption().getRenderStyle()) { case Option::RenderValuesStyle: - for (unsigned i = 0, e = getNumValues(); i != e; ++i) - Output.push_back(getValue(i)); + Output.append(Values.begin(), Values.end()); break; case Option::RenderCommaJoinedStyle: { @@ -109,14 +107,12 @@ void Arg::render(const ArgList &Args, ArgStringList &Output) const { case Option::RenderJoinedStyle: Output.push_back(Args.GetOrMakeJoinedArgString( getIndex(), getSpelling(), getValue(0))); - for (unsigned i = 1, e = getNumValues(); i != e; ++i) - Output.push_back(getValue(i)); + Output.append(Values.begin() + 1, Values.end()); break; case Option::RenderSeparateStyle: Output.push_back(Args.MakeArgString(getSpelling())); - for (unsigned i = 0, e = getNumValues(); i != e; ++i) - Output.push_back(getValue(i)); + Output.append(Values.begin(), Values.end()); break; } } diff --git a/llvm/lib/Option/ArgList.cpp b/llvm/lib/Option/ArgList.cpp index b1a916d..85e956f 100644 --- a/llvm/lib/Option/ArgList.cpp +++ b/llvm/lib/Option/ArgList.cpp @@ -253,8 +253,8 @@ void ArgList::AddAllArgValues(ArgStringList &Output, OptSpecifier Id0, OptSpecifier Id1, OptSpecifier Id2) const { for (auto Arg : filtered(Id0, Id1, Id2)) { Arg->claim(); - for (unsigned i = 0, e = Arg->getNumValues(); i != e; ++i) - Output.push_back(Arg->getValue(i)); + const auto &Values = Arg->getValues(); + Output.append(Values.begin(), Values.end()); } } diff --git a/llvm/lib/ProfileData/CoverageMapping.cpp b/llvm/lib/ProfileData/CoverageMapping.cpp index df6fae7..9ff7f29 100644 --- a/llvm/lib/ProfileData/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/CoverageMapping.cpp @@ -333,8 +333,8 @@ public: std::vector CoverageMapping::getUniqueSourceFiles() const { std::vector Filenames; for (const auto &Function : getCoveredFunctions()) - for (const auto &Filename : Function.Filenames) - Filenames.push_back(Filename); + Filenames.insert(Filenames.end(), Function.Filenames.begin(), + Function.Filenames.end()); std::sort(Filenames.begin(), Filenames.end()); auto Last = std::unique(Filenames.begin(), Filenames.end()); Filenames.erase(Last, Filenames.end()); @@ -425,8 +425,8 @@ CoverageMapping::getInstantiations(StringRef Filename) { for (const auto &InstantiationSet : InstantiationSetCollector) { if (InstantiationSet.second.size() < 2) continue; - for (auto Function : InstantiationSet.second) - Result.push_back(Function); + Result.insert(Result.end(), InstantiationSet.second.begin(), + InstantiationSet.second.end()); } return Result; } diff --git a/llvm/lib/Support/CommandLine.cpp b/llvm/lib/Support/CommandLine.cpp index 0351d28..b49ec36 100644 --- a/llvm/lib/Support/CommandLine.cpp +++ b/llvm/lib/Support/CommandLine.cpp @@ -840,9 +840,7 @@ void CommandLineParser::ParseCommandLineOptions(int argc, assert(hasOptions() && "No options specified!"); // Expand response files. - SmallVector newArgv; - for (int i = 0; i != argc; ++i) - newArgv.push_back(argv[i]); + SmallVector newArgv(argv, argv + argc); StrDupSaver Saver; ExpandResponseFiles(Saver, TokenizeGNUCommandLine, newArgv); argv = &newArgv[0]; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b6275e4..c4b7395 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1337,10 +1337,7 @@ getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) { SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG, RTLIB::Libcall Call) const { - SmallVector Ops; - for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) - Ops.push_back(Op.getOperand(i)); - + SmallVector Ops(Op->op_begin(), Op->op_end()); return makeLibCall(DAG, Call, MVT::f128, &Ops[0], Ops.size(), false, SDLoc(Op)).first; } @@ -1568,10 +1565,7 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op, else LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(), Op.getValueType()); - SmallVector Ops; - for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) - Ops.push_back(Op.getOperand(i)); - + SmallVector Ops(Op->op_begin(), Op->op_end()); return makeLibCall(DAG, LC, Op.getValueType(), &Ops[0], Ops.size(), false, SDLoc(Op)).first; } diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index d1c1e2f..5b5bbe2 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -1053,9 +1053,7 @@ public: assert (Regs.size() > 0 && "Empty list not allowed"); auto Op = make_unique(k_RegList, Parser); - Op->RegList.List = new SmallVector(); - for (auto Reg : Regs) - Op->RegList.List->push_back(Reg); + Op->RegList.List = new SmallVector(Regs.begin(), Regs.end()); Op->StartLoc = StartLoc; Op->EndLoc = EndLoc; return Op; diff --git a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index e180cb0..8415f28 100644 --- a/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -1836,11 +1836,9 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_fill_h: case Intrinsic::mips_fill_w: case Intrinsic::mips_fill_d: { - SmallVector Ops; EVT ResTy = Op->getValueType(0); - - for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) - Ops.push_back(Op->getOperand(1)); + SmallVector Ops(ResTy.getVectorNumElements(), + Op->getOperand(1)); // If ResTy is v2i64 then the type legalizer will break this node down into // an equivalent v4i32. diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index 38e17f1..e84aabc 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -2183,9 +2183,7 @@ SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, unsigned Opcode = Node->getMachineOpcode(); SDValue FakeOp; - std::vector Ops; - for (const SDUse &I : Node->ops()) - Ops.push_back(I); + std::vector Ops(Node->op_begin(), Node->op_end()); if (Opcode == AMDGPU::DOT_4) { int OperandIdx[] = { @@ -2247,10 +2245,7 @@ SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, AMDGPU::OpName::clamp); if (ClampIdx < 0) return Node; - std::vector Ops; - unsigned NumOp = Src.getNumOperands(); - for(unsigned i = 0; i < NumOp; ++i) - Ops.push_back(Src.getOperand(i)); + std::vector Ops(Src->op_begin(), Src->op_end()); Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32); return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node), Node->getVTList(), Ops); diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 4fee32d..2821a0c 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -577,8 +577,7 @@ SDValue SITargetLowering::LowerFormalArguments( // Fill up the missing vector elements NumElements = Arg.VT.getVectorNumElements() - NumElements; - for (unsigned j = 0; j != NumElements; ++j) - Regs.push_back(DAG.getUNDEF(VT)); + Regs.append(NumElements, DAG.getUNDEF(VT)); InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); continue; @@ -778,15 +777,12 @@ SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN); // Build the result and - SmallVector Res; - for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i) - Res.push_back(Intr->getValueType(i)); + ArrayRef Res(Intr->value_begin() + 1, Intr->value_end()); // operands of the new intrinsic call SmallVector Ops; Ops.push_back(BRCOND.getOperand(0)); - for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i) - Ops.push_back(Intr->getOperand(i)); + Ops.append(Intr->op_begin() + 1, Intr->op_end()); Ops.push_back(Target); // build the new intrinsic call @@ -1758,9 +1754,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N, if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) { SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI); if (NewPtr) { - SmallVector NewOps; - for (unsigned I = 0, E = MemNode->getNumOperands(); I != E; ++I) - NewOps.push_back(MemNode->getOperand(I)); + SmallVector NewOps(MemNode->op_begin(), MemNode->op_end()); NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr; return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0); @@ -1938,8 +1932,7 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node, // Adjust the writemask in the node std::vector Ops; Ops.push_back(DAG.getTargetConstant(NewDmask, MVT::i32)); - for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) - Ops.push_back(Node->getOperand(i)); + Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end()); Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops); // If we only got one lane, replace it with a copy @@ -2196,8 +2189,7 @@ MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N, // Copy remaining operands so we keep any chain and glue nodes that follow // the normal operands. - for (unsigned I = 2, E = N->getNumOperands(); I != E; ++I) - Ops.push_back(N->getOperand(I)); + Ops.append(N->op_begin() + 2, N->op_end()); return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops); } diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index 34f4441..ade6c77 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -393,17 +393,14 @@ static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load, Ops.clear(); Ops.push_back(NewChain); } - for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i) - Ops.push_back(OrigChain.getOperand(i)); + Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end()); CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops); CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0), Load.getOperand(1), Load.getOperand(2)); - unsigned NumOps = Call.getNode()->getNumOperands(); Ops.clear(); Ops.push_back(SDValue(Load.getNode(), 1)); - for (unsigned i = 1, e = NumOps; i != e; ++i) - Ops.push_back(Call.getOperand(i)); + Ops.append(Call->op_begin() + 1, Call->op_end()); CurDAG->UpdateNodeOperands(Call.getNode(), Ops); } diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a08ac33..ae0aae4 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6011,9 +6011,7 @@ LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) { LD->getPointerInfo().getWithOffset(StartOffset), false, false, false, 0); - SmallVector Mask; - for (unsigned i = 0; i != NumElems; ++i) - Mask.push_back(EltNo); + SmallVector Mask(NumElems, EltNo); return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]); } @@ -7083,9 +7081,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { // elements, otherwise build the individual 128-bit pieces and use // shuffles to put them in place. if (VT.is256BitVector() || VT.is512BitVector()) { - SmallVector V; - for (unsigned i = 0; i != NumElems; ++i) - V.push_back(Op.getOperand(i)); + SmallVector V(Op->op_begin(), Op->op_begin() + NumElems); // Check for a build vector of consecutive loads. if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false)) @@ -15572,9 +15568,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl, DAG.getConstant(0, Op.getValueType())); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); - SmallVector Ops; - for (unsigned i = 0; i != NumOperands; ++i) - Ops.push_back(Op.getOperand(i)); + SmallVector Ops(Op->op_begin(), Op->op_begin() + NumOperands); SDValue New = DAG.getNode(Opcode, dl, VTs, Ops); DAG.ReplaceAllUsesWith(Op, New); @@ -19812,9 +19806,7 @@ static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget, DAG.getIntPtrConstant(i))); // Explicitly mark the extra elements as Undef. - SDValue Undef = DAG.getUNDEF(SVT); - for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i) - Elts.push_back(Undef); + Elts.append(NumElts, DAG.getUNDEF(SVT)); EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2); SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts); diff --git a/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp index ae1c228..6adf0d2 100644 --- a/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/DataFlowSanitizer.cpp @@ -371,10 +371,8 @@ DataFlowSanitizer::DataFlowSanitizer( } FunctionType *DataFlowSanitizer::getArgsFunctionType(FunctionType *T) { - llvm::SmallVector ArgTypes; - std::copy(T->param_begin(), T->param_end(), std::back_inserter(ArgTypes)); - for (unsigned i = 0, e = T->getNumParams(); i != e; ++i) - ArgTypes.push_back(ShadowTy); + llvm::SmallVector ArgTypes(T->param_begin(), T->param_end()); + ArgTypes.append(T->getNumParams(), ShadowTy); if (T->isVarArg()) ArgTypes.push_back(ShadowPtrTy); Type *RetType = T->getReturnType(); @@ -387,9 +385,8 @@ FunctionType *DataFlowSanitizer::getTrampolineFunctionType(FunctionType *T) { assert(!T->isVarArg()); llvm::SmallVector ArgTypes; ArgTypes.push_back(T->getPointerTo()); - std::copy(T->param_begin(), T->param_end(), std::back_inserter(ArgTypes)); - for (unsigned i = 0, e = T->getNumParams(); i != e; ++i) - ArgTypes.push_back(ShadowTy); + ArgTypes.append(T->param_begin(), T->param_end()); + ArgTypes.append(T->getNumParams(), ShadowTy); Type *RetType = T->getReturnType(); if (!RetType->isVoidTy()) ArgTypes.push_back(ShadowPtrTy); diff --git a/llvm/lib/Transforms/Utils/LoopSimplify.cpp b/llvm/lib/Transforms/Utils/LoopSimplify.cpp index e0cf8f8..a0f8268 100644 --- a/llvm/lib/Transforms/Utils/LoopSimplify.cpp +++ b/llvm/lib/Transforms/Utils/LoopSimplify.cpp @@ -726,8 +726,7 @@ bool llvm::simplifyLoop(Loop *L, DominatorTree *DT, LoopInfo *LI, Pass *PP, // order. We can use this simple process because loops form a tree. for (unsigned Idx = 0; Idx != Worklist.size(); ++Idx) { Loop *L2 = Worklist[Idx]; - for (Loop::iterator I = L2->begin(), E = L2->end(); I != E; ++I) - Worklist.push_back(*I); + Worklist.append(L2->begin(), L2->end()); } while (!Worklist.empty()) -- 2.7.4