From 6cb42cd6669785f3b611106e1b6b38bbe65733a9 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 2 Mar 2022 10:55:18 -0800 Subject: [PATCH] [RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmConstraint. Until Zfinx is supported in CodeGen we need to convert all Zfinx register classes to GPR. Remove the zfinx-types.ll test which didn't test anything meaningful since -mattr=zfinx isn't implemented completely in llc. Follow up to D93298. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 25 ++++-------- .../CodeGen/RISCV/inline-asm-d-constraint-f.ll | 34 +++++++++++++++++ .../CodeGen/RISCV/inline-asm-f-constraint-f.ll | 20 ++++++++++ .../CodeGen/RISCV/inline-asm-zfh-constraint-f.ll | 44 ++++++++++++++++++++++ llvm/test/CodeGen/RISCV/zfinx-types.ll | 19 ---------- 5 files changed, 105 insertions(+), 37 deletions(-) delete mode 100644 llvm/test/CodeGen/RISCV/zfinx-types.ll diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index d553279..0d086e1 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -11027,24 +11027,13 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, std::pair Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); - if (Res.second == &RISCV::GPRF32RegClass) { - if (!Subtarget.is64Bit() || VT == MVT::Other) - return std::make_pair(Res.first, &RISCV::GPRRegClass); - return std::make_pair(0, nullptr); - } - - if (Res.second == &RISCV::GPRF64RegClass || - Res.second == &RISCV::GPRPF64RegClass) { - if (Subtarget.is64Bit() || VT == MVT::Other) - return std::make_pair(Res.first, &RISCV::GPRRegClass); - return std::make_pair(0, nullptr); - } - - if (Res.second == &RISCV::GPRF16RegClass) { - if (VT == MVT::Other) - return std::make_pair(Res.first, &RISCV::GPRRegClass); - return std::make_pair(0, nullptr); - } + // If we picked one of the Zfinx register classes, remap it to the GPR class. + // FIXME: When Zfinx is supported in CodeGen this will need to take the + // Subtarget into account. + if (Res.second == &RISCV::GPRF16RegClass || + Res.second == &RISCV::GPRF32RegClass || + Res.second == &RISCV::GPRF64RegClass) + return std::make_pair(Res.first, &RISCV::GPRRegClass); return Res; } diff --git a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll index 5549fd0..6aa9fb3 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll @@ -71,3 +71,37 @@ define double @constraint_f_double_abi_name(double %a) nounwind { %2 = tail call double asm "fadd.d $0, $1, $2", "={ft0},{fa1},{fs0}"(double %a, double %1) ret double %2 } + +define double @constraint_gpr(double %x) { +; RV32F-LABEL: constraint_gpr: +; RV32F: # %bb.0: +; RV32F-NEXT: addi sp, sp, -32 +; RV32F-NEXT: .cfi_def_cfa_offset 32 +; RV32F-NEXT: sw a0, 8(sp) +; RV32F-NEXT: sw a1, 12(sp) +; RV32F-NEXT: fld ft0, 8(sp) +; RV32F-NEXT: fsd ft0, 24(sp) +; RV32F-NEXT: lw a0, 24(sp) +; RV32F-NEXT: lw a1, 28(sp) +; RV32F-NEXT: #APP +; RV32F-NEXT: mv a0, a0 +; RV32F-NEXT: #NO_APP +; RV32F-NEXT: sw a1, 20(sp) +; RV32F-NEXT: sw a0, 16(sp) +; RV32F-NEXT: fld ft0, 16(sp) +; RV32F-NEXT: fsd ft0, 8(sp) +; RV32F-NEXT: lw a0, 8(sp) +; RV32F-NEXT: lw a1, 12(sp) +; RV32F-NEXT: addi sp, sp, 32 +; RV32F-NEXT: ret +; +; RV64F-LABEL: constraint_gpr: +; RV64F: # %bb.0: +; RV64F-NEXT: .cfi_def_cfa_offset 0 +; RV64F-NEXT: #APP +; RV64F-NEXT: mv a0, a0 +; RV64F-NEXT: #NO_APP +; RV64F-NEXT: ret + %1 = tail call double asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(double %x) + ret double %1 +} diff --git a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll index 698b49b..de2669f 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll @@ -64,3 +64,23 @@ define float @constraint_f_float_abi_name(float %a) nounwind { %2 = tail call float asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(float %a, float %1) ret float %2 } + +define float @constraint_gpr(float %x) { +; RV32F-LABEL: constraint_gpr: +; RV32F: # %bb.0: +; RV32F-NEXT: .cfi_def_cfa_offset 0 +; RV32F-NEXT: #APP +; RV32F-NEXT: mv a0, a0 +; RV32F-NEXT: #NO_APP +; RV32F-NEXT: ret +; +; RV64F-LABEL: constraint_gpr: +; RV64F: # %bb.0: +; RV64F-NEXT: .cfi_def_cfa_offset 0 +; RV64F-NEXT: #APP +; RV64F-NEXT: mv a0, a0 +; RV64F-NEXT: #NO_APP +; RV64F-NEXT: ret + %1 = tail call float asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(float %x) + ret float %1 +} diff --git a/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll b/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll index dae55de..91e7011 100644 --- a/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll +++ b/llvm/test/CodeGen/RISCV/inline-asm-zfh-constraint-f.ll @@ -111,3 +111,47 @@ define half @constraint_f_half_abi_name(half %a) nounwind { %2 = tail call half asm "fadd.s $0, $1, $2", "={ft0},{fa0},{fs0}"(half %a, half %1) ret half %2 } + +define half @constraint_gpr(half %x) { +; RV32ZFH-LABEL: constraint_gpr: +; RV32ZFH: # %bb.0: +; RV32ZFH-NEXT: .cfi_def_cfa_offset 0 +; RV32ZFH-NEXT: fmv.x.h a0, fa0 +; RV32ZFH-NEXT: #APP +; RV32ZFH-NEXT: mv a0, a0 +; RV32ZFH-NEXT: #NO_APP +; RV32ZFH-NEXT: fmv.h.x fa0, a0 +; RV32ZFH-NEXT: ret +; +; RV64ZFH-LABEL: constraint_gpr: +; RV64ZFH: # %bb.0: +; RV64ZFH-NEXT: .cfi_def_cfa_offset 0 +; RV64ZFH-NEXT: fmv.x.h a0, fa0 +; RV64ZFH-NEXT: #APP +; RV64ZFH-NEXT: mv a0, a0 +; RV64ZFH-NEXT: #NO_APP +; RV64ZFH-NEXT: fmv.h.x fa0, a0 +; RV64ZFH-NEXT: ret +; +; RV32DZFH-LABEL: constraint_gpr: +; RV32DZFH: # %bb.0: +; RV32DZFH-NEXT: .cfi_def_cfa_offset 0 +; RV32DZFH-NEXT: fmv.x.h a0, fa0 +; RV32DZFH-NEXT: #APP +; RV32DZFH-NEXT: mv a0, a0 +; RV32DZFH-NEXT: #NO_APP +; RV32DZFH-NEXT: fmv.h.x fa0, a0 +; RV32DZFH-NEXT: ret +; +; RV64DZFH-LABEL: constraint_gpr: +; RV64DZFH: # %bb.0: +; RV64DZFH-NEXT: .cfi_def_cfa_offset 0 +; RV64DZFH-NEXT: fmv.x.h a0, fa0 +; RV64DZFH-NEXT: #APP +; RV64DZFH-NEXT: mv a0, a0 +; RV64DZFH-NEXT: #NO_APP +; RV64DZFH-NEXT: fmv.h.x fa0, a0 +; RV64DZFH-NEXT: ret + %1 = tail call half asm sideeffect alignstack "mv $0, $1", "={x10},{x10}"(half %x) + ret half %1 +} diff --git a/llvm/test/CodeGen/RISCV/zfinx-types.ll b/llvm/test/CodeGen/RISCV/zfinx-types.ll deleted file mode 100644 index 9cbc7d9..0000000 --- a/llvm/test/CodeGen/RISCV/zfinx-types.ll +++ /dev/null @@ -1,19 +0,0 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+zfinx -verify-machineinstrs < %s \ -; RUN: -target-abi=ilp32f | FileCheck -check-prefix=RVZFINX %s -; RUN: llc -mtriple=riscv64 -mattr=+zfinx -verify-machineinstrs < %s \ -; RUN: -target-abi=lp64f | FileCheck -check-prefix=RVZFINX %s - -define float @test_float(float %x) { -; RVZFINX-LABEL: test_float: -; RVZFINX: # %bb.0: -; RVZFINX-NEXT: .cfi_def_cfa_offset 0 -; RVZFINX-NEXT: li a0, 0 -; RVZFINX-NEXT: #APP -; RVZFINX-NEXT: mv a0, a0 -; RVZFINX-NEXT: #NO_APP -; RVZFINX-NEXT: li a0, 0 -; RVZFINX-NEXT: ret - %1 = tail call float asm sideeffect alignstack "mv a0, a0", "={x10},{x10}"(float 0.000000e+00) - ret float 0.000000e+00 -} -- 2.7.4