From 6c1d32581a4a07a05a916edf136b50f991818f19 Mon Sep 17 00:00:00 2001 From: Faith Ekstrand Date: Mon, 14 Aug 2023 11:43:35 -0500 Subject: [PATCH] nir: Drop nir_alu_dest Instead, we replace it directly with nir_def. We could replace it with nir_dest but the next commit gets rid of that so this avoids unnecessary churn. Most of this commit was generated by sed: sed -i -e 's/dest.dest.ssa/def/g' src/**/*.h src/**/*.c src/**/*.cpp There were a few manual fixups required in the nir_legacy.c and nir_from_ssa.c as nir_legacy_reg and nir_parallel_copy_entry both have a similar pattern. Acked-by: Alyssa Rosenzweig Part-of: --- docs/nir/alu.rst | 3 - src/amd/common/ac_nir_lower_ngg.c | 4 +- src/amd/common/ac_nir_lower_tex.c | 6 +- src/amd/compiler/aco_instruction_selection.cpp | 102 +++++++------- .../compiler/aco_instruction_selection_setup.cpp | 13 +- src/amd/llvm/ac_nir_to_llvm.c | 28 ++-- src/amd/vulkan/radv_pipeline.c | 14 +- src/amd/vulkan/radv_shader.c | 2 +- src/asahi/compiler/agx_compile.c | 8 +- src/broadcom/compiler/nir_to_vir.c | 4 +- src/compiler/glsl/glsl_to_nir.cpp | 2 +- src/compiler/glsl/tests/test_gl_lower_mediump.cpp | 2 +- src/compiler/nir/nir.c | 6 +- src/compiler/nir/nir.h | 7 +- src/compiler/nir/nir_builder.c | 8 +- src/compiler/nir/nir_builder.h | 4 +- src/compiler/nir/nir_clone.c | 2 +- src/compiler/nir/nir_divergence_analysis.c | 4 +- src/compiler/nir/nir_gather_info.c | 4 +- src/compiler/nir/nir_gather_types.c | 8 +- src/compiler/nir/nir_inline_helpers.h | 2 +- src/compiler/nir/nir_instr_set.c | 10 +- src/compiler/nir/nir_legacy.c | 16 +-- src/compiler/nir/nir_loop_analyze.c | 26 ++-- src/compiler/nir/nir_lower_alu.c | 2 +- src/compiler/nir/nir_lower_alu_width.c | 26 ++-- src/compiler/nir/nir_lower_amul.c | 2 +- src/compiler/nir/nir_lower_bit_size.c | 6 +- src/compiler/nir/nir_lower_bool_to_bitsize.c | 14 +- src/compiler/nir/nir_lower_bool_to_float.c | 10 +- src/compiler/nir/nir_lower_bool_to_int32.c | 8 +- src/compiler/nir/nir_lower_convert_alu_types.c | 2 +- src/compiler/nir/nir_lower_double_ops.c | 6 +- src/compiler/nir/nir_lower_flrp.c | 22 ++-- src/compiler/nir/nir_lower_fp16_conv.c | 2 +- src/compiler/nir/nir_lower_frexp.c | 2 +- src/compiler/nir/nir_lower_idiv.c | 2 +- src/compiler/nir/nir_lower_int64.c | 8 +- src/compiler/nir/nir_lower_int_to_float.c | 6 +- src/compiler/nir/nir_lower_packing.c | 2 +- src/compiler/nir/nir_lower_phis_to_scalar.c | 8 +- src/compiler/nir/nir_lower_shader_calls.c | 2 +- src/compiler/nir/nir_lower_vars_to_ssa.c | 4 +- src/compiler/nir/nir_lower_vec_to_regs.c | 24 ++-- src/compiler/nir/nir_mod_analysis.c | 2 +- src/compiler/nir/nir_move_vec_src_uses_to_dest.c | 4 +- src/compiler/nir/nir_opt_comparison_pre.c | 26 ++-- src/compiler/nir/nir_opt_constant_folding.c | 10 +- src/compiler/nir/nir_opt_copy_propagate.c | 10 +- src/compiler/nir/nir_opt_dce.c | 2 +- src/compiler/nir/nir_opt_idiv_const.c | 8 +- src/compiler/nir/nir_opt_if.c | 24 ++-- src/compiler/nir/nir_opt_intrinsics.c | 10 +- src/compiler/nir/nir_opt_peephole_select.c | 6 +- src/compiler/nir/nir_opt_phi_precision.c | 4 +- src/compiler/nir/nir_opt_reassociate_bfi.c | 10 +- src/compiler/nir/nir_opt_rematerialize_compares.c | 12 +- src/compiler/nir/nir_opt_shrink_vectors.c | 6 +- src/compiler/nir/nir_opt_undef.c | 10 +- src/compiler/nir/nir_opt_vectorize.c | 40 +++--- src/compiler/nir/nir_print.c | 2 +- src/compiler/nir/nir_propagate_invariant.c | 2 +- src/compiler/nir/nir_range_analysis.c | 2 +- src/compiler/nir/nir_scale_fdiv.c | 2 +- src/compiler/nir/nir_search.c | 28 ++-- src/compiler/nir/nir_search_helpers.h | 14 +- src/compiler/nir/nir_serialize.c | 4 +- src/compiler/nir/nir_split_64bit_vec3_and_vec4.c | 2 +- src/compiler/nir/nir_validate.c | 4 +- src/compiler/nir/tests/comparison_pre_tests.cpp | 12 +- src/compiler/nir/tests/mod_analysis_tests.cpp | 4 +- src/compiler/nir/tests/range_analysis_tests.cpp | 2 +- src/compiler/spirv/spirv_to_nir.c | 6 +- src/freedreno/ir3/ir3_compiler_nir.c | 20 +-- src/freedreno/ir3/ir3_nir_opt_preamble.c | 8 +- src/gallium/auxiliary/gallivm/lp_bld_nir.c | 6 +- src/gallium/auxiliary/nir/nir_to_tgsi.c | 12 +- src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c | 18 +-- src/gallium/drivers/etnaviv/etnaviv_compiler_nir.h | 4 +- src/gallium/drivers/etnaviv/etnaviv_nir.c | 10 +- .../etnaviv/etnaviv_nir_lower_source_mods.c | 2 +- src/gallium/drivers/freedreno/a2xx/ir2_nir.c | 4 +- src/gallium/drivers/lima/ir/gp/nir.c | 4 +- .../drivers/lima/ir/lima_nir_split_load_input.c | 14 +- src/gallium/drivers/lima/ir/pp/nir.c | 2 +- src/gallium/drivers/lima/lima_program.c | 2 +- src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp | 146 ++++++++++----------- .../drivers/r600/sfn/sfn_nir_lower_64bit.cpp | 16 +-- .../r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp | 4 +- .../r600/sfn/tests/sfn_valuefactory_test.cpp | 8 +- src/gallium/drivers/radeonsi/si_shader_nir.c | 8 +- src/gallium/drivers/vc4/vc4_program.c | 12 +- .../drivers/zink/nir_to_spirv/nir_to_spirv.c | 18 +-- src/gallium/drivers/zink/zink_compiler.c | 6 +- src/imagination/rogue/rogue_compile.c | 10 +- src/intel/compiler/brw_fs_nir.cpp | 50 +++---- src/intel/compiler/brw_nir.c | 4 +- src/intel/compiler/brw_nir_lower_conversions.c | 4 +- src/intel/compiler/brw_nir_opt_peephole_ffma.c | 24 ++-- .../compiler/brw_nir_opt_peephole_imul32x16.c | 16 +-- src/intel/compiler/brw_vec4_nir.cpp | 72 +++++----- src/mesa/program/prog_to_nir.c | 4 +- src/microsoft/clc/clc_compiler.c | 2 +- src/microsoft/compiler/dxil_nir.c | 12 +- src/microsoft/compiler/nir_to_dxil.c | 38 +++--- src/nouveau/codegen/nv50_ir_from_nir.cpp | 68 +++++----- src/panfrost/compiler/bifrost_compile.c | 8 +- src/panfrost/midgard/midgard_compile.c | 10 +- src/panfrost/midgard/midgard_derivatives.c | 2 +- src/panfrost/midgard/midgard_nir_type_csel.c | 2 +- 110 files changed, 676 insertions(+), 685 deletions(-) diff --git a/docs/nir/alu.rst b/docs/nir/alu.rst index b7af909..4b1eb3c 100644 --- a/docs/nir/alu.rst +++ b/docs/nir/alu.rst @@ -65,9 +65,6 @@ use in other instruction types like intrinsics or texture ops. .. doxygenstruct:: nir_alu_src :members: -.. doxygenstruct:: nir_alu_dest - :members: - NIR ALU Opcode Reference: ------------------------- diff --git a/src/amd/common/ac_nir_lower_ngg.c b/src/amd/common/ac_nir_lower_ngg.c index c9cb7c5..4d31e86 100644 --- a/src/amd/common/ac_nir_lower_ngg.c +++ b/src/amd/common/ac_nir_lower_ngg.c @@ -1153,12 +1153,12 @@ find_reusable_ssa_def(nir_instr *instr) switch (instr->type) { case nir_instr_type_alu: { nir_alu_instr *alu = nir_instr_as_alu(instr); - if (alu->dest.dest.ssa.divergent) + if (alu->def.divergent) return NULL; /* Ignore uniform floats because they regress VGPR usage too much */ if (nir_op_infos[alu->op].output_type & nir_type_float) return NULL; - return &alu->dest.dest.ssa; + return &alu->def; } case nir_instr_type_intrinsic: { nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr); diff --git a/src/amd/common/ac_nir_lower_tex.c b/src/amd/common/ac_nir_lower_tex.c index 940e76e..f741339 100644 --- a/src/amd/common/ac_nir_lower_tex.c +++ b/src/amd/common/ac_nir_lower_tex.c @@ -420,12 +420,12 @@ move_fddxy(struct move_tex_coords_state *state, nir_function_impl *impl, nir_alu return false; } - unsigned num_components = instr->dest.dest.ssa.num_components; + unsigned num_components = instr->def.num_components; nir_scalar components[NIR_MAX_VEC_COMPONENTS]; coord_info infos[NIR_MAX_VEC_COMPONENTS]; bool can_move_all = true; for (unsigned i = 0; i < num_components; i++) { - components[i] = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&instr->dest.dest.ssa, i), 0); + components[i] = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&instr->def, i), 0); components[i] = nir_scalar_chase_movs(components[i]); can_move_all &= can_move_coord(components[i], &infos[i]); } @@ -439,7 +439,7 @@ move_fddxy(struct move_tex_coords_state *state, nir_function_impl *impl, nir_alu nir_def *def = nir_vec_scalars(&state->toplevel_b, components, num_components); def = nir_build_alu1(&state->toplevel_b, instr->op, def); - nir_def_rewrite_uses(&instr->dest.dest.ssa, def); + nir_def_rewrite_uses(&instr->def, def); state->num_wqm_vgprs += num_components; diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index bd71cc1..284c9b0 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -961,7 +961,7 @@ emit_vop3p_instruction(isel_context* ctx, nir_alu_instr* instr, aco_opcode op, T Temp src1 = get_alu_src_vop3p(ctx, instr->src[!swap_srcs]); if (src0.type() == RegType::sgpr && src1.type() == RegType::sgpr) src1 = as_vgpr(ctx, src1); - assert(instr->dest.dest.ssa.num_components == 2); + assert(instr->def.num_components == 2); /* swizzle to opsel: all swizzles are either 0 (x) or 1 (y) */ unsigned opsel_lo = @@ -1081,7 +1081,7 @@ emit_comparison(isel_context* ctx, nir_alu_instr* instr, Temp dst, aco_opcode v1 aco_opcode v_op = instr->src[0].src.ssa->bit_size == 64 ? v64_op : instr->src[0].src.ssa->bit_size == 32 ? v32_op : v16_op; - bool use_valu = s_op == aco_opcode::num_opcodes || instr->dest.dest.ssa.divergent || + bool use_valu = s_op == aco_opcode::num_opcodes || instr->def.divergent || get_ssa_temp(ctx, instr->src[0].src.ssa).type() == RegType::vgpr || get_ssa_temp(ctx, instr->src[1].src.ssa).type() == RegType::vgpr; aco_opcode op = use_valu ? v_op : s_op; @@ -1142,7 +1142,7 @@ emit_bcsel(isel_context* ctx, nir_alu_instr* instr, Temp dst) return; } - if (instr->dest.dest.ssa.bit_size == 1) { + if (instr->def.bit_size == 1) { assert(dst.regClass() == bld.lm); assert(then.regClass() == bld.lm); assert(els.regClass() == bld.lm); @@ -1165,7 +1165,7 @@ emit_bcsel(isel_context* ctx, nir_alu_instr* instr, Temp dst) /* divergent boolean bcsel * this implements bcsel on bools: dst = s0 ? s1 : s2 * are going to be: dst = (s0 & s1) | (~s0 & s2) */ - assert(instr->dest.dest.ssa.bit_size == 1); + assert(instr->def.bit_size == 1); if (cond.id() != then.id()) then = bld.sop2(Builder::s_and, bld.def(bld.lm), bld.def(s1, scc), cond, then); @@ -1368,7 +1368,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) { Builder bld(ctx->program, ctx->block); bld.is_precise = instr->exact; - Temp dst = get_ssa_temp(ctx, &instr->dest.dest.ssa); + Temp dst = get_ssa_temp(ctx, &instr->def); switch (instr->op) { case nir_op_vec2: case nir_op_vec3: @@ -1377,14 +1377,14 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_vec8: case nir_op_vec16: { std::array elems; - unsigned num = instr->dest.dest.ssa.num_components; + unsigned num = instr->def.num_components; for (unsigned i = 0; i < num; ++i) elems[i] = get_alu_src(ctx, instr->src[i]); - if (instr->dest.dest.ssa.bit_size >= 32 || dst.type() == RegType::vgpr) { + if (instr->def.bit_size >= 32 || dst.type() == RegType::vgpr) { aco_ptr vec{create_instruction( - aco_opcode::p_create_vector, Format::PSEUDO, instr->dest.dest.ssa.num_components, 1)}; - RegClass elem_rc = RegClass::get(RegType::vgpr, instr->dest.dest.ssa.bit_size / 8u); + aco_opcode::p_create_vector, Format::PSEUDO, instr->def.num_components, 1)}; + RegClass elem_rc = RegClass::get(RegType::vgpr, instr->def.bit_size / 8u); for (unsigned i = 0; i < num; ++i) { if (elems[i].type() == RegType::sgpr && elem_rc.is_subdword()) elems[i] = emit_extract_vector(ctx, elems[i], 0, elem_rc); @@ -1395,14 +1395,14 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) ctx->allocated_vec.emplace(dst.id(), elems); } else { bool use_s_pack = ctx->program->gfx_level >= GFX9; - Temp mask = bld.copy(bld.def(s1), Operand::c32((1u << instr->dest.dest.ssa.bit_size) - 1)); + Temp mask = bld.copy(bld.def(s1), Operand::c32((1u << instr->def.bit_size) - 1)); std::array packed; uint32_t const_vals[NIR_MAX_VEC_COMPONENTS] = {}; for (unsigned i = 0; i < num; i++) { unsigned packed_size = use_s_pack ? 16 : 32; - unsigned idx = i * instr->dest.dest.ssa.bit_size / packed_size; - unsigned offset = i * instr->dest.dest.ssa.bit_size % packed_size; + unsigned idx = i * instr->def.bit_size / packed_size; + unsigned offset = i * instr->def.bit_size % packed_size; if (nir_src_is_const(instr->src[i].src)) { const_vals[idx] |= nir_src_as_uint(instr->src[i].src) << offset; continue; @@ -1410,7 +1410,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) if (nir_src_is_undef(instr->src[i].src)) continue; - if (offset != packed_size - instr->dest.dest.ssa.bit_size) + if (offset != packed_size - instr->def.bit_size) elems[i] = bld.sop2(aco_opcode::s_and_b32, bld.def(s1), bld.def(s1, scc), elems[i], mask); @@ -1500,7 +1500,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_iabs: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Temp src = get_alu_src_vop3p(ctx, instr->src[0]); unsigned opsel_lo = (instr->src[0].swizzle[0] & 1) << 1; @@ -1574,7 +1574,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_max_i16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_max_i16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_i32, dst, true); @@ -1590,7 +1590,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_max_u16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_max_u16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_u32, dst, true); @@ -1606,7 +1606,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_min_i16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_min_i16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_i32, dst, true); @@ -1622,7 +1622,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_min_u16_e64, dst); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_min_u16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_u32, dst, true); @@ -1634,7 +1634,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_ior: { - if (instr->dest.dest.ssa.bit_size == 1) { + if (instr->def.bit_size == 1) { emit_boolean_logic(ctx, instr, Builder::s_or, dst); } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_or_b32, dst, true); @@ -1650,7 +1650,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_iand: { - if (instr->dest.dest.ssa.bit_size == 1) { + if (instr->def.bit_size == 1) { emit_boolean_logic(ctx, instr, Builder::s_and, dst); } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_and_b32, dst, true); @@ -1666,7 +1666,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_ixor: { - if (instr->dest.dest.ssa.bit_size == 1) { + if (instr->def.bit_size == 1) { emit_boolean_logic(ctx, instr, Builder::s_xor, dst); } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_xor_b32, dst, true); @@ -1686,7 +1686,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_lshrrev_b16_e64, dst, false, 2, true); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b16, dst, false, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_lshrrev_b16, dst, true); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshrrev_b32, dst, false, true); @@ -1709,7 +1709,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_lshlrev_b16_e64, dst, false, 2, true); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b16, dst, false, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_lshlrev_b16, dst, true); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_lshlrev_b32, dst, false, true, false, @@ -1733,7 +1733,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_ashrrev_i16_e64, dst, false, 2, true); } else if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i16, dst, false, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_ashrrev_i16, dst, true); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_ashrrev_i32, dst, false, true); @@ -1850,7 +1850,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) { emit_vop2_instruction(ctx, instr, aco_opcode::v_add_u16, dst, true); break; - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_u16, dst); break; } @@ -1891,7 +1891,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_uadd_sat: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Instruction* add_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_u16, dst); add_instr->valu().clamp = 1; break; @@ -1973,7 +1973,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_iadd_sat: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Instruction* add_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_i16, dst); add_instr->valu().clamp = 1; break; @@ -2049,7 +2049,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) if (dst.regClass() == s1) { emit_sop2_instruction(ctx, instr, aco_opcode::s_sub_i32, dst, true); break; - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_u16, dst); break; } @@ -2133,7 +2133,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_usub_sat: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_u16, dst); sub_instr->valu().clamp = 1; break; @@ -2215,7 +2215,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_isub_sat: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Instruction* sub_instr = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_sub_i16, dst); sub_instr->valu().clamp = 1; break; @@ -2253,7 +2253,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) emit_vop3a_instruction(ctx, instr, aco_opcode::v_mul_lo_u16_e64, dst); } else if (dst.bytes() <= 2 && ctx->program->gfx_level >= GFX8) { emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_lo_u16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_mul_lo_u16, dst); } else if (dst.type() == RegType::vgpr) { uint32_t src0_ub = get_alu_src_ub(ctx, instr, 0); @@ -2317,7 +2317,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_fmul: { if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_mul_f16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_f32, dst, true); @@ -2339,7 +2339,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_fadd: { if (dst.regClass() == v2b) { emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_f16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_add_f32, dst, true); @@ -2351,7 +2351,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_fsub: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Instruction* add = emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_add_f16, dst); VALU_instruction& sub = add->valu(); sub.neg_lo[1] = true; @@ -2383,8 +2383,8 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_ffma: { if (dst.regClass() == v2b) { emit_vop3a_instruction(ctx, instr, aco_opcode::v_fma_f16, dst, false, 3); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { - assert(instr->dest.dest.ssa.num_components == 2); + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { + assert(instr->def.num_components == 2); Temp src0 = as_vgpr(ctx, get_alu_src_vop3p(ctx, instr->src[0])); Temp src1 = as_vgpr(ctx, get_alu_src_vop3p(ctx, instr->src[1])); @@ -2421,7 +2421,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) if (dst.regClass() == v2b) { // TODO: check fp_mode.must_flush_denorms16_64 emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_max_f16, dst); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_max_f32, dst, true, false, @@ -2438,7 +2438,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) if (dst.regClass() == v2b) { // TODO: check fp_mode.must_flush_denorms16_64 emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f16, dst, true); - } else if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == v1 && instr->def.bit_size == 16) { emit_vop3p_instruction(ctx, instr, aco_opcode::v_pk_min_f16, dst, true); } else if (dst.regClass() == v1) { emit_vop2_instruction(ctx, instr, aco_opcode::v_min_f32, dst, true, false, @@ -2527,7 +2527,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_fneg: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Temp src = get_alu_src_vop3p(ctx, instr->src[0]); Instruction* vop3p = bld.vop3p(aco_opcode::v_pk_mul_f16, Definition(dst), src, Operand::c16(0x3C00), @@ -2556,7 +2556,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_fabs: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Temp src = get_alu_src_vop3p(ctx, instr->src[0]); Instruction* vop3p = bld.vop3p(aco_opcode::v_pk_max_f16, Definition(dst), src, src, @@ -2591,7 +2591,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) break; } case nir_op_fsat: { - if (dst.regClass() == v1 && instr->dest.dest.ssa.bit_size == 16) { + if (dst.regClass() == v1 && instr->def.bit_size == 16) { Temp src = get_alu_src_vop3p(ctx, instr->src[0]); Instruction* vop3p = bld.vop3p(aco_opcode::v_pk_mul_f16, Definition(dst), src, Operand::c16(0x3C00), @@ -3030,7 +3030,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp tmp = bld.tmp(v1); emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f16, tmp); tmp = bld.vop1(aco_opcode::v_cvt_i32_f32, bld.def(v1), tmp); - tmp = convert_int(ctx, bld, tmp, 32, instr->dest.dest.ssa.bit_size, false, + tmp = convert_int(ctx, bld, tmp, 32, instr->def.bit_size, false, (dst.type() == RegType::sgpr) ? Temp() : dst); if (dst.type() == RegType::sgpr) { bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp); @@ -3053,7 +3053,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) Temp tmp = bld.tmp(v1); emit_vop1_instruction(ctx, instr, aco_opcode::v_cvt_f32_f16, tmp); tmp = bld.vop1(aco_opcode::v_cvt_u32_f32, bld.def(v1), tmp); - tmp = convert_int(ctx, bld, tmp, 32, instr->dest.dest.ssa.bit_size, false, + tmp = convert_int(ctx, bld, tmp, 32, instr->def.bit_size, false, (dst.type() == RegType::sgpr) ? Temp() : dst); if (dst.type() == RegType::sgpr) { bld.pseudo(aco_opcode::p_as_uniform, Definition(dst), tmp); @@ -3157,13 +3157,13 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_i2i32: { if (dst.type() == RegType::sgpr && instr->src[0].src.ssa->bit_size < 32) { /* no need to do the extract in get_alu_src() */ - sgpr_extract_mode mode = instr->dest.dest.ssa.bit_size > instr->src[0].src.ssa->bit_size + sgpr_extract_mode mode = instr->def.bit_size > instr->src[0].src.ssa->bit_size ? sgpr_extract_sext : sgpr_extract_undef; extract_8_16_bit_sgpr_element(ctx, dst, &instr->src[0], mode); } else { const unsigned input_bitsize = instr->src[0].src.ssa->bit_size; - const unsigned output_bitsize = instr->dest.dest.ssa.bit_size; + const unsigned output_bitsize = instr->def.bit_size; convert_int(ctx, bld, get_alu_src(ctx, instr->src[0]), input_bitsize, output_bitsize, output_bitsize > input_bitsize, dst); } @@ -3174,13 +3174,13 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) case nir_op_u2u32: { if (dst.type() == RegType::sgpr && instr->src[0].src.ssa->bit_size < 32) { /* no need to do the extract in get_alu_src() */ - sgpr_extract_mode mode = instr->dest.dest.ssa.bit_size > instr->src[0].src.ssa->bit_size + sgpr_extract_mode mode = instr->def.bit_size > instr->src[0].src.ssa->bit_size ? sgpr_extract_zext : sgpr_extract_undef; extract_8_16_bit_sgpr_element(ctx, dst, &instr->src[0], mode); } else { convert_int(ctx, bld, get_alu_src(ctx, instr->src[0]), instr->src[0].src.ssa->bit_size, - instr->dest.dest.ssa.bit_size, false, dst); + instr->def.bit_size, false, dst); } break; } @@ -3522,17 +3522,17 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) unsigned comp = instr->op == nir_op_extract_u8 || instr->op == nir_op_extract_i8 ? 4 : 2; uint32_t bits = comp == 4 ? 8 : 16; unsigned index = nir_src_as_uint(instr->src[1].src); - if (bits >= instr->dest.dest.ssa.bit_size || index * bits >= instr->dest.dest.ssa.bit_size) { + if (bits >= instr->def.bit_size || index * bits >= instr->def.bit_size) { assert(index == 0); bld.copy(Definition(dst), get_alu_src(ctx, instr->src[0])); - } else if (dst.regClass() == s1 && instr->dest.dest.ssa.bit_size == 16) { + } else if (dst.regClass() == s1 && instr->def.bit_size == 16) { Temp vec = get_ssa_temp(ctx, instr->src[0].src.ssa); unsigned swizzle = instr->src[0].swizzle[0]; if (vec.size() > 1) { vec = emit_extract_vector(ctx, vec, swizzle / 2, s1); swizzle = swizzle & 1; } - index += swizzle * instr->dest.dest.ssa.bit_size / bits; + index += swizzle * instr->def.bit_size / bits; bld.pseudo(aco_opcode::p_extract, Definition(dst), bld.def(s1, scc), Operand(vec), Operand::c32(index), Operand::c32(bits), Operand::c32(is_signed)); } else { @@ -3563,7 +3563,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) unsigned comp = instr->op == nir_op_insert_u8 ? 4 : 2; uint32_t bits = comp == 4 ? 8 : 16; unsigned index = nir_src_as_uint(instr->src[1].src); - if (bits >= instr->dest.dest.ssa.bit_size || index * bits >= instr->dest.dest.ssa.bit_size) { + if (bits >= instr->def.bit_size || index * bits >= instr->def.bit_size) { assert(index == 0); bld.copy(Definition(dst), get_alu_src(ctx, instr->src[0])); } else { diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp b/src/amd/compiler/aco_instruction_selection_setup.cpp index 60709d2..5cbec2b 100644 --- a/src/amd/compiler/aco_instruction_selection_setup.cpp +++ b/src/amd/compiler/aco_instruction_selection_setup.cpp @@ -74,7 +74,7 @@ only_used_by_cross_lane_instrs(nir_def* ssa, bool follow_phis = true) nir_alu_instr* alu = nir_instr_as_alu(src->parent_instr); if (alu->op != nir_op_unpack_64_2x32_split_x && alu->op != nir_op_unpack_64_2x32_split_y) return false; - if (!only_used_by_cross_lane_instrs(&alu->dest.dest.ssa, follow_phis)) + if (!only_used_by_cross_lane_instrs(&alu->def, follow_phis)) return false; continue; @@ -340,8 +340,7 @@ init_context(isel_context* ctx, nir_shader* shader) switch (instr->type) { case nir_instr_type_alu: { nir_alu_instr* alu_instr = nir_instr_as_alu(instr); - RegType type = - alu_instr->dest.dest.ssa.divergent ? RegType::vgpr : RegType::sgpr; + RegType type = alu_instr->def.divergent ? RegType::vgpr : RegType::sgpr; switch (alu_instr->op) { case nir_op_fmul: case nir_op_fmulz: @@ -435,7 +434,7 @@ init_context(isel_context* ctx, nir_shader* shader) case nir_op_ishr: case nir_op_ushr: /* packed 16bit instructions have to be VGPR */ - type = alu_instr->dest.dest.ssa.num_components == 2 ? RegType::vgpr : type; + type = alu_instr->def.num_components == 2 ? RegType::vgpr : type; FALLTHROUGH; default: for (unsigned i = 0; i < nir_op_infos[alu_instr->op].num_inputs; i++) { @@ -445,9 +444,9 @@ init_context(isel_context* ctx, nir_shader* shader) break; } - RegClass rc = get_reg_class(ctx, type, alu_instr->dest.dest.ssa.num_components, - alu_instr->dest.dest.ssa.bit_size); - regclasses[alu_instr->dest.dest.ssa.index] = rc; + RegClass rc = + get_reg_class(ctx, type, alu_instr->def.num_components, alu_instr->def.bit_size); + regclasses[alu_instr->def.index] = rc; break; } case nir_instr_type_load_const: { diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 5f6bf26..49ccc54 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -541,9 +541,9 @@ ac_build_const_int_vec(struct ac_llvm_context *ctx, LLVMTypeRef type, long long static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) { LLVMValueRef src[16], result = NULL; - unsigned num_components = instr->dest.dest.ssa.num_components; + unsigned num_components = instr->def.num_components; unsigned src_components; - LLVMTypeRef def_type = get_def_type(ctx, &instr->dest.dest.ssa); + LLVMTypeRef def_type = get_def_type(ctx, &instr->def); assert(nir_op_infos[instr->op].num_inputs <= ARRAY_SIZE(src)); switch (instr->op) { @@ -589,7 +589,7 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) /* fneg will be optimized by backend compiler with sign * bit removed via XOR. This is probably a LLVM bug. */ - result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); + result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size); } break; case nir_op_inot: @@ -738,7 +738,7 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) /* fabs will be optimized by backend compiler with sign * bit removed via AND. */ - result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); + result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size); } break; case nir_op_fsat: @@ -825,27 +825,27 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) break; case nir_op_frexp_sig: src[0] = ac_to_float(&ctx->ac, src[0]); - result = ac_build_frexp_mant(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size); + result = ac_build_frexp_mant(&ctx->ac, src[0], instr->def.bit_size); break; case nir_op_fmax: result = emit_intrin_2f_param(&ctx->ac, "llvm.maxnum", ac_to_float_type(&ctx->ac, def_type), src[0], src[1]); - if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) { + if (ctx->ac.gfx_level < GFX9 && instr->def.bit_size == 32) { /* Only pre-GFX9 chips do not flush denorms. */ - result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); + result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size); } break; case nir_op_fmin: result = emit_intrin_2f_param(&ctx->ac, "llvm.minnum", ac_to_float_type(&ctx->ac, def_type), src[0], src[1]); - if (ctx->ac.gfx_level < GFX9 && instr->dest.dest.ssa.bit_size == 32) { + if (ctx->ac.gfx_level < GFX9 && instr->def.bit_size == 32) { /* Only pre-GFX9 chips do not flush denorms. */ - result = ac_build_canonicalize(&ctx->ac, result, instr->dest.dest.ssa.bit_size); + result = ac_build_canonicalize(&ctx->ac, result, instr->def.bit_size); } break; case nir_op_ffma: /* FMA is slow on gfx6-8, so it shouldn't be used. */ - assert(instr->dest.dest.ssa.bit_size != 32 || ctx->ac.gfx_level >= GFX9); + assert(instr->def.bit_size != 32 || ctx->ac.gfx_level >= GFX9); result = emit_intrin_3f_param(&ctx->ac, "llvm.fma", ac_to_float_type(&ctx->ac, def_type), src[0], src[1], src[2]); break; @@ -1030,13 +1030,13 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) case nir_op_b2f16: case nir_op_b2f32: case nir_op_b2f64: - result = emit_b2f(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size); + result = emit_b2f(&ctx->ac, src[0], instr->def.bit_size); break; case nir_op_b2i8: case nir_op_b2i16: case nir_op_b2i32: case nir_op_b2i64: - result = emit_b2i(&ctx->ac, src[0], instr->dest.dest.ssa.bit_size); + result = emit_b2i(&ctx->ac, src[0], instr->def.bit_size); break; case nir_op_b2b1: /* after loads */ result = emit_i2b(&ctx->ac, src[0]); @@ -1280,7 +1280,7 @@ static bool visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr) if (result) { result = ac_to_integer_or_pointer(&ctx->ac, result); - ctx->ssa_defs[instr->dest.dest.ssa.index] = result; + ctx->ssa_defs[instr->def.index] = result; } return true; } @@ -4142,7 +4142,7 @@ static bool is_def_used_in_an_export(const nir_def *def) return true; } else if (use_src->parent_instr->type == nir_instr_type_alu) { nir_alu_instr *instr = nir_instr_as_alu(use_src->parent_instr); - if (instr->op == nir_op_vec4 && is_def_used_in_an_export(&instr->dest.dest.ssa)) { + if (instr->op == nir_op_vec4 && is_def_used_in_an_export(&instr->def)) { return true; } } diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index f9fe581..e89405e 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -394,11 +394,11 @@ lower_bit_size_callback(const nir_instr *instr, void *_) /* If an instruction is not scalarized by this point, * it can be emitted as packed instruction */ - if (alu->dest.dest.ssa.num_components > 1) + if (alu->def.num_components > 1) return 0; - if (alu->dest.dest.ssa.bit_size & (8 | 16)) { - unsigned bit_size = alu->dest.dest.ssa.bit_size; + if (alu->def.bit_size & (8 | 16)) { + unsigned bit_size = alu->def.bit_size; switch (alu->op) { case nir_op_bitfield_select: case nir_op_imul_high: @@ -417,10 +417,10 @@ lower_bit_size_callback(const nir_instr *instr, void *_) case nir_op_isign: case nir_op_uadd_sat: case nir_op_usub_sat: - return (bit_size == 8 || !(chip >= GFX8 && alu->dest.dest.ssa.divergent)) ? 32 : 0; + return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0; case nir_op_iadd_sat: case nir_op_isub_sat: - return bit_size == 8 || !alu->dest.dest.ssa.divergent ? 32 : 0; + return bit_size == 8 || !alu->def.divergent ? 32 : 0; default: return 0; @@ -442,7 +442,7 @@ lower_bit_size_callback(const nir_instr *instr, void *_) case nir_op_uge: case nir_op_bitz: case nir_op_bitnz: - return (bit_size == 8 || !(chip >= GFX8 && alu->dest.dest.ssa.divergent)) ? 32 : 0; + return (bit_size == 8 || !(chip >= GFX8 && alu->def.divergent)) ? 32 : 0; default: return 0; } @@ -463,7 +463,7 @@ opt_vectorize_callback(const nir_instr *instr, const void *_) return 1; const nir_alu_instr *alu = nir_instr_as_alu(instr); - const unsigned bit_size = alu->dest.dest.ssa.bit_size; + const unsigned bit_size = alu->def.bit_size; if (bit_size != 16) return 1; diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 0405326..7cff6e1 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -134,7 +134,7 @@ vectorize_vec2_16bit(const nir_instr *instr, const void *_) return 0; const nir_alu_instr *alu = nir_instr_as_alu(instr); - const unsigned bit_size = alu->dest.dest.ssa.bit_size; + const unsigned bit_size = alu->def.bit_size; if (bit_size == 16) return 2; else diff --git a/src/asahi/compiler/agx_compile.c b/src/asahi/compiler/agx_compile.c index 5a83418..7b8f54a 100644 --- a/src/asahi/compiler/agx_compile.c +++ b/src/asahi/compiler/agx_compile.c @@ -1225,9 +1225,9 @@ static agx_instr * agx_emit_alu(agx_builder *b, nir_alu_instr *instr) { unsigned srcs = nir_op_infos[instr->op].num_inputs; - unsigned sz = instr->dest.dest.ssa.bit_size; + unsigned sz = instr->def.bit_size; unsigned src_sz = srcs ? nir_src_bit_size(instr->src[0].src) : 0; - ASSERTED unsigned comps = instr->dest.dest.ssa.num_components; + ASSERTED unsigned comps = instr->def.num_components; assert(comps == 1 || nir_op_is_vec(instr->op)); assert(sz == 1 || @@ -1235,7 +1235,7 @@ agx_emit_alu(agx_builder *b, nir_alu_instr *instr) sz == 8) || sz == 16 || sz == 32 || sz == 64); - agx_index dst = agx_def_index(&instr->dest.dest.ssa); + agx_index dst = agx_def_index(&instr->def); agx_index s0 = srcs > 0 ? agx_alu_src_index(b, instr->src[0]) : agx_null(); agx_index s1 = srcs > 1 ? agx_alu_src_index(b, instr->src[1]) : agx_null(); agx_index s2 = srcs > 2 ? agx_alu_src_index(b, instr->src[2]) : agx_null(); @@ -2461,7 +2461,7 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *_) * implemented natively. */ nir_alu_instr *alu = nir_instr_as_alu(instr); - if (alu->dest.dest.ssa.bit_size == 8 && !is_conversion_to_8bit(alu->op)) + if (alu->def.bit_size == 8 && !is_conversion_to_8bit(alu->op)) return 16; else return 0; diff --git a/src/broadcom/compiler/nir_to_vir.c b/src/broadcom/compiler/nir_to_vir.c index b5e037a..92bb251 100644 --- a/src/broadcom/compiler/nir_to_vir.c +++ b/src/broadcom/compiler/nir_to_vir.c @@ -1360,7 +1360,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) srcs[i] = ntq_get_src(c, instr->src[i].src, instr->src[i].swizzle[0]); for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) - ntq_store_def(c, &instr->dest.dest.ssa, i, + ntq_store_def(c, &instr->def, i, vir_MOV(c, srcs[i])); return; } @@ -1722,7 +1722,7 @@ ntq_emit_alu(struct v3d_compile *c, nir_alu_instr *instr) abort(); } - ntq_store_def(c, &instr->dest.dest.ssa, 0, result); + ntq_store_def(c, &instr->def, 0, result); } /* Each TLB read/write setup (a render target or depth buffer) takes an 8-bit diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 90eb6a7..4bcf070 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -1731,7 +1731,7 @@ get_instr_def(nir_instr *instr) switch (instr->type) { case nir_instr_type_alu: alu_instr = nir_instr_as_alu(instr); - return &alu_instr->dest.dest.ssa; + return &alu_instr->def; case nir_instr_type_intrinsic: intrinsic_instr = nir_instr_as_intrinsic(instr); diff --git a/src/compiler/glsl/tests/test_gl_lower_mediump.cpp b/src/compiler/glsl/tests/test_gl_lower_mediump.cpp index 2824149..352b3f4 100644 --- a/src/compiler/glsl/tests/test_gl_lower_mediump.cpp +++ b/src/compiler/glsl/tests/test_gl_lower_mediump.cpp @@ -82,7 +82,7 @@ namespace { nir_alu_instr *alu = find_op(op); EXPECT_TRUE(alu != NULL); - return alu->dest.dest.ssa.bit_size; + return alu->def.bit_size; } char *get_fs_ir(void) { diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index 39aedb2..d362e9a 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -1290,7 +1290,7 @@ nir_instr_ssa_def(nir_instr *instr) { switch (instr->type) { case nir_instr_type_alu: - return &nir_instr_as_alu(instr)->dest.dest.ssa; + return &nir_instr_as_alu(instr)->def; case nir_instr_type_deref: return &nir_instr_as_deref(instr)->dest.ssa; @@ -2834,7 +2834,7 @@ nir_alu_instr_channel_used(const nir_alu_instr *instr, unsigned src, if (nir_op_infos[instr->op].input_sizes[src] > 0) return channel < nir_op_infos[instr->op].input_sizes[src]; - return channel < instr->dest.dest.ssa.num_components; + return channel < instr->def.num_components; } nir_component_mask_t @@ -2856,7 +2856,7 @@ nir_ssa_alu_instr_src_components(const nir_alu_instr *instr, unsigned src) if (nir_op_infos[instr->op].input_sizes[src] > 0) return nir_op_infos[instr->op].input_sizes[src]; - return instr->dest.dest.ssa.num_components; + return instr->def.num_components; } #define CASE_ALL_SIZES(op) \ diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 8ac01c6..7b82f18 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1120,11 +1120,6 @@ typedef struct { uint8_t swizzle[NIR_MAX_VEC_COMPONENTS]; } nir_alu_src; -typedef struct { - /** Base destination */ - nir_dest dest; -} nir_alu_dest; - /** NIR sized and unsized types * * The values in this enum are carefully chosen so that the sized type is @@ -1446,7 +1441,7 @@ typedef struct nir_alu_instr { bool no_unsigned_wrap : 1; /** Destination */ - nir_alu_dest dest; + nir_def def; /** Sources * diff --git a/src/compiler/nir/nir_builder.c b/src/compiler/nir/nir_builder.c index 53c49b1..2924113 100644 --- a/src/compiler/nir/nir_builder.c +++ b/src/compiler/nir/nir_builder.c @@ -113,12 +113,12 @@ nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr } } - nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_components, + nir_def_init(&instr->instr, &instr->def, num_components, bit_size); nir_builder_instr_insert(build, &instr->instr); - return &instr->dest.dest.ssa; + return &instr->def; } nir_def * @@ -328,12 +328,12 @@ nir_vec_scalars(nir_builder *build, nir_scalar *comp, unsigned num_components) /* Note: not reusing nir_builder_alu_instr_finish_and_insert() because it * can't re-guess the num_components when num_components == 1 (nir_op_mov). */ - nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_components, + nir_def_init(&instr->instr, &instr->def, num_components, comp[0].def->bit_size); nir_builder_instr_insert(build, &instr->instr); - return &instr->dest.dest.ssa; + return &instr->def; } /** diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 43de41d..5767f90 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -509,13 +509,13 @@ nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components) } nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov); - nir_def_init(&mov->instr, &mov->dest.dest.ssa, num_components, + nir_def_init(&mov->instr, &mov->def, num_components, nir_src_bit_size(src.src)); mov->exact = build->exact; mov->src[0] = src; nir_builder_instr_insert(build, &mov->instr); - return &mov->dest.dest.ssa; + return &mov->def; } /** diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c index 4120552..50bb697 100644 --- a/src/compiler/nir/nir_clone.c +++ b/src/compiler/nir/nir_clone.c @@ -219,7 +219,7 @@ clone_alu(clone_state *state, const nir_alu_instr *alu) nalu->no_signed_wrap = alu->no_signed_wrap; nalu->no_unsigned_wrap = alu->no_unsigned_wrap; - __clone_def(state, &nalu->instr, &nalu->dest.dest.ssa, &alu->dest.dest.ssa); + __clone_def(state, &nalu->instr, &nalu->def, &alu->def); for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { __clone_src(state, &nalu->instr, &nalu->src[i].src, &alu->src[i].src); diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index fbb04a8..432c774 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -62,14 +62,14 @@ visit_cf_list(struct exec_list *list, struct divergence_state *state); static bool visit_alu(nir_alu_instr *instr) { - if (instr->dest.dest.ssa.divergent) + if (instr->def.divergent) return false; unsigned num_src = nir_op_infos[instr->op].num_inputs; for (unsigned i = 0; i < num_src; i++) { if (instr->src[i].src.ssa->divergent) { - instr->dest.dest.ssa.divergent = true; + instr->def.divergent = true; return true; } } diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c index c391030..3f2f54b 100644 --- a/src/compiler/nir/nir_gather_info.c +++ b/src/compiler/nir/nir_gather_info.c @@ -853,9 +853,9 @@ gather_alu_info(nir_alu_instr *instr, nir_shader *shader) shader->info.bit_sizes_int |= nir_src_bit_size(instr->src[i].src); } if (nir_alu_type_get_base_type(info->output_type) == nir_type_float) - shader->info.bit_sizes_float |= instr->dest.dest.ssa.bit_size; + shader->info.bit_sizes_float |= instr->def.bit_size; else - shader->info.bit_sizes_int |= instr->dest.dest.ssa.bit_size; + shader->info.bit_sizes_int |= instr->def.bit_size; } static void diff --git a/src/compiler/nir/nir_gather_types.c b/src/compiler/nir/nir_gather_types.c index f3ed461..50c7fe5 100644 --- a/src/compiler/nir/nir_gather_types.c +++ b/src/compiler/nir/nir_gather_types.c @@ -118,7 +118,7 @@ nir_gather_types(nir_function_impl *impl, case nir_op_vec8: case nir_op_vec16: for (unsigned i = 0; i < info->num_inputs; i++) { - copy_types(alu->src[i].src, &alu->dest.dest.ssa, + copy_types(alu->src[i].src, &alu->def, float_types, int_types, &progress); } break; @@ -127,9 +127,9 @@ nir_gather_types(nir_function_impl *impl, case nir_op_b32csel: set_type(alu->src[0].src.ssa->index, nir_type_bool, float_types, int_types, &progress); - copy_types(alu->src[1].src, &alu->dest.dest.ssa, + copy_types(alu->src[1].src, &alu->def, float_types, int_types, &progress); - copy_types(alu->src[2].src, &alu->dest.dest.ssa, + copy_types(alu->src[2].src, &alu->def, float_types, int_types, &progress); break; @@ -139,7 +139,7 @@ nir_gather_types(nir_function_impl *impl, info->input_types[i], float_types, int_types, &progress); } - set_type(alu->dest.dest.ssa.index, info->output_type, + set_type(alu->def.index, info->output_type, float_types, int_types, &progress); } break; diff --git a/src/compiler/nir/nir_inline_helpers.h b/src/compiler/nir/nir_inline_helpers.h index 8d96450..bec7c65 100644 --- a/src/compiler/nir/nir_inline_helpers.h +++ b/src/compiler/nir/nir_inline_helpers.h @@ -6,7 +6,7 @@ _nir_foreach_def(nir_instr *instr, nir_foreach_def_cb cb, void *state) { switch (instr->type) { case nir_instr_type_alu: - return cb(&nir_instr_as_alu(instr)->dest.dest.ssa, state); + return cb(&nir_instr_as_alu(instr)->def, state); case nir_instr_type_deref: return cb(&nir_instr_as_deref(instr)->dest.ssa, state); case nir_instr_type_intrinsic: { diff --git a/src/compiler/nir/nir_instr_set.c b/src/compiler/nir/nir_instr_set.c index 6b93b83..e0d2da7 100644 --- a/src/compiler/nir/nir_instr_set.c +++ b/src/compiler/nir/nir_instr_set.c @@ -84,8 +84,8 @@ hash_alu(uint32_t hash, const nir_alu_instr *instr) instr->no_unsigned_wrap << 1; hash = HASH(hash, flags); - hash = HASH(hash, instr->dest.dest.ssa.num_components); - hash = HASH(hash, instr->dest.dest.ssa.bit_size); + hash = HASH(hash, instr->def.num_components); + hash = HASH(hash, instr->def.bit_size); if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) { assert(nir_op_infos[instr->op].num_inputs >= 2); @@ -516,10 +516,10 @@ nir_instrs_equal(const nir_instr *instr1, const nir_instr *instr2) /* TODO: We can probably acutally do something more inteligent such * as allowing different numbers and taking a maximum or something * here */ - if (alu1->dest.dest.ssa.num_components != alu2->dest.dest.ssa.num_components) + if (alu1->def.num_components != alu2->def.num_components) return false; - if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size) + if (alu1->def.bit_size != alu2->def.bit_size) return false; if (nir_op_infos[alu1->op].algebraic_properties & NIR_OP_IS_2SRC_COMMUTATIVE) { @@ -717,7 +717,7 @@ nir_instr_get_dest_ssa_def(nir_instr *instr) { switch (instr->type) { case nir_instr_type_alu: - return &nir_instr_as_alu(instr)->dest.dest.ssa; + return &nir_instr_as_alu(instr)->def; case nir_instr_type_deref: return &nir_instr_as_deref(instr)->dest.ssa; case nir_instr_type_load_const: diff --git a/src/compiler/nir/nir_legacy.c b/src/compiler/nir/nir_legacy.c index 0c452b8..fb5c40c 100644 --- a/src/compiler/nir/nir_legacy.c +++ b/src/compiler/nir/nir_legacy.c @@ -14,10 +14,10 @@ nir_legacy_float_mod_folds(nir_alu_instr *mod) assert(mod->op == nir_op_fabs || mod->op == nir_op_fneg); /* No legacy user supports fp64 modifiers */ - if (mod->dest.dest.ssa.bit_size == 64) + if (mod->def.bit_size == 64) return false; - nir_foreach_use_including_if(src, &mod->dest.dest.ssa) { + nir_foreach_use_including_if(src, &mod->def) { if (src->is_if) return false; @@ -180,8 +180,8 @@ nir_legacy_fsat_folds(nir_alu_instr *fsat) return false; /* We can't do expansions without a move in the middle */ - unsigned nr_components = generate_alu->dest.dest.ssa.num_components; - if (fsat->dest.dest.ssa.num_components != nr_components) + unsigned nr_components = generate_alu->def.num_components; + if (fsat->def.num_components != nr_components) return false; /* We don't handle swizzles here, so check for the identity */ @@ -213,7 +213,7 @@ chase_fsat(nir_def **def) /* Otherwise, we're good */ nir_alu_instr *alu = nir_instr_as_alu(use->parent_instr); - *def = &alu->dest.dest.ssa; + *def = &alu->def; return true; } @@ -289,7 +289,7 @@ fuse_mods_with_registers(nir_builder *b, nir_instr *instr, void *fuse_fabs_) * already know that they're all float ALU instructions because * nir_legacy_float_mod_folds() returned true. */ - nir_foreach_use_including_if_safe(use, &alu->dest.dest.ssa) { + nir_foreach_use_including_if_safe(use, &alu->def) { assert(!use->is_if); assert(use->parent_instr->type == nir_instr_type_alu); nir_alu_src *alu_use = list_entry(use, nir_alu_src, src); @@ -307,13 +307,13 @@ fuse_mods_with_registers(nir_builder *b, nir_instr *instr, void *fuse_fabs_) } } - nir_legacy_alu_dest dest = nir_legacy_chase_alu_dest(&alu->dest.dest.ssa); + nir_legacy_alu_dest dest = nir_legacy_chase_alu_dest(&alu->def); if (dest.fsat) { nir_intrinsic_instr *store = nir_store_reg_for_def(dest.dest.ssa); if (store) { nir_intrinsic_set_legacy_fsat(store, true); - nir_src_rewrite(&store->src[0], &alu->dest.dest.ssa); + nir_src_rewrite(&store->src[0], &alu->def); return true; } } diff --git a/src/compiler/nir/nir_loop_analyze.c b/src/compiler/nir/nir_loop_analyze.c index e344c04..0b9a2e0 100644 --- a/src/compiler/nir/nir_loop_analyze.c +++ b/src/compiler/nir/nir_loop_analyze.c @@ -178,8 +178,8 @@ instr_cost(loop_info_state *state, nir_instr *instr, /* Also if the selects condition is only used by the select then * remove that alu instructons cost from the cost total also. */ - if (!list_is_singular(&sel_alu->dest.dest.ssa.uses) || - nir_def_used_by_if(&sel_alu->dest.dest.ssa)) + if (!list_is_singular(&sel_alu->def.uses) || + nir_def_used_by_if(&sel_alu->def)) return 0; else return -1; @@ -188,9 +188,9 @@ instr_cost(loop_info_state *state, nir_instr *instr, } if (alu->op == nir_op_flrp) { - if ((options->lower_flrp16 && alu->dest.dest.ssa.bit_size == 16) || - (options->lower_flrp32 && alu->dest.dest.ssa.bit_size == 32) || - (options->lower_flrp64 && alu->dest.dest.ssa.bit_size == 64)) + if ((options->lower_flrp16 && alu->def.bit_size == 16) || + (options->lower_flrp32 && alu->def.bit_size == 32) || + (options->lower_flrp64 && alu->def.bit_size == 64)) cost *= 3; } @@ -199,11 +199,11 @@ instr_cost(loop_info_state *state, nir_instr *instr, * There are no 64-bit ops that don't have a 64-bit thing as their * destination or first source. */ - if (alu->dest.dest.ssa.bit_size < 64 && + if (alu->def.bit_size < 64 && nir_src_bit_size(alu->src[0].src) < 64) return cost; - bool is_fp64 = alu->dest.dest.ssa.bit_size == 64 && + bool is_fp64 = alu->def.bit_size == 64 && nir_alu_type_get_base_type(info->output_type) == nir_type_float; for (unsigned i = 0; i < info->num_inputs; i++) { if (nir_src_bit_size(alu->src[i].src) == 64 && @@ -355,7 +355,7 @@ static bool alu_src_has_identity_swizzle(nir_alu_instr *alu, unsigned src_idx) { assert(nir_op_infos[alu->op].input_sizes[src_idx] == 0); - for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; i++) { + for (unsigned i = 0; i < alu->def.num_components; i++) { if (alu->src[src_idx].swizzle[i] != i) return false; } @@ -436,7 +436,7 @@ compute_induction_information(loop_info_state *state) nir_instr_as_phi(src_var->def->parent_instr); nir_alu_instr *src_phi_alu = phi_instr_as_alu(src_phi); if (src_phi_alu) { - src_var = get_loop_var(&src_phi_alu->dest.dest.ssa, state); + src_var = get_loop_var(&src_phi_alu->def, state); if (!src_var->in_if_branch) break; } @@ -768,7 +768,7 @@ try_eval_const_alu(nir_const_value *dest, nir_alu_instr *alu, */ unsigned bit_size = 0; if (!nir_alu_type_get_type_size(nir_op_infos[alu->op].output_type)) - bit_size = alu->dest.dest.ssa.bit_size; + bit_size = alu->def.bit_size; for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { if (bit_size == 0 && @@ -814,7 +814,7 @@ try_eval_const_alu(nir_const_value *dest, nir_alu_instr *alu, for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; ++i) srcs[i] = src[i]; - nir_eval_const_opcode(alu->op, dest, alu->dest.dest.ssa.num_components, + nir_eval_const_opcode(alu->op, dest, alu->def.num_components, bit_size, srcs, execution_mode); return true; @@ -1030,8 +1030,8 @@ calculate_iterations(nir_def *basis, nir_def *limit_basis, */ unsigned trip_offset = 0; nir_alu_instr *cond_alu = nir_instr_as_alu(cond.def->parent_instr); - if (cond_alu->src[0].src.ssa == &alu->dest.dest.ssa || - cond_alu->src[1].src.ssa == &alu->dest.dest.ssa) { + if (cond_alu->src[0].src.ssa == &alu->def || + cond_alu->src[1].src.ssa == &alu->def) { trip_offset = 1; } diff --git a/src/compiler/nir/nir_lower_alu.c b/src/compiler/nir/nir_lower_alu.c index c967365..675e95b 100644 --- a/src/compiler/nir/nir_lower_alu.c +++ b/src/compiler/nir/nir_lower_alu.c @@ -213,7 +213,7 @@ lower_alu_instr(nir_builder *b, nir_instr *instr_, UNUSED void *cb_data) } if (lowered) { - nir_def_rewrite_uses(&instr->dest.dest.ssa, lowered); + nir_def_rewrite_uses(&instr->def, lowered); nir_instr_remove(&instr->instr); return true; } else { diff --git a/src/compiler/nir/nir_lower_alu_width.c b/src/compiler/nir/nir_lower_alu_width.c index 3b576f9..eb2202f 100644 --- a/src/compiler/nir/nir_lower_alu_width.c +++ b/src/compiler/nir/nir_lower_alu_width.c @@ -51,7 +51,7 @@ inst_is_vector_alu(const nir_instr *instr, const void *_state) /* There is no ALU instruction which has a scalar destination, scalar * src[0], and some other vector source. */ - return alu->dest.dest.ssa.num_components > 1 || + return alu->def.num_components > 1 || nir_op_infos[alu->op].input_sizes[0] > 1; } @@ -76,7 +76,7 @@ alu_is_swizzled_in_bounds(const nir_alu_instr *alu, unsigned width) continue; unsigned mask = ~(width - 1); - for (unsigned j = 1; j < alu->dest.dest.ssa.num_components; j++) { + for (unsigned j = 1; j < alu->def.num_components; j++) { if ((alu->src[i].swizzle[0] & mask) != (alu->src[i].swizzle[j] & mask)) return false; } @@ -89,7 +89,7 @@ static void nir_alu_ssa_dest_init(nir_alu_instr *alu, unsigned num_components, unsigned bit_size) { - nir_def_init(&alu->instr, &alu->dest.dest.ssa, num_components, bit_size); + nir_def_init(&alu->instr, &alu->def, num_components, bit_size); } static nir_def * @@ -102,7 +102,7 @@ lower_reduction(nir_alu_instr *alu, nir_op chan_op, nir_op merge_op, for (int i = 0; i < num_components; i++) { int channel = reverse_order ? num_components - 1 - i : i; nir_alu_instr *chan = nir_alu_instr_create(builder->shader, chan_op); - nir_alu_ssa_dest_init(chan, 1, alu->dest.dest.ssa.bit_size); + nir_alu_ssa_dest_init(chan, 1, alu->def.bit_size); nir_alu_src_copy(&chan->src[0], &alu->src[0], chan); chan->src[0].swizzle[0] = chan->src[0].swizzle[channel]; if (nir_op_infos[chan_op].num_inputs > 1) { @@ -115,10 +115,10 @@ lower_reduction(nir_alu_instr *alu, nir_op chan_op, nir_op merge_op, nir_builder_instr_insert(builder, &chan->instr); if (i == 0) { - last = &chan->dest.dest.ssa; + last = &chan->def; } else { last = nir_build_alu(builder, merge_op, - last, &chan->dest.dest.ssa, NULL, NULL); + last, &chan->def, NULL, NULL); } } @@ -151,7 +151,7 @@ lower_fdot(nir_alu_instr *alu, nir_builder *builder) /* If we don't want to lower ffma, create several ffma instead of fmul+fadd * and fusing later because fusing is not possible for exact fdot instructions. */ - if (will_lower_ffma(builder->shader, alu->dest.dest.ssa.bit_size)) + if (will_lower_ffma(builder->shader, alu->def.bit_size)) return lower_reduction(alu, nir_op_fmul, nir_op_fadd, builder, reverse_order); unsigned num_components = nir_op_infos[alu->op].input_sizes[0]; @@ -161,7 +161,7 @@ lower_fdot(nir_alu_instr *alu, nir_builder *builder) int channel = reverse_order ? num_components - 1 - i : i; nir_alu_instr *instr = nir_alu_instr_create( builder->shader, prev ? nir_op_ffma : nir_op_fmul); - nir_alu_ssa_dest_init(instr, 1, alu->dest.dest.ssa.bit_size); + nir_alu_ssa_dest_init(instr, 1, alu->def.bit_size); for (unsigned j = 0; j < 2; j++) { nir_alu_src_copy(&instr->src[j], &alu->src[j], instr); instr->src[j].swizzle[0] = alu->src[j].swizzle[channel]; @@ -172,7 +172,7 @@ lower_fdot(nir_alu_instr *alu, nir_builder *builder) nir_builder_instr_insert(builder, &instr->instr); - prev = &instr->dest.dest.ssa; + prev = &instr->def; } return prev; @@ -188,7 +188,7 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data) b->exact = alu->exact; - unsigned num_components = alu->dest.dest.ssa.num_components; + unsigned num_components = alu->def.num_components; unsigned target_width = 1; if (data->cb) { @@ -283,7 +283,7 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data) /* Only use reverse order for imprecise fdph, see explanation in lower_fdot. */ bool reverse_order = !b->exact; - if (will_lower_ffma(b->shader, alu->dest.dest.ssa.bit_size)) { + if (will_lower_ffma(b->shader, alu->def.bit_size)) { nir_def *sum[4]; for (unsigned i = 0; i < 3; i++) { int dest = reverse_order ? 3 - i : i; @@ -403,11 +403,11 @@ lower_alu_instr_width(nir_builder *b, nir_instr *instr, void *_data) } } - nir_alu_ssa_dest_init(lower, components, alu->dest.dest.ssa.bit_size); + nir_alu_ssa_dest_init(lower, components, alu->def.bit_size); lower->exact = alu->exact; for (i = 0; i < components; i++) { - vec->src[chan + i].src = nir_src_for_ssa(&lower->dest.dest.ssa); + vec->src[chan + i].src = nir_src_for_ssa(&lower->def); vec->src[chan + i].swizzle[0] = i; } diff --git a/src/compiler/nir/nir_lower_amul.c b/src/compiler/nir/nir_lower_amul.c index ed773a1..7e3ccea 100644 --- a/src/compiler/nir/nir_lower_amul.c +++ b/src/compiler/nir/nir_lower_amul.c @@ -260,7 +260,7 @@ nir_lower_amul(nir_shader *shader, if (alu->op != nir_op_amul) continue; - if (alu->dest.dest.ssa.bit_size <= 32) + if (alu->def.bit_size <= 32) alu->op = nir_op_imul24; else alu->op = nir_op_imul; diff --git a/src/compiler/nir/nir_lower_bit_size.c b/src/compiler/nir/nir_lower_bit_size.c index beb339a..5dc6437 100644 --- a/src/compiler/nir/nir_lower_bit_size.c +++ b/src/compiler/nir/nir_lower_bit_size.c @@ -52,7 +52,7 @@ static void lower_alu_instr(nir_builder *bld, nir_alu_instr *alu, unsigned bit_size) { const nir_op op = alu->op; - unsigned dst_bit_size = alu->dest.dest.ssa.bit_size; + unsigned dst_bit_size = alu->def.bit_size; bld->cursor = nir_before_instr(&alu->instr); @@ -120,9 +120,9 @@ lower_alu_instr(nir_builder *bld, nir_alu_instr *alu, unsigned bit_size) dst_bit_size != bit_size) { nir_alu_type type = nir_op_infos[op].output_type; nir_def *dst = nir_convert_to_bit_size(bld, lowered_dst, type, dst_bit_size); - nir_def_rewrite_uses(&alu->dest.dest.ssa, dst); + nir_def_rewrite_uses(&alu->def, dst); } else { - nir_def_rewrite_uses(&alu->dest.dest.ssa, lowered_dst); + nir_def_rewrite_uses(&alu->def, lowered_dst); } } diff --git a/src/compiler/nir/nir_lower_bool_to_bitsize.c b/src/compiler/nir/nir_lower_bool_to_bitsize.c index 6511fac..730d12e 100644 --- a/src/compiler/nir/nir_lower_bool_to_bitsize.c +++ b/src/compiler/nir/nir_lower_bool_to_bitsize.c @@ -76,8 +76,8 @@ make_sources_canonical(nir_builder *b, nir_alu_instr *alu, uint32_t start_idx) */ nir_alu_instr *conv_instr = nir_instr_as_alu(nir_builder_last_instr(b)); - conv_instr->dest.dest.ssa.num_components = - alu->dest.dest.ssa.num_components; + conv_instr->def.num_components = + alu->def.num_components; memcpy(conv_instr->src[0].swizzle, alu->src[i].swizzle, sizeof(conv_instr->src[0].swizzle)); @@ -112,7 +112,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) case nir_op_iand: case nir_op_ior: case nir_op_ixor: - if (alu->dest.dest.ssa.bit_size > 1) + if (alu->def.bit_size > 1) return false; /* Not a boolean instruction */ FALLTHROUGH; @@ -135,7 +135,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) case nir_op_bcsel: /* bcsel may be choosing between boolean sources too */ - if (alu->dest.dest.ssa.bit_size == 1) + if (alu->def.bit_size == 1) make_sources_canonical(b, alu, 1); break; @@ -296,7 +296,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) break; default: - assert(alu->dest.dest.ssa.bit_size > 1); + assert(alu->def.bit_size > 1); for (unsigned i = 0; i < op_info->num_inputs; i++) assert(alu->src[i].src.ssa->bit_size > 1); return false; @@ -304,8 +304,8 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) alu->op = opcode; - if (alu->dest.dest.ssa.bit_size == 1) - alu->dest.dest.ssa.bit_size = bit_size; + if (alu->def.bit_size == 1) + alu->def.bit_size = bit_size; return true; } diff --git a/src/compiler/nir/nir_lower_bool_to_float.c b/src/compiler/nir/nir_lower_bool_to_float.c index 69923f0..f221679 100644 --- a/src/compiler/nir/nir_lower_bool_to_float.c +++ b/src/compiler/nir/nir_lower_bool_to_float.c @@ -60,7 +60,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu, bool has_fcsel_ne, case nir_op_vec5: case nir_op_vec8: case nir_op_vec16: - if (alu->dest.dest.ssa.bit_size != 1) + if (alu->def.bit_size != 1) return false; /* These we expect to have booleans but the opcode doesn't change */ break; @@ -176,7 +176,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu, bool has_fcsel_ne, break; default: - assert(alu->dest.dest.ssa.bit_size > 1); + assert(alu->def.bit_size > 1); for (unsigned i = 0; i < op_info->num_inputs; i++) assert(alu->src[i].src.ssa->bit_size > 1); return false; @@ -184,11 +184,11 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu, bool has_fcsel_ne, if (rep) { /* We've emitted a replacement instruction */ - nir_def_rewrite_uses(&alu->dest.dest.ssa, rep); + nir_def_rewrite_uses(&alu->def, rep); nir_instr_remove(&alu->instr); } else { - if (alu->dest.dest.ssa.bit_size == 1) - alu->dest.dest.ssa.bit_size = 32; + if (alu->def.bit_size == 1) + alu->def.bit_size = 32; } return true; diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c b/src/compiler/nir/nir_lower_bool_to_int32.c index c72996a..4138380 100644 --- a/src/compiler/nir/nir_lower_bool_to_int32.c +++ b/src/compiler/nir/nir_lower_bool_to_int32.c @@ -59,7 +59,7 @@ lower_alu_instr(nir_alu_instr *alu) case nir_op_iand: case nir_op_ior: case nir_op_ixor: - if (alu->dest.dest.ssa.bit_size != 1) + if (alu->def.bit_size != 1) return false; /* These we expect to have booleans but the opcode doesn't change */ break; @@ -150,14 +150,14 @@ lower_alu_instr(nir_alu_instr *alu) break; default: - assert(alu->dest.dest.ssa.bit_size > 1); + assert(alu->def.bit_size > 1); for (unsigned i = 0; i < op_info->num_inputs; i++) assert(alu->src[i].src.ssa->bit_size > 1); return false; } - if (alu->dest.dest.ssa.bit_size == 1) - alu->dest.dest.ssa.bit_size = 32; + if (alu->def.bit_size == 1) + alu->def.bit_size = 32; return true; } diff --git a/src/compiler/nir/nir_lower_convert_alu_types.c b/src/compiler/nir/nir_lower_convert_alu_types.c index 52ba0d3..14f3561 100644 --- a/src/compiler/nir/nir_lower_convert_alu_types.c +++ b/src/compiler/nir/nir_lower_convert_alu_types.c @@ -192,7 +192,7 @@ lower_alu_conversion(nir_builder *b, nir_instr *instr, UNUSED void *_data) nir_def *src = nir_ssa_for_alu_src(b, alu, 0); nir_alu_type src_type = nir_op_infos[alu->op].input_types[0] | src->bit_size; nir_alu_type dst_type = nir_op_infos[alu->op].output_type; - return nir_convert_alu_types(b, alu->dest.dest.ssa.bit_size, src, + return nir_convert_alu_types(b, alu->def.bit_size, src, .src_type = src_type, .dest_type = dst_type, .rounding_mode = nir_rounding_mode_undef, .saturate = false); diff --git a/src/compiler/nir/nir_lower_double_ops.c b/src/compiler/nir/nir_lower_double_ops.c index 1fcc721..c4d7073 100644 --- a/src/compiler/nir/nir_lower_double_ops.c +++ b/src/compiler/nir/nir_lower_double_ops.c @@ -679,7 +679,7 @@ should_lower_double_instr(const nir_instr *instr, const void *_data) const nir_alu_instr *alu = nir_instr_as_alu(instr); - bool is_64 = alu->dest.dest.ssa.bit_size == 64; + bool is_64 = alu->def.bit_size == 64; unsigned num_srcs = nir_op_infos[alu->op].num_inputs; for (unsigned i = 0; i < num_srcs; i++) { @@ -711,7 +711,7 @@ lower_doubles_instr(nir_builder *b, nir_instr *instr, void *_data) return NULL; nir_def *src = nir_mov_alu(b, alu->src[0], - alu->dest.dest.ssa.num_components); + alu->def.num_components); switch (alu->op) { case nir_op_frcp: @@ -735,7 +735,7 @@ lower_doubles_instr(nir_builder *b, nir_instr *instr, void *_data) case nir_op_fsub: case nir_op_fmod: { nir_def *src1 = nir_mov_alu(b, alu->src[1], - alu->dest.dest.ssa.num_components); + alu->def.num_components); switch (alu->op) { case nir_op_fdiv: return nir_fmul(b, src, nir_frcp(b, src1)); diff --git a/src/compiler/nir/nir_lower_flrp.c b/src/compiler/nir/nir_lower_flrp.c index 73b3a60..2e41ae9 100644 --- a/src/compiler/nir/nir_lower_flrp.c +++ b/src/compiler/nir/nir_lower_flrp.c @@ -60,7 +60,7 @@ replace_with_strict_ffma(struct nir_builder *bld, struct u_vector *dead_flrp, nir_def *const outer_ffma = nir_ffma(bld, b, c, inner_ffma); nir_instr_as_alu(outer_ffma->parent_instr)->exact = alu->exact; - nir_def_rewrite_uses(&alu->dest.dest.ssa, outer_ffma); + nir_def_rewrite_uses(&alu->def, outer_ffma); /* DO NOT REMOVE the original flrp yet. Many of the lowering choices are * based on other uses of the sources. Removing the flrp may cause the @@ -93,7 +93,7 @@ replace_with_single_ffma(struct nir_builder *bld, struct u_vector *dead_flrp, nir_def *const final_ffma = nir_ffma(bld, a, one_minus_c, b_times_c); nir_instr_as_alu(final_ffma->parent_instr)->exact = alu->exact; - nir_def_rewrite_uses(&alu->dest.dest.ssa, final_ffma); + nir_def_rewrite_uses(&alu->def, final_ffma); /* DO NOT REMOVE the original flrp yet. Many of the lowering choices are * based on other uses of the sources. Removing the flrp may cause the @@ -129,7 +129,7 @@ replace_with_strict(struct nir_builder *bld, struct u_vector *dead_flrp, nir_def *const sum = nir_fadd(bld, first_product, second_product); nir_instr_as_alu(sum->parent_instr)->exact = alu->exact; - nir_def_rewrite_uses(&alu->dest.dest.ssa, sum); + nir_def_rewrite_uses(&alu->def, sum); /* DO NOT REMOVE the original flrp yet. Many of the lowering choices are * based on other uses of the sources. Removing the flrp may cause the @@ -161,7 +161,7 @@ replace_with_fast(struct nir_builder *bld, struct u_vector *dead_flrp, nir_def *const sum = nir_fadd(bld, a, product); nir_instr_as_alu(sum->parent_instr)->exact = alu->exact; - nir_def_rewrite_uses(&alu->dest.dest.ssa, sum); + nir_def_rewrite_uses(&alu->def, sum); /* DO NOT REMOVE the original flrp yet. Many of the lowering choices are * based on other uses of the sources. Removing the flrp may cause the @@ -203,7 +203,7 @@ replace_with_expanded_ffma_and_add(struct nir_builder *bld, nir_def *const outer_sum = nir_fadd(bld, inner_sum, b_times_c); nir_instr_as_alu(outer_sum->parent_instr)->exact = alu->exact; - nir_def_rewrite_uses(&alu->dest.dest.ssa, outer_sum); + nir_def_rewrite_uses(&alu->def, outer_sum); /* DO NOT REMOVE the original flrp yet. Many of the lowering choices are * based on other uses of the sources. Removing the flrp may cause the @@ -230,9 +230,9 @@ all_same_constant(const nir_alu_instr *instr, unsigned src, double *result) return false; const uint8_t *const swizzle = instr->src[src].swizzle; - const unsigned num_components = instr->dest.dest.ssa.num_components; + const unsigned num_components = instr->def.num_components; - if (instr->dest.dest.ssa.bit_size == 32) { + if (instr->def.bit_size == 32) { const float first = val[swizzle[0]].f32; for (unsigned i = 1; i < num_components; i++) { @@ -266,9 +266,9 @@ sources_are_constants_with_similar_magnitudes(const nir_alu_instr *instr) const uint8_t *const swizzle0 = instr->src[0].swizzle; const uint8_t *const swizzle1 = instr->src[1].swizzle; - const unsigned num_components = instr->dest.dest.ssa.num_components; + const unsigned num_components = instr->def.num_components; - if (instr->dest.dest.ssa.bit_size == 32) { + if (instr->def.bit_size == 32) { for (unsigned i = 0; i < num_components; i++) { int exp0; int exp1; @@ -367,7 +367,7 @@ convert_flrp_instruction(nir_builder *bld, bool always_precise) { bool have_ffma = false; - unsigned bit_size = alu->dest.dest.ssa.bit_size; + unsigned bit_size = alu->def.bit_size; if (bit_size == 16) have_ffma = !bld->shader->options->lower_ffma16; @@ -607,7 +607,7 @@ lower_flrp_impl(nir_function_impl *impl, nir_alu_instr *const alu = nir_instr_as_alu(instr); if (alu->op == nir_op_flrp && - (alu->dest.dest.ssa.bit_size & lowering_mask)) { + (alu->def.bit_size & lowering_mask)) { convert_flrp_instruction(&b, dead_flrp, alu, always_precise); } } diff --git a/src/compiler/nir/nir_lower_fp16_conv.c b/src/compiler/nir/nir_lower_fp16_conv.c index f2c74a1..057a355 100644 --- a/src/compiler/nir/nir_lower_fp16_conv.c +++ b/src/compiler/nir/nir_lower_fp16_conv.c @@ -179,7 +179,7 @@ lower_fp16_cast_impl(nir_builder *b, nir_instr *instr, void *data) nir_alu_instr *alu = nir_instr_as_alu(instr); src = alu->src[0].src.ssa; swizzle = alu->src[0].swizzle; - dst = &alu->dest.dest.ssa; + dst = &alu->def; switch (alu->op) { case nir_op_f2f16: if (b->shader->info.float_controls_execution_mode & FLOAT_CONTROLS_ROUNDING_MODE_RTZ_FP16) diff --git a/src/compiler/nir/nir_lower_frexp.c b/src/compiler/nir/nir_lower_frexp.c index 7e0a5c2..31a9e83 100644 --- a/src/compiler/nir/nir_lower_frexp.c +++ b/src/compiler/nir/nir_lower_frexp.c @@ -180,7 +180,7 @@ lower_frexp_instr(nir_builder *b, nir_instr *instr, UNUSED void *cb_data) return false; } - nir_def_rewrite_uses(&alu_instr->dest.dest.ssa, lower); + nir_def_rewrite_uses(&alu_instr->def, lower); nir_instr_remove(instr); return true; } diff --git a/src/compiler/nir/nir_lower_idiv.c b/src/compiler/nir/nir_lower_idiv.c index b828254..16acadc 100644 --- a/src/compiler/nir/nir_lower_idiv.c +++ b/src/compiler/nir/nir_lower_idiv.c @@ -157,7 +157,7 @@ inst_is_idiv(const nir_instr *instr, UNUSED const void *_state) nir_alu_instr *alu = nir_instr_as_alu(instr); - if (alu->dest.dest.ssa.bit_size > 32) + if (alu->def.bit_size > 32) return false; switch (alu->op) { diff --git a/src/compiler/nir/nir_lower_int64.c b/src/compiler/nir/nir_lower_int64.c index b9d322d..b015700 100644 --- a/src/compiler/nir/nir_lower_int64.c +++ b/src/compiler/nir/nir_lower_int64.c @@ -1060,11 +1060,11 @@ lower_int64_alu_instr(nir_builder *b, nir_alu_instr *alu) case nir_op_i2f64: case nir_op_i2f32: case nir_op_i2f16: - return lower_2f(b, src[0], alu->dest.dest.ssa.bit_size, true); + return lower_2f(b, src[0], alu->def.bit_size, true); case nir_op_u2f64: case nir_op_u2f32: case nir_op_u2f16: - return lower_2f(b, src[0], alu->dest.dest.ssa.bit_size, false); + return lower_2f(b, src[0], alu->def.bit_size, false); case nir_op_f2i64: case nir_op_f2u64: return lower_f2(b, src[0], alu->op == nir_op_f2i64); @@ -1113,7 +1113,7 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_amul: if (options->has_imul24) return false; - if (alu->dest.dest.ssa.bit_size != 64) + if (alu->def.bit_size != 64) return false; break; case nir_op_i2f64: @@ -1129,7 +1129,7 @@ should_lower_int64_alu_instr(const nir_alu_instr *alu, case nir_op_f2i64: FALLTHROUGH; default: - if (alu->dest.dest.ssa.bit_size != 64) + if (alu->def.bit_size != 64) return false; break; } diff --git a/src/compiler/nir/nir_lower_int_to_float.c b/src/compiler/nir/nir_lower_int_to_float.c index 41406e2..906390b 100644 --- a/src/compiler/nir/nir_lower_int_to_float.c +++ b/src/compiler/nir/nir_lower_int_to_float.c @@ -39,7 +39,7 @@ instr_has_only_trivial_swizzles(nir_alu_instr *alu) const nir_op_info *info = &nir_op_infos[alu->op]; for (unsigned i = 0; i < info->num_inputs; i++) { - for (unsigned chan = 0; chan < alu->dest.dest.ssa.num_components; chan++) { + for (unsigned chan = 0; chan < alu->def.num_components; chan++) { if (alu->src[i].swizzle[chan] != chan) return false; } @@ -83,7 +83,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) { const nir_op_info *info = &nir_op_infos[alu->op]; - bool is_bool_only = alu->dest.dest.ssa.bit_size == 1; + bool is_bool_only = alu->def.bit_size == 1; for (unsigned i = 0; i < info->num_inputs; i++) { if (alu->src[i].src.ssa->bit_size != 1) is_bool_only = false; @@ -247,7 +247,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) if (rep) { /* We've emitted a replacement instruction */ - nir_def_rewrite_uses(&alu->dest.dest.ssa, rep); + nir_def_rewrite_uses(&alu->def, rep); nir_instr_remove(&alu->instr); } diff --git a/src/compiler/nir/nir_lower_packing.c b/src/compiler/nir/nir_lower_packing.c index adabc14..24493de 100644 --- a/src/compiler/nir/nir_lower_packing.c +++ b/src/compiler/nir/nir_lower_packing.c @@ -142,7 +142,7 @@ lower_pack_instr(nir_builder *b, nir_instr *instr, void *data) default: unreachable("Impossible opcode"); } - nir_def_rewrite_uses(&alu_instr->dest.dest.ssa, dest); + nir_def_rewrite_uses(&alu_instr->def, dest); nir_instr_remove(&alu_instr->instr); return true; diff --git a/src/compiler/nir/nir_lower_phis_to_scalar.c b/src/compiler/nir/nir_lower_phis_to_scalar.c index 8b41141..5b5a69f 100644 --- a/src/compiler/nir/nir_lower_phis_to_scalar.c +++ b/src/compiler/nir/nir_lower_phis_to_scalar.c @@ -201,7 +201,7 @@ lower_phis_to_scalar_block(nir_block *block, nir_op vec_op = nir_op_vec(phi->dest.ssa.num_components); nir_alu_instr *vec = nir_alu_instr_create(state->shader, vec_op); - nir_def_init(&vec->instr, &vec->dest.dest.ssa, + nir_def_init(&vec->instr, &vec->def, phi->dest.ssa.num_components, bit_size); for (unsigned i = 0; i < phi->dest.ssa.num_components; i++) { @@ -215,7 +215,7 @@ lower_phis_to_scalar_block(nir_block *block, /* We need to insert a mov to grab the i'th component of src */ nir_alu_instr *mov = nir_alu_instr_create(state->shader, nir_op_mov); - nir_def_init(&mov->instr, &mov->dest.dest.ssa, 1, bit_size); + nir_def_init(&mov->instr, &mov->def, 1, bit_size); nir_src_copy(&mov->src[0].src, &src->src, &mov->instr); mov->src[0].swizzle[0] = i; @@ -226,7 +226,7 @@ lower_phis_to_scalar_block(nir_block *block, else nir_instr_insert_after_block(src->pred, &mov->instr); - nir_phi_instr_add_src(new_phi, src->pred, nir_src_for_ssa(&mov->dest.dest.ssa)); + nir_phi_instr_add_src(new_phi, src->pred, nir_src_for_ssa(&mov->def)); } nir_instr_insert_before(&phi->instr, &new_phi->instr); @@ -235,7 +235,7 @@ lower_phis_to_scalar_block(nir_block *block, nir_instr_insert_after(&last_phi->instr, &vec->instr); nir_def_rewrite_uses(&phi->dest.ssa, - &vec->dest.dest.ssa); + &vec->def); nir_instr_remove(&phi->instr); exec_list_push_tail(&state->dead_instrs, &phi->instr.node); diff --git a/src/compiler/nir/nir_lower_shader_calls.c b/src/compiler/nir/nir_lower_shader_calls.c index b27b653..a120dee 100644 --- a/src/compiler/nir/nir_lower_shader_calls.c +++ b/src/compiler/nir/nir_lower_shader_calls.c @@ -1562,7 +1562,7 @@ nir_opt_trim_stack_values(nir_shader *shader) nir_alu_instr *alu = nir_instr_as_alu(use_src->parent_instr); nir_alu_src *alu_src = exec_node_data(nir_alu_src, use_src, src); - unsigned count = alu->dest.dest.ssa.num_components; + unsigned count = alu->def.num_components; for (unsigned idx = 0; idx < count; ++idx) alu_src->swizzle[idx] = swiz_map[alu_src->swizzle[idx]]; } else if (use_src->parent_instr->type == nir_instr_type_intrinsic) { diff --git a/src/compiler/nir/nir_lower_vars_to_ssa.c b/src/compiler/nir/nir_lower_vars_to_ssa.c index dcf9811..f857f86 100644 --- a/src/compiler/nir/nir_lower_vars_to_ssa.c +++ b/src/compiler/nir/nir_lower_vars_to_ssa.c @@ -602,14 +602,14 @@ rename_variables(struct lower_variables_state *state) for (unsigned i = intrin->num_components; i < NIR_MAX_VEC_COMPONENTS; i++) mov->src[0].swizzle[i] = 0; - nir_def_init(&mov->instr, &mov->dest.dest.ssa, + nir_def_init(&mov->instr, &mov->def, intrin->num_components, intrin->dest.ssa.bit_size); nir_instr_insert_before(&intrin->instr, &mov->instr); nir_instr_remove(&intrin->instr); nir_def_rewrite_uses(&intrin->dest.ssa, - &mov->dest.dest.ssa); + &mov->def); break; } diff --git a/src/compiler/nir/nir_lower_vec_to_regs.c b/src/compiler/nir/nir_lower_vec_to_regs.c index aa38135..4a85121 100644 --- a/src/compiler/nir/nir_lower_vec_to_regs.c +++ b/src/compiler/nir/nir_lower_vec_to_regs.c @@ -32,7 +32,7 @@ insert_store(nir_builder *b, nir_def *reg, nir_alu_instr *vec, assert(start_idx < nir_op_infos[vec->op].num_inputs); nir_def *src = vec->src[start_idx].src.ssa; - unsigned num_components = vec->dest.dest.ssa.num_components; + unsigned num_components = vec->def.num_components; assert(num_components == nir_op_infos[vec->op].num_inputs); unsigned write_mask = 0; unsigned swiz[NIR_MAX_VEC_COMPONENTS] = { 0 }; @@ -125,13 +125,13 @@ try_coalesce(nir_builder *b, nir_def *reg, nir_alu_instr *vec, for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) swizzles[j][i] = src_alu->src[j].swizzle[i]; - unsigned dest_components = vec->dest.dest.ssa.num_components; + unsigned dest_components = vec->def.num_components; assert(dest_components == nir_op_infos[vec->op].num_inputs); /* Generate the final write mask */ nir_component_mask_t write_mask = 0; for (unsigned i = start_idx; i < dest_components; i++) { - if (vec->src[i].src.ssa != &src_alu->dest.dest.ssa) + if (vec->src[i].src.ssa != &src_alu->def) continue; write_mask |= BITFIELD_BIT(i); @@ -169,19 +169,19 @@ try_coalesce(nir_builder *b, nir_def *reg, nir_alu_instr *vec, } /* We've cleared the only use of the destination */ - assert(list_is_empty(&src_alu->dest.dest.ssa.uses)); + assert(list_is_empty(&src_alu->def.uses)); /* ... so we can replace it with the bigger destination accommodating the * whole vector that will be masked for the store. */ - unsigned bit_size = vec->dest.dest.ssa.bit_size; - assert(bit_size == src_alu->dest.dest.ssa.bit_size); - nir_def_init(&src_alu->instr, &src_alu->dest.dest.ssa, dest_components, + unsigned bit_size = vec->def.bit_size; + assert(bit_size == src_alu->def.bit_size); + nir_def_init(&src_alu->instr, &src_alu->def, dest_components, bit_size); /* Then we can store that ALU result directly into the register */ b->cursor = nir_after_instr(&src_alu->instr); - nir_build_store_reg(b, &src_alu->dest.dest.ssa, + nir_build_store_reg(b, &src_alu->def, reg, .write_mask = write_mask); return write_mask; @@ -198,7 +198,7 @@ lower(nir_builder *b, nir_instr *instr, void *data_) if (vec->op == nir_op_mov || !nir_op_is_vec(vec->op)) return false; - unsigned num_components = vec->dest.dest.ssa.num_components; + unsigned num_components = vec->def.num_components; /* Special case: if all sources are the same, just swizzle instead to avoid * the extra copies from a register. @@ -214,7 +214,7 @@ lower(nir_builder *b, nir_instr *instr, void *data_) if (need_reg) { /* We'll replace with a register. Declare one for the purpose. */ nir_def *reg = nir_decl_reg(b, num_components, - vec->dest.dest.ssa.bit_size, 0); + vec->def.bit_size, 0); unsigned finished_write_mask = 0; for (unsigned i = 0; i < num_components; i++) { @@ -227,7 +227,7 @@ lower(nir_builder *b, nir_instr *instr, void *data_) finished_write_mask |= insert_store(b, reg, vec, i); } - nir_rewrite_uses_to_load_reg(b, &vec->dest.dest.ssa, reg); + nir_rewrite_uses_to_load_reg(b, &vec->def, reg); } else { /* Otherwise, we replace with a swizzle */ unsigned swiz[NIR_MAX_VEC_COMPONENTS] = { 0 }; @@ -239,7 +239,7 @@ lower(nir_builder *b, nir_instr *instr, void *data_) b->cursor = nir_before_instr(instr); nir_def *swizzled = nir_swizzle(b, vec->src[0].src.ssa, swiz, num_components); - nir_def_rewrite_uses(&vec->dest.dest.ssa, swizzled); + nir_def_rewrite_uses(&vec->def, swizzled); } nir_instr_remove(&vec->instr); diff --git a/src/compiler/nir/nir_mod_analysis.c b/src/compiler/nir/nir_mod_analysis.c index 4868b8b..2828837 100644 --- a/src/compiler/nir/nir_mod_analysis.c +++ b/src/compiler/nir/nir_mod_analysis.c @@ -85,7 +85,7 @@ nir_mod_analysis(nir_scalar val, nir_alu_type val_type, unsigned div, unsigned * case nir_instr_type_alu: { nir_alu_instr *alu = nir_instr_as_alu(val.def->parent_instr); - if (alu->dest.dest.ssa.num_components != 1) + if (alu->def.num_components != 1) return false; switch (alu->op) { diff --git a/src/compiler/nir/nir_move_vec_src_uses_to_dest.c b/src/compiler/nir/nir_move_vec_src_uses_to_dest.c index 371388a..9285650 100644 --- a/src/compiler/nir/nir_move_vec_src_uses_to_dest.c +++ b/src/compiler/nir/nir_move_vec_src_uses_to_dest.c @@ -110,7 +110,7 @@ move_vec_src_uses_to_dest_block(nir_block *block) continue; /* We need to dominate the use if we are going to rewrite it */ - if (!ssa_def_dominates_instr(&vec->dest.dest.ssa, use->parent_instr)) + if (!ssa_def_dominates_instr(&vec->def, use->parent_instr)) continue; /* For now, we'll just rewrite ALU instructions */ @@ -143,7 +143,7 @@ move_vec_src_uses_to_dest_block(nir_block *block) * Go ahead and rewrite it as needed. */ nir_instr_rewrite_src(use->parent_instr, use, - nir_src_for_ssa(&vec->dest.dest.ssa)); + nir_src_for_ssa(&vec->def)); for (unsigned j = 0; j < 4; j++) { if (!nir_alu_instr_channel_used(use_alu, src_idx, j)) continue; diff --git a/src/compiler/nir/nir_opt_comparison_pre.c b/src/compiler/nir/nir_opt_comparison_pre.c index 9bda104..191833a 100644 --- a/src/compiler/nir/nir_opt_comparison_pre.c +++ b/src/compiler/nir/nir_opt_comparison_pre.c @@ -143,7 +143,7 @@ is_compatible_condition(const nir_alu_instr *instr) if (is_used_by_if(instr)) return true; - nir_foreach_use(src, &instr->dest.dest.ssa) { + nir_foreach_use(src, &instr->def) { const nir_instr *const user_instr = src->parent_instr; if (user_instr->type != nir_instr_type_alu) @@ -187,7 +187,7 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp, : nir_fadd(bld, a, nir_fneg(bld, b)); nir_def *const zero = - nir_imm_floatN_t(bld, 0.0, orig_add->dest.dest.ssa.bit_size); + nir_imm_floatN_t(bld, 0.0, orig_add->def.bit_size); nir_def *const cmp = zero_on_left ? nir_build_alu(bld, orig_cmp->op, zero, fadd, NULL, NULL) @@ -199,25 +199,25 @@ rewrite_compare_instruction(nir_builder *bld, nir_alu_instr *orig_cmp, * nir_search.c). */ nir_alu_instr *mov_add = nir_alu_instr_create(bld->shader, nir_op_mov); - nir_def_init(&mov_add->instr, &mov_add->dest.dest.ssa, - orig_add->dest.dest.ssa.num_components, - orig_add->dest.dest.ssa.bit_size); + nir_def_init(&mov_add->instr, &mov_add->def, + orig_add->def.num_components, + orig_add->def.bit_size); mov_add->src[0].src = nir_src_for_ssa(fadd); nir_builder_instr_insert(bld, &mov_add->instr); nir_alu_instr *mov_cmp = nir_alu_instr_create(bld->shader, nir_op_mov); - nir_def_init(&mov_cmp->instr, &mov_cmp->dest.dest.ssa, - orig_cmp->dest.dest.ssa.num_components, - orig_cmp->dest.dest.ssa.bit_size); + nir_def_init(&mov_cmp->instr, &mov_cmp->def, + orig_cmp->def.num_components, + orig_cmp->def.bit_size); mov_cmp->src[0].src = nir_src_for_ssa(cmp); nir_builder_instr_insert(bld, &mov_cmp->instr); - nir_def_rewrite_uses(&orig_cmp->dest.dest.ssa, - &mov_cmp->dest.dest.ssa); - nir_def_rewrite_uses(&orig_add->dest.dest.ssa, - &mov_add->dest.dest.ssa); + nir_def_rewrite_uses(&orig_cmp->def, + &mov_cmp->def); + nir_def_rewrite_uses(&orig_add->def, + &mov_add->def); /* We know these have no more uses because we just rewrote them all, so we * can remove them. @@ -253,7 +253,7 @@ comparison_pre_block(nir_block *block, struct block_queue *bq, nir_builder *bld) nir_alu_instr *const alu = nir_instr_as_alu(instr); - if (alu->dest.dest.ssa.num_components != 1) + if (alu->def.num_components != 1) continue; static const uint8_t swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 }; diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index 3d2aefc..1bbfba5 100644 --- a/src/compiler/nir/nir_opt_constant_folding.c +++ b/src/compiler/nir/nir_opt_constant_folding.c @@ -52,7 +52,7 @@ try_fold_alu(nir_builder *b, nir_alu_instr *alu) */ unsigned bit_size = 0; if (!nir_alu_type_get_type_size(nir_op_infos[alu->op].output_type)) - bit_size = alu->dest.dest.ssa.bit_size; + bit_size = alu->def.bit_size; for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { if (bit_size == 0 && @@ -79,15 +79,15 @@ try_fold_alu(nir_builder *b, nir_alu_instr *alu) memset(dest, 0, sizeof(dest)); for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; ++i) srcs[i] = src[i]; - nir_eval_const_opcode(alu->op, dest, alu->dest.dest.ssa.num_components, + nir_eval_const_opcode(alu->op, dest, alu->def.num_components, bit_size, srcs, b->shader->info.float_controls_execution_mode); b->cursor = nir_before_instr(&alu->instr); - nir_def *imm = nir_build_imm(b, alu->dest.dest.ssa.num_components, - alu->dest.dest.ssa.bit_size, + nir_def *imm = nir_build_imm(b, alu->def.num_components, + alu->def.bit_size, dest); - nir_def_rewrite_uses(&alu->dest.dest.ssa, imm); + nir_def_rewrite_uses(&alu->def, imm); nir_instr_remove(&alu->instr); nir_instr_free(&alu->instr); diff --git a/src/compiler/nir/nir_opt_copy_propagate.c b/src/compiler/nir/nir_opt_copy_propagate.c index bf7e732..6945e20 100644 --- a/src/compiler/nir/nir_opt_copy_propagate.c +++ b/src/compiler/nir/nir_opt_copy_propagate.c @@ -35,7 +35,7 @@ static bool is_swizzleless_move(nir_alu_instr *instr) { - unsigned num_comp = instr->dest.dest.ssa.num_components; + unsigned num_comp = instr->def.num_components; if (instr->src[0].src.ssa->num_components != num_comp) return false; @@ -64,13 +64,13 @@ rewrite_to_vec(nir_alu_instr *mov, nir_alu_instr *vec) nir_builder b = nir_builder_at(nir_after_instr(&mov->instr)); - unsigned num_comp = mov->dest.dest.ssa.num_components; + unsigned num_comp = mov->def.num_components; nir_alu_instr *new_vec = nir_alu_instr_create(b.shader, nir_op_vec(num_comp)); for (unsigned i = 0; i < num_comp; i++) new_vec->src[i] = vec->src[mov->src[0].swizzle[i]]; nir_def *new = nir_builder_alu_instr_finish_and_insert(&b, new_vec); - nir_def_rewrite_uses(&mov->dest.dest.ssa, new); + nir_def_rewrite_uses(&mov->def, new); /* If we remove "mov" and it's the next instruction in the * nir_foreach_instr_safe() loop, then we would end copy-propagation early. */ @@ -133,14 +133,14 @@ copy_prop_instr(nir_instr *instr) bool progress = false; - nir_foreach_use_including_if_safe(src, &mov->dest.dest.ssa) { + nir_foreach_use_including_if_safe(src, &mov->def) { if (!src->is_if && src->parent_instr->type == nir_instr_type_alu) progress |= copy_propagate_alu(container_of(src, nir_alu_src, src), mov); else progress |= copy_propagate(src, mov); } - if (progress && nir_def_is_unused(&mov->dest.dest.ssa)) + if (progress && nir_def_is_unused(&mov->def)) nir_instr_remove(&mov->instr); return progress; diff --git a/src/compiler/nir/nir_opt_dce.c b/src/compiler/nir/nir_opt_dce.c index 9b27a5c..dc9b6ef 100644 --- a/src/compiler/nir/nir_opt_dce.c +++ b/src/compiler/nir/nir_opt_dce.c @@ -60,7 +60,7 @@ is_live(BITSET_WORD *defs_live, nir_instr *instr) return true; case nir_instr_type_alu: { nir_alu_instr *alu = nir_instr_as_alu(instr); - return is_def_live(&alu->dest.dest.ssa, defs_live); + return is_def_live(&alu->def, defs_live); } case nir_instr_type_deref: { nir_deref_instr *deref = nir_instr_as_deref(instr); diff --git a/src/compiler/nir/nir_opt_idiv_const.c b/src/compiler/nir/nir_opt_idiv_const.c index 06c4c17..ade23c3 100644 --- a/src/compiler/nir/nir_opt_idiv_const.c +++ b/src/compiler/nir/nir_opt_idiv_const.c @@ -161,7 +161,7 @@ nir_opt_idiv_const_instr(nir_builder *b, nir_instr *instr, void *user_data) alu->op != nir_op_irem) return false; - if (alu->dest.dest.ssa.bit_size < *min_bit_size) + if (alu->def.bit_size < *min_bit_size) return false; if (!nir_src_is_const(alu->src[1].src)) @@ -172,7 +172,7 @@ nir_opt_idiv_const_instr(nir_builder *b, nir_instr *instr, void *user_data) b->cursor = nir_before_instr(&alu->instr); nir_def *q[NIR_MAX_VEC_COMPONENTS]; - for (unsigned comp = 0; comp < alu->dest.dest.ssa.num_components; comp++) { + for (unsigned comp = 0; comp < alu->def.num_components; comp++) { /* Get the numerator for the channel */ nir_def *n = nir_channel(b, alu->src[0].src.ssa, alu->src[0].swizzle[comp]); @@ -212,8 +212,8 @@ nir_opt_idiv_const_instr(nir_builder *b, nir_instr *instr, void *user_data) } } - nir_def *qvec = nir_vec(b, q, alu->dest.dest.ssa.num_components); - nir_def_rewrite_uses(&alu->dest.dest.ssa, qvec); + nir_def *qvec = nir_vec(b, q, alu->def.num_components); + nir_def_rewrite_uses(&alu->def, qvec); nir_instr_remove(&alu->instr); return true; diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c index 442db28..e005db2 100644 --- a/src/compiler/nir/nir_opt_if.c +++ b/src/compiler/nir/nir_opt_if.c @@ -469,10 +469,10 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop) if (!is_prev_result_undef && !is_prev_result_const) { /* check if the only user is a trivial bcsel */ - if (!list_is_singular(&alu->dest.dest.ssa.uses)) + if (!list_is_singular(&alu->def.uses)) continue; - nir_src *use = list_first_entry(&alu->dest.dest.ssa.uses, nir_src, use_link); + nir_src *use = list_first_entry(&alu->def.uses, nir_src, use_link); if (use->is_if || !is_trivial_bcsel(use->parent_instr, true)) continue; } @@ -508,7 +508,7 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop) /* Modify all readers of the original ALU instruction to read the * result of the phi. */ - nir_def_rewrite_uses(&alu->dest.dest.ssa, + nir_def_rewrite_uses(&alu->def, &phi->dest.ssa); /* Since the original ALU instruction no longer has any readers, just @@ -664,8 +664,8 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop) ->src); nir_def_init(&phi->instr, &phi->dest.ssa, - bcsel->dest.dest.ssa.num_components, - bcsel->dest.dest.ssa.bit_size); + bcsel->def.num_components, + bcsel->def.bit_size); b->cursor = nir_after_phis(header_block); nir_builder_instr_insert(b, &phi->instr); @@ -673,7 +673,7 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop) /* Modify all readers of the bcsel instruction to read the result of * the phi. */ - nir_def_rewrite_uses(&bcsel->dest.dest.ssa, + nir_def_rewrite_uses(&bcsel->def, &phi->dest.ssa); /* Since the original bcsel instruction no longer has any readers, @@ -874,7 +874,7 @@ opt_if_simplification(nir_builder *b, nir_if *nif) b->cursor = nir_after_instr(&alu_instr->instr); nir_def *new_condition = - nir_inot(b, &alu_instr->dest.dest.ssa); + nir_inot(b, &alu_instr->def); nir_if_rewrite_condition(nif, nir_src_for_ssa(new_condition)); @@ -1184,9 +1184,9 @@ clone_alu_and_replace_src_defs(nir_builder *b, const nir_alu_instr *alu, nir_alu_instr *nalu = nir_alu_instr_create(b->shader, alu->op); nalu->exact = alu->exact; - nir_def_init(&nalu->instr, &nalu->dest.dest.ssa, - alu->dest.dest.ssa.num_components, - alu->dest.dest.ssa.bit_size); + nir_def_init(&nalu->instr, &nalu->def, + alu->def.num_components, + alu->def.bit_size); for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { nalu->src[i].src = nir_src_for_ssa(src_defs[i]); @@ -1196,7 +1196,7 @@ clone_alu_and_replace_src_defs(nir_builder *b, const nir_alu_instr *alu, nir_builder_instr_insert(b, &nalu->instr); - return &nalu->dest.dest.ssa; + return &nalu->def; ; } @@ -1320,7 +1320,7 @@ evaluate_condition_use(nir_builder *b, nir_if *nif, nir_src *use_src) if (!use_src->is_if && can_propagate_through_alu(use_src)) { nir_alu_instr *alu = nir_instr_as_alu(use_src->parent_instr); - nir_foreach_use_including_if_safe(alu_use, &alu->dest.dest.ssa) + nir_foreach_use_including_if_safe(alu_use, &alu->def) progress |= propagate_condition_eval(b, nif, use_src, alu_use, alu); } diff --git a/src/compiler/nir/nir_opt_intrinsics.c b/src/compiler/nir/nir_opt_intrinsics.c index 541842c..a07fcee 100644 --- a/src/compiler/nir/nir_opt_intrinsics.c +++ b/src/compiler/nir/nir_opt_intrinsics.c @@ -223,7 +223,7 @@ opt_intrinsics_alu(nir_builder *b, nir_alu_instr *alu, break; case nir_op_iand: case nir_op_ior: - if (alu->dest.dest.ssa.bit_size == 1 && options->optimize_quad_vote_to_reduce) + if (alu->def.bit_size == 1 && options->optimize_quad_vote_to_reduce) replacement = try_opt_quad_vote(b, alu, block_has_discard); break; default: @@ -231,7 +231,7 @@ opt_intrinsics_alu(nir_builder *b, nir_alu_instr *alu, } if (replacement) { - nir_def_rewrite_uses(&alu->dest.dest.ssa, + nir_def_rewrite_uses(&alu->def, replacement); nir_instr_remove(&alu->instr); return true; @@ -260,7 +260,7 @@ try_opt_exclusive_scan_to_inclusive(nir_intrinsic_instr *intrin) alu->op != nir_op_fmax && alu->op != nir_op_fmin && alu->exact) return false; - if (alu->dest.dest.ssa.num_components != 1) + if (alu->def.num_components != 1) return false; nir_alu_src *alu_src = list_entry(src, nir_alu_src, src); @@ -282,7 +282,7 @@ try_opt_exclusive_scan_to_inclusive(nir_intrinsic_instr *intrin) nir_foreach_use_including_if_safe(src, &intrin->dest.ssa) { /* Remove alu. */ nir_alu_instr *alu = nir_instr_as_alu(src->parent_instr); - nir_def_rewrite_uses(&alu->dest.dest.ssa, &intrin->dest.ssa); + nir_def_rewrite_uses(&alu->def, &intrin->dest.ssa); nir_instr_remove(&alu->instr); } @@ -322,7 +322,7 @@ opt_intrinsics_intrin(nir_builder *b, nir_intrinsic_instr *intrin, if (alu->op == nir_op_ine) new_expr = nir_inot(b, new_expr); - nir_def_rewrite_uses(&alu->dest.dest.ssa, + nir_def_rewrite_uses(&alu->def, new_expr); nir_instr_remove(&alu->instr); progress = true; diff --git a/src/compiler/nir/nir_opt_peephole_select.c b/src/compiler/nir/nir_opt_peephole_select.c index c19bbfe..344d90c 100644 --- a/src/compiler/nir/nir_opt_peephole_select.c +++ b/src/compiler/nir/nir_opt_peephole_select.c @@ -222,7 +222,7 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count, (*count)++; } else { /* The only uses of this definition must be phis in the successor */ - nir_foreach_use_including_if(use, &mov->dest.dest.ssa) { + nir_foreach_use_including_if(use, &mov->def) { if (use->is_if || use->parent_instr->type != nir_instr_type_phi || use->parent_instr->block != block->successors[0]) @@ -457,11 +457,11 @@ nir_opt_peephole_select_block(nir_block *block, nir_shader *shader, nir_src_copy(&sel->src[idx].src, &src->src, &sel->instr); } - nir_def_init(&sel->instr, &sel->dest.dest.ssa, + nir_def_init(&sel->instr, &sel->def, phi->dest.ssa.num_components, phi->dest.ssa.bit_size); nir_def_rewrite_uses(&phi->dest.ssa, - &sel->dest.dest.ssa); + &sel->def); nir_instr_insert_before(&phi->instr, &sel->instr); nir_instr_remove(&phi->instr); diff --git a/src/compiler/nir/nir_opt_phi_precision.c b/src/compiler/nir/nir_opt_phi_precision.c index 0398273..c0d53bb 100644 --- a/src/compiler/nir/nir_opt_phi_precision.c +++ b/src/compiler/nir/nir_opt_phi_precision.c @@ -183,7 +183,7 @@ widening_conversion_op(nir_instr *instr, unsigned *bit_size) /* We also need to check that the conversion's dest was actually * wider: */ - if (alu->dest.dest.ssa.bit_size <= *bit_size) + if (alu->def.bit_size <= *bit_size) return INVALID_OP; return alu->op; @@ -403,7 +403,7 @@ try_move_widening_src(nir_builder *b, nir_phi_instr *phi) /* The conversion we are stripping off could have had a swizzle, * so replace it with a mov if necessary: */ - unsigned num_comp = alu->dest.dest.ssa.num_components; + unsigned num_comp = alu->def.num_components; new_src = nir_mov_alu(b, alu->src[0], num_comp); } diff --git a/src/compiler/nir/nir_opt_reassociate_bfi.c b/src/compiler/nir/nir_opt_reassociate_bfi.c index 29567ed..dabdc04 100644 --- a/src/compiler/nir/nir_opt_reassociate_bfi.c +++ b/src/compiler/nir/nir_opt_reassociate_bfi.c @@ -70,7 +70,7 @@ nir_opt_reassociate_bfi_instr(nir_builder *b, return false; nir_alu_instr *bfiCD0 = nir_instr_as_alu(instr); - if (bfiCD0->op != nir_op_bfi || bfiCD0->dest.dest.ssa.num_components != 1) + if (bfiCD0->op != nir_op_bfi || bfiCD0->def.num_components != 1) return false; /* Enforce the bfi('#c', d, 0) part of the pattern. */ @@ -87,19 +87,19 @@ nir_opt_reassociate_bfi_instr(nir_builder *b, if (!is_used_once(bfiCD0)) return false; - nir_src *use = list_first_entry(&bfiCD0->dest.dest.ssa.uses, + nir_src *use = list_first_entry(&bfiCD0->def.uses, nir_src, use_link); if (use->parent_instr->type != nir_instr_type_alu) return false; nir_alu_instr *bfiABx = nir_instr_as_alu(use->parent_instr); - if (bfiABx->op != nir_op_bfi || bfiABx->dest.dest.ssa.num_components != 1) + if (bfiABx->op != nir_op_bfi || bfiABx->def.num_components != 1) return false; /* Enforce the bfi('#a', b, ...) part of the pattern. */ if (!nir_src_is_const(bfiABx->src[0].src) || - bfiABx->src[2].src.ssa != &bfiCD0->dest.dest.ssa) { + bfiABx->src[2].src.ssa != &bfiCD0->def) { return false; } @@ -127,7 +127,7 @@ nir_opt_reassociate_bfi_instr(nir_builder *b, nir_mov_alu(b, bfiABx->src[0], 1), nir_mov_alu(b, bfiABx->src[1], 1))); - nir_def_rewrite_uses(&bfiABx->dest.dest.ssa, new_bfi); + nir_def_rewrite_uses(&bfiABx->def, new_bfi); return true; } diff --git a/src/compiler/nir/nir_opt_rematerialize_compares.c b/src/compiler/nir/nir_opt_rematerialize_compares.c index 16b3d26..e85591a 100644 --- a/src/compiler/nir/nir_opt_rematerialize_compares.c +++ b/src/compiler/nir/nir_opt_rematerialize_compares.c @@ -60,7 +60,7 @@ is_two_src_comparison(const nir_alu_instr *instr) static bool all_uses_are_bcsel(const nir_alu_instr *instr) { - nir_foreach_use(use, &instr->dest.dest.ssa) { + nir_foreach_use(use, &instr->def) { if (use->parent_instr->type != nir_instr_type_alu) return false; @@ -72,7 +72,7 @@ all_uses_are_bcsel(const nir_alu_instr *instr) /* Not only must the result be used by a bcsel, but it must be used as * the first source (the condition). */ - if (alu->src[0].src.ssa != &instr->dest.dest.ssa) + if (alu->src[0].src.ssa != &instr->def) return false; } @@ -106,7 +106,7 @@ nir_opt_rematerialize_compares_impl(nir_shader *shader, nir_function_impl *impl) * instruction must be duplicated only once in each block because CSE * cannot be run after this pass. */ - nir_foreach_use_including_if_safe(use, &alu->dest.dest.ssa) { + nir_foreach_use_including_if_safe(use, &alu->def) { if (use->is_if) { nir_if *const if_stmt = use->parent_if; @@ -124,7 +124,7 @@ nir_opt_rematerialize_compares_impl(nir_shader *shader, nir_function_impl *impl) nir_instr_insert_after_block(prev_block, &clone->instr); nir_if_rewrite_condition(if_stmt, - nir_src_for_ssa(&clone->dest.dest.ssa)); + nir_src_for_ssa(&clone->def)); progress = true; } else { nir_instr *const use_instr = use->parent_instr; @@ -141,10 +141,10 @@ nir_opt_rematerialize_compares_impl(nir_shader *shader, nir_function_impl *impl) nir_alu_instr *const use_alu = nir_instr_as_alu(use_instr); for (unsigned i = 0; i < nir_op_infos[use_alu->op].num_inputs; i++) { - if (use_alu->src[i].src.ssa == &alu->dest.dest.ssa) { + if (use_alu->src[i].src.ssa == &alu->def) { nir_instr_rewrite_src(&use_alu->instr, &use_alu->src[i].src, - nir_src_for_ssa(&clone->dest.dest.ssa)); + nir_src_for_ssa(&clone->def)); progress = true; } } diff --git a/src/compiler/nir/nir_opt_shrink_vectors.c b/src/compiler/nir/nir_opt_shrink_vectors.c index 17cee53..9b01dd2 100644 --- a/src/compiler/nir/nir_opt_shrink_vectors.c +++ b/src/compiler/nir/nir_opt_shrink_vectors.c @@ -149,7 +149,7 @@ is_only_used_by_alu(nir_def *def) static bool opt_shrink_vector(nir_builder *b, nir_alu_instr *instr) { - nir_def *def = &instr->dest.dest.ssa; + nir_def *def = &instr->def; unsigned mask = nir_def_components_read(def); /* If nothing was read, leave it up to DCE. */ @@ -200,7 +200,7 @@ opt_shrink_vector(nir_builder *b, nir_alu_instr *instr) static bool opt_shrink_vectors_alu(nir_builder *b, nir_alu_instr *instr) { - nir_def *def = &instr->dest.dest.ssa; + nir_def *def = &instr->def; /* Nothing to shrink */ if (def->num_components == 1) @@ -425,7 +425,7 @@ opt_shrink_vectors_phi(nir_builder *b, nir_phi_instr *instr) int src_idx = alu_src - &alu->src[0]; nir_component_mask_t src_read_mask = nir_alu_instr_src_read_mask(alu, src_idx); - nir_def *alu_def = &alu->dest.dest.ssa; + nir_def *alu_def = &alu->def; /* We don't mark the channels used if the only reader is the original phi. * This can happen in the case of loops. diff --git a/src/compiler/nir/nir_opt_undef.c b/src/compiler/nir/nir_opt_undef.c index 35890fe..0430ca7 100644 --- a/src/compiler/nir/nir_opt_undef.c +++ b/src/compiler/nir/nir_opt_undef.c @@ -81,9 +81,9 @@ opt_undef_vecN(nir_builder *b, nir_alu_instr *alu) } b->cursor = nir_before_instr(&alu->instr); - nir_def *undef = nir_undef(b, alu->dest.dest.ssa.num_components, - alu->dest.dest.ssa.bit_size); - nir_def_rewrite_uses(&alu->dest.dest.ssa, undef); + nir_def *undef = nir_undef(b, alu->def.num_components, + alu->def.bit_size); + nir_def_rewrite_uses(&alu->def, undef); return true; } @@ -169,10 +169,10 @@ opt_undef_pack(nir_builder *b, nir_alu_instr *alu) default: return false; } - unsigned num_components = alu->dest.dest.ssa.num_components; + unsigned num_components = alu->def.num_components; b->cursor = nir_before_instr(&alu->instr); nir_def *def = nir_undef(b, num_components, 32); - nir_def_rewrite_uses_after(&alu->dest.dest.ssa, def, &alu->instr); + nir_def_rewrite_uses_after(&alu->def, def, &alu->instr); nir_instr_remove(&alu->instr); return true; } diff --git a/src/compiler/nir/nir_opt_vectorize.c b/src/compiler/nir/nir_opt_vectorize.c index c9aa621..c78a8b2 100644 --- a/src/compiler/nir/nir_opt_vectorize.c +++ b/src/compiler/nir/nir_opt_vectorize.c @@ -70,11 +70,11 @@ hash_instr(const void *data) nir_alu_instr *alu = nir_instr_as_alu(instr); uint32_t hash = HASH(0, alu->op); - hash = HASH(hash, alu->dest.dest.ssa.bit_size); + hash = HASH(hash, alu->def.bit_size); for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) hash = hash_alu_src(hash, &alu->src[i], - alu->dest.dest.ssa.num_components, + alu->def.num_components, instr->pass_flags); return hash; @@ -113,7 +113,7 @@ instrs_equal(const void *data1, const void *data2) if (alu1->op != alu2->op) return false; - if (alu1->dest.dest.ssa.bit_size != alu2->dest.dest.ssa.bit_size) + if (alu1->def.bit_size != alu2->def.bit_size) return false; for (unsigned i = 0; i < nir_op_infos[alu1->op].num_inputs; i++) { @@ -139,7 +139,7 @@ instr_can_rewrite(nir_instr *instr) return false; /* no need to hash instructions which are already vectorized */ - if (alu->dest.dest.ssa.num_components >= instr->pass_flags) + if (alu->def.num_components >= instr->pass_flags) return false; if (nir_op_infos[alu->op].output_size != 0) @@ -152,7 +152,7 @@ instr_can_rewrite(nir_instr *instr) /* don't hash instructions which are already swizzled * outside of max_components: these should better be scalarized */ uint32_t mask = ~(instr->pass_flags - 1); - for (unsigned j = 1; j < alu->dest.dest.ssa.num_components; j++) { + for (unsigned j = 1; j < alu->def.num_components; j++) { if ((alu->src[i].swizzle[0] & mask) != (alu->src[i].swizzle[j] & mask)) return false; } @@ -182,9 +182,9 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2) nir_alu_instr *alu1 = nir_instr_as_alu(instr1); nir_alu_instr *alu2 = nir_instr_as_alu(instr2); - assert(alu1->dest.dest.ssa.bit_size == alu2->dest.dest.ssa.bit_size); - unsigned alu1_components = alu1->dest.dest.ssa.num_components; - unsigned alu2_components = alu2->dest.dest.ssa.num_components; + assert(alu1->def.bit_size == alu2->def.bit_size); + unsigned alu1_components = alu1->def.num_components; + unsigned alu2_components = alu2->def.num_components; unsigned total_components = alu1_components + alu2_components; assert(instr1->pass_flags == instr2->pass_flags); @@ -194,8 +194,8 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2) nir_builder b = nir_builder_at(nir_after_instr(instr1)); nir_alu_instr *new_alu = nir_alu_instr_create(b.shader, alu1->op); - nir_def_init(&new_alu->instr, &new_alu->dest.dest.ssa, total_components, - alu1->dest.dest.ssa.bit_size); + nir_def_init(&new_alu->instr, &new_alu->def, total_components, + alu1->def.bit_size); new_alu->instr.pass_flags = alu1->instr.pass_flags; /* If either channel is exact, we have to preserve it even if it's @@ -243,7 +243,7 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2) nir_builder_instr_insert(&b, &new_alu->instr); /* update all ALU uses */ - nir_foreach_use_safe(src, &alu1->dest.dest.ssa) { + nir_foreach_use_safe(src, &alu1->def) { nir_instr *user_instr = src->parent_instr; if (user_instr->type == nir_instr_type_alu) { /* Check if user is found in the hashset */ @@ -253,7 +253,7 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2) * round-trip through copy propagation. */ nir_instr_rewrite_src(user_instr, src, - nir_src_for_ssa(&new_alu->dest.dest.ssa)); + nir_src_for_ssa(&new_alu->def)); /* Rehash user if it was found in the hashset */ if (entry && entry->key == user_instr) { @@ -263,13 +263,13 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2) } } - nir_foreach_use_safe(src, &alu2->dest.dest.ssa) { + nir_foreach_use_safe(src, &alu2->def) { if (src->parent_instr->type == nir_instr_type_alu) { /* For ALU instructions, rewrite the source directly to avoid a * round-trip through copy propagation. */ nir_instr_rewrite_src(src->parent_instr, src, - nir_src_for_ssa(&new_alu->dest.dest.ssa)); + nir_src_for_ssa(&new_alu->def)); nir_alu_src *alu_src = container_of(src, nir_alu_src, src); nir_alu_instr *use = nir_instr_as_alu(src->parent_instr); @@ -282,20 +282,20 @@ instr_try_combine(struct set *instr_set, nir_instr *instr1, nir_instr *instr2) /* update all other uses if there are any */ unsigned swiz[NIR_MAX_VEC_COMPONENTS]; - if (!nir_def_is_unused(&alu1->dest.dest.ssa)) { + if (!nir_def_is_unused(&alu1->def)) { for (unsigned i = 0; i < alu1_components; i++) swiz[i] = i; - nir_def *new_alu1 = nir_swizzle(&b, &new_alu->dest.dest.ssa, swiz, + nir_def *new_alu1 = nir_swizzle(&b, &new_alu->def, swiz, alu1_components); - nir_def_rewrite_uses(&alu1->dest.dest.ssa, new_alu1); + nir_def_rewrite_uses(&alu1->def, new_alu1); } - if (!nir_def_is_unused(&alu2->dest.dest.ssa)) { + if (!nir_def_is_unused(&alu2->def)) { for (unsigned i = 0; i < alu2_components; i++) swiz[i] = i + alu1_components; - nir_def *new_alu2 = nir_swizzle(&b, &new_alu->dest.dest.ssa, swiz, + nir_def *new_alu2 = nir_swizzle(&b, &new_alu->def, swiz, alu2_components); - nir_def_rewrite_uses(&alu2->dest.dest.ssa, new_alu2); + nir_def_rewrite_uses(&alu2->def, new_alu2); } nir_instr_remove(instr1); diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index 6228a57..aa21342 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -471,7 +471,7 @@ print_alu_instr(nir_alu_instr *instr, print_state *state) { FILE *fp = state->fp; - print_def(&instr->dest.dest.ssa, state); + print_def(&instr->def, state); fprintf(fp, " = %s", nir_op_infos[instr->op].name); if (instr->exact) diff --git a/src/compiler/nir/nir_propagate_invariant.c b/src/compiler/nir/nir_propagate_invariant.c index b59d68c..4b930a9 100644 --- a/src/compiler/nir/nir_propagate_invariant.c +++ b/src/compiler/nir/nir_propagate_invariant.c @@ -81,7 +81,7 @@ propagate_invariant_instr(nir_instr *instr, struct set *invariants) switch (instr->type) { case nir_instr_type_alu: { nir_alu_instr *alu = nir_instr_as_alu(instr); - if (!def_is_invariant(&alu->dest.dest.ssa, invariants)) + if (!def_is_invariant(&alu->def, invariants)) break; alu->exact = true; diff --git a/src/compiler/nir/nir_range_analysis.c b/src/compiler/nir/nir_range_analysis.c index cefdd83..e666e05 100644 --- a/src/compiler/nir/nir_range_analysis.c +++ b/src/compiler/nir/nir_range_analysis.c @@ -2045,7 +2045,7 @@ ssa_def_bits_used(const nir_def *def, int recur) * question can eventually answered after the shader has been * scalarized. */ - if (use_alu->dest.dest.ssa.num_components > 1) + if (use_alu->def.num_components > 1) return all_bits; switch (use_alu->op) { diff --git a/src/compiler/nir/nir_scale_fdiv.c b/src/compiler/nir/nir_scale_fdiv.c index 13c9c80..6a2a1ae 100644 --- a/src/compiler/nir/nir_scale_fdiv.c +++ b/src/compiler/nir/nir_scale_fdiv.c @@ -57,7 +57,7 @@ nir_scale_fdiv_instr(nir_builder *b, nir_instr *instr, UNUSED void *_data) (nir_bcsel(b, small, scaled_up_b, orig_b))); nir_def *new_div = nir_fdiv(b, final_a, final_b); - nir_def_rewrite_uses(&alu->dest.dest.ssa, new_div); + nir_def_rewrite_uses(&alu->def, new_div); return true; } diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index 268e328..bc4bcbd 100644 --- a/src/compiler/nir/nir_search.c +++ b/src/compiler/nir/nir_search.c @@ -374,7 +374,7 @@ match_expression(const nir_algebraic_table *table, const nir_search_expression * return false; if (expr->value.bit_size > 0 && - instr->dest.dest.ssa.bit_size != expr->value.bit_size) + instr->def.bit_size != expr->value.bit_size) return false; state->inexact_match = expr->inexact || state->inexact_match; @@ -451,7 +451,7 @@ construct_value(nir_builder *build, num_components = nir_op_infos[op].output_size; nir_alu_instr *alu = nir_alu_instr_create(build->shader, op); - nir_def_init(&alu->instr, &alu->dest.dest.ssa, num_components, + nir_def_init(&alu->instr, &alu->def, num_components, dst_bit_size); /* We have no way of knowing what values in a given search expression @@ -475,13 +475,13 @@ construct_value(nir_builder *build, nir_builder_instr_insert(build, &alu->instr); - assert(alu->dest.dest.ssa.index == + assert(alu->def.index == util_dynarray_num_elements(state->states, uint16_t)); util_dynarray_append(state->states, uint16_t, 0); nir_algebraic_automaton(&alu->instr, state->states, state->pass_op_table); nir_alu_src val; - val.src = nir_src_for_ssa(&alu->dest.dest.ssa); + val.src = nir_src_for_ssa(&alu->def); memcpy(val.swizzle, identity_swizzle, sizeof val.swizzle); return val; @@ -662,7 +662,7 @@ nir_replace_instr(nir_builder *build, nir_alu_instr *instr, { uint8_t swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 }; - for (unsigned i = 0; i < instr->dest.dest.ssa.num_components; ++i) + for (unsigned i = 0; i < instr->def.num_components; ++i) swizzle[i] = i; struct match_state state; @@ -686,7 +686,7 @@ nir_replace_instr(nir_builder *build, nir_alu_instr *instr, state.variables_seen = 0; if (match_expression(table, search, instr, - instr->dest.dest.ssa.num_components, + instr->def.num_components, swizzle, &state)) { found = true; break; @@ -700,7 +700,7 @@ nir_replace_instr(nir_builder *build, nir_alu_instr *instr, dump_value(&search->value); fprintf(stderr, " -> "); dump_value(replace); - fprintf(stderr, " ssa_%d\n", instr->dest.dest.ssa.index); + fprintf(stderr, " ssa_%d\n", instr->def.index); #endif /* If the instruction at the root of the expression tree being replaced is @@ -742,15 +742,15 @@ nir_replace_instr(nir_builder *build, nir_alu_instr *instr, state.states = states; nir_alu_src val = construct_value(build, replace, - instr->dest.dest.ssa.num_components, - instr->dest.dest.ssa.bit_size, + instr->def.num_components, + instr->def.bit_size, &state, &instr->instr); /* Note that NIR builder will elide the MOV if it's a no-op, which may * allow more work to be done in a single pass through algebraic. */ nir_def *ssa_val = - nir_mov_alu(build, val, instr->dest.dest.ssa.num_components); + nir_mov_alu(build, val, instr->def.num_components); if (ssa_val->index == util_dynarray_num_elements(states, uint16_t)) { util_dynarray_append(states, uint16_t, 0); nir_algebraic_automaton(ssa_val->parent_instr, states, table->pass_op_table); @@ -759,7 +759,7 @@ nir_replace_instr(nir_builder *build, nir_alu_instr *instr, /* Rewrite the uses of the old SSA value to the new one, and recurse * through the uses updating the automaton's state. */ - nir_def_rewrite_uses(&instr->dest.dest.ssa, ssa_val); + nir_def_rewrite_uses(&instr->def, ssa_val); nir_algebraic_update_automaton(ssa_val->parent_instr, algebraic_worklist, states, table->pass_op_table); @@ -802,7 +802,7 @@ nir_algebraic_automaton(nir_instr *instr, struct util_dynarray *states, } uint16_t *state = util_dynarray_element(states, uint16_t, - alu->dest.dest.ssa.index); + alu->def.index); if (*state != tbl->table[index]) { *state = tbl->table[index]; return true; @@ -841,7 +841,7 @@ nir_algebraic_instr(nir_builder *build, nir_instr *instr, nir_alu_instr *alu = nir_instr_as_alu(instr); - unsigned bit_size = alu->dest.dest.ssa.bit_size; + unsigned bit_size = alu->def.bit_size; const unsigned execution_mode = build->shader->info.float_controls_execution_mode; const bool ignore_inexact = @@ -849,7 +849,7 @@ nir_algebraic_instr(nir_builder *build, nir_instr *instr, nir_is_denorm_flush_to_zero(execution_mode, bit_size); int xform_idx = *util_dynarray_element(states, uint16_t, - alu->dest.dest.ssa.index); + alu->def.index); for (const struct transform *xform = &table->transforms[table->transform_offsets[xform_idx]]; xform->condition_offset != ~0; xform++) { diff --git a/src/compiler/nir/nir_search_helpers.h b/src/compiler/nir/nir_search_helpers.h index 03439a0..32c1f88 100644 --- a/src/compiler/nir/nir_search_helpers.h +++ b/src/compiler/nir/nir_search_helpers.h @@ -402,13 +402,13 @@ is_not_const_and_not_fsign(struct hash_table *ht, const nir_alu_instr *instr, static inline bool is_used_once(const nir_alu_instr *instr) { - return list_is_singular(&instr->dest.dest.ssa.uses); + return list_is_singular(&instr->def.uses); } static inline bool is_used_by_if(const nir_alu_instr *instr) { - return nir_def_used_by_if(&instr->dest.dest.ssa); + return nir_def_used_by_if(&instr->def); } static inline bool @@ -420,7 +420,7 @@ is_not_used_by_if(const nir_alu_instr *instr) static inline bool is_used_by_non_fsat(const nir_alu_instr *instr) { - nir_foreach_use(src, &instr->dest.dest.ssa) { + nir_foreach_use(src, &instr->def) { const nir_instr *const user_instr = src->parent_instr; if (user_instr->type != nir_instr_type_alu) @@ -439,7 +439,7 @@ is_used_by_non_fsat(const nir_alu_instr *instr) static inline bool is_only_used_as_float(const nir_alu_instr *instr) { - nir_foreach_use(src, &instr->dest.dest.ssa) { + nir_foreach_use(src, &instr->def) { const nir_instr *const user_instr = src->parent_instr; if (user_instr->type != nir_instr_type_alu) return false; @@ -459,7 +459,7 @@ is_only_used_as_float(const nir_alu_instr *instr) static inline bool is_only_used_by_fadd(const nir_alu_instr *instr) { - nir_foreach_use(src, &instr->dest.dest.ssa) { + nir_foreach_use(src, &instr->def) { const nir_instr *const user_instr = src->parent_instr; if (user_instr->type != nir_instr_type_alu) return false; @@ -481,13 +481,13 @@ is_only_used_by_fadd(const nir_alu_instr *instr) static inline bool only_lower_8_bits_used(const nir_alu_instr *instr) { - return (nir_def_bits_used(&instr->dest.dest.ssa) & ~0xffull) == 0; + return (nir_def_bits_used(&instr->def) & ~0xffull) == 0; } static inline bool only_lower_16_bits_used(const nir_alu_instr *instr) { - return (nir_def_bits_used(&instr->dest.dest.ssa) & ~0xffffull) == 0; + return (nir_def_bits_used(&instr->def) & ~0xffffull) == 0; } /** diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c index e0340df..b3c74fe 100644 --- a/src/compiler/nir/nir_serialize.c +++ b/src/compiler/nir/nir_serialize.c @@ -737,7 +737,7 @@ write_alu(write_ctx *ctx, const nir_alu_instr *alu) header.alu.writemask_or_two_swizzles |= alu->src[1].swizzle[0] << 2; } - write_def(ctx, &alu->dest.dest.ssa, header, alu->instr.type); + write_def(ctx, &alu->def, header, alu->instr.type); if (header.alu.packed_src_ssa_16bit) { for (unsigned i = 0; i < num_srcs; i++) { @@ -788,7 +788,7 @@ read_alu(read_ctx *ctx, union packed_instr header) alu->no_signed_wrap = header.alu.no_signed_wrap; alu->no_unsigned_wrap = header.alu.no_unsigned_wrap; - read_def(ctx, &alu->dest.dest.ssa, &alu->instr, header); + read_def(ctx, &alu->def, &alu->instr, header); if (header.alu.packed_src_ssa_16bit) { for (unsigned i = 0; i < num_srcs; i++) { diff --git a/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c b/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c index 34c5d01..0771559 100644 --- a/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c +++ b/src/compiler/nir/nir_split_64bit_vec3_and_vec4.c @@ -225,7 +225,7 @@ split_phi(nir_builder *b, nir_phi_instr *phi) nir_op vec_op = nir_op_vec(phi->dest.ssa.num_components); nir_alu_instr *vec = nir_alu_instr_create(b->shader, vec_op); - nir_def_init(&vec->instr, &vec->dest.dest.ssa, + nir_def_init(&vec->instr, &vec->def, phi->dest.ssa.num_components, 64); int num_comp[2] = { 2, phi->dest.ssa.num_components - 2 }; diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c index 9c2e06f..b400632 100644 --- a/src/compiler/nir/nir_validate.c +++ b/src/compiler/nir/nir_validate.c @@ -248,7 +248,7 @@ validate_alu_instr(nir_alu_instr *instr, validate_state *state) } nir_alu_type dest_type = nir_op_infos[instr->op].output_type; - unsigned dest_bit_size = instr->dest.dest.ssa.bit_size; + unsigned dest_bit_size = instr->def.bit_size; if (nir_alu_type_get_type_size(dest_type)) { validate_assert(state, dest_bit_size == nir_alu_type_get_type_size(dest_type)); } else if (instr_bit_size) { @@ -263,7 +263,7 @@ validate_alu_instr(nir_alu_instr *instr, validate_state *state) dest_bit_size == 64); } - validate_def(&instr->dest.dest.ssa, state, 0, 0); + validate_def(&instr->def, state, 0, 0); } static void diff --git a/src/compiler/nir/tests/comparison_pre_tests.cpp b/src/compiler/nir/tests/comparison_pre_tests.cpp index 4f19db0..78e08d2 100644 --- a/src/compiler/nir/tests/comparison_pre_tests.cpp +++ b/src/compiler/nir/tests/comparison_pre_tests.cpp @@ -504,9 +504,9 @@ TEST_F(comparison_pre_test, swizzle_of_same_immediate_vector) nir_builder_alu_instr_finish_and_insert(&bld, flt); - flt->dest.dest.ssa.num_components = 1; + flt->def.num_components = 1; - nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa); + nir_if *nif = nir_push_if(&bld, &flt->def); nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd); @@ -518,7 +518,7 @@ TEST_F(comparison_pre_test, swizzle_of_same_immediate_vector) nir_builder_alu_instr_finish_and_insert(&bld, fadd); - fadd->dest.dest.ssa.num_components = 1; + fadd->def.num_components = 1; nir_pop_if(&bld, nif); @@ -559,9 +559,9 @@ TEST_F(comparison_pre_test, non_scalar_add_result) nir_builder_alu_instr_finish_and_insert(&bld, flt); - flt->dest.dest.ssa.num_components = 1; + flt->def.num_components = 1; - nir_if *nif = nir_push_if(&bld, &flt->dest.dest.ssa); + nir_if *nif = nir_push_if(&bld, &flt->def); nir_alu_instr *fadd = nir_alu_instr_create(bld.shader, nir_op_fadd); @@ -573,7 +573,7 @@ TEST_F(comparison_pre_test, non_scalar_add_result) nir_builder_alu_instr_finish_and_insert(&bld, fadd); - fadd->dest.dest.ssa.num_components = 2; + fadd->def.num_components = 2; nir_pop_if(&bld, nif); diff --git a/src/compiler/nir/tests/mod_analysis_tests.cpp b/src/compiler/nir/tests/mod_analysis_tests.cpp index d4523ab..ba95a74 100644 --- a/src/compiler/nir/tests/mod_analysis_tests.cpp +++ b/src/compiler/nir/tests/mod_analysis_tests.cpp @@ -58,10 +58,10 @@ nir_mod_analysis_test::nir_imul_vec2y(nir_builder *b, nir_def *src0, nir_def *sr instr->src[1].src = nir_src_for_ssa(src1); instr->src[1].swizzle[0] = 1; - nir_def_init(&instr->instr, &instr->dest.dest.ssa, 1, 32); + nir_def_init(&instr->instr, &instr->def, 1, 32); nir_builder_instr_insert(b, &instr->instr); - return &instr->dest.dest.ssa; + return &instr->def; } TEST_F(nir_mod_analysis_test, const_val) diff --git a/src/compiler/nir/tests/range_analysis_tests.cpp b/src/compiler/nir/tests/range_analysis_tests.cpp index 97063b3..fbf419a 100644 --- a/src/compiler/nir/tests/range_analysis_tests.cpp +++ b/src/compiler/nir/tests/range_analysis_tests.cpp @@ -61,7 +61,7 @@ ssa_def_bits_used_test::build_alu_instr(nir_op op, if (alu == NULL) return NULL; - alu->dest.dest.ssa.num_components = 1; + alu->def.num_components = 1; return alu; } diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 5163d45..bc06999 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -4066,7 +4066,7 @@ create_vec(struct vtn_builder *b, unsigned num_components, unsigned bit_size) { nir_op op = nir_op_vec(num_components); nir_alu_instr *vec = nir_alu_instr_create(b->shader, op); - nir_def_init(&vec->instr, &vec->dest.dest.ssa, num_components, bit_size); + nir_def_init(&vec->instr, &vec->def, num_components, bit_size); return vec; } @@ -4126,7 +4126,7 @@ vtn_vector_shuffle(struct vtn_builder *b, unsigned num_components, nir_builder_instr_insert(&b->nb, &vec->instr); - return &vec->dest.dest.ssa; + return &vec->def; } /* @@ -4165,7 +4165,7 @@ vtn_vector_construct(struct vtn_builder *b, unsigned num_components, nir_builder_instr_insert(&b->nb, &vec->instr); - return &vec->dest.dest.ssa; + return &vec->def; } static struct vtn_ssa_value * diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 453d5d1..395e268 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -378,12 +378,12 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) unsigned bs[info->num_inputs]; /* bit size */ struct ir3_block *b = ctx->block; unsigned dst_sz, wrmask; - type_t dst_type = type_uint_size(alu->dest.dest.ssa.bit_size); + type_t dst_type = type_uint_size(alu->def.bit_size); - dst_sz = alu->dest.dest.ssa.num_components; + dst_sz = alu->def.num_components; wrmask = (1 << dst_sz) - 1; - dst = ir3_get_def(ctx, &alu->dest.dest.ssa, dst_sz); + dst = ir3_get_def(ctx, &alu->def, dst_sz); /* Vectors are special in that they have non-scalarized writemasks, * and just take the first swizzle channel for each argument in @@ -402,7 +402,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[i] = ir3_MOV(b, src[i], dst_type); } - ir3_put_def(ctx, &alu->dest.dest.ssa); + ir3_put_def(ctx, &alu->def); return; } @@ -421,12 +421,12 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) } } - ir3_put_def(ctx, &alu->dest.dest.ssa); + ir3_put_def(ctx, &alu->def); return; } /* General case: We can just grab the one used channel per src. */ - assert(alu->dest.dest.ssa.num_components == 1); + assert(alu->def.num_components == 1); for (int i = 0; i < info->num_inputs; i++) { nir_alu_src *asrc = &alu->src[i]; @@ -645,7 +645,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0); break; case nir_op_imul: - compile_assert(ctx, alu->dest.dest.ssa.bit_size == 16); + compile_assert(ctx, alu->def.bit_size == 16); dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0); break; case nir_op_imul24: @@ -843,7 +843,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) } if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) { - assert(alu->dest.dest.ssa.bit_size == 1 || alu->op == nir_op_b2b32); + assert(alu->def.bit_size == 1 || alu->op == nir_op_b2b32); assert(dst_sz == 1); } else { /* 1-bit values stored in 32-bit registers are only valid for certain @@ -857,11 +857,11 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) case nir_op_bcsel: break; default: - compile_assert(ctx, alu->dest.dest.ssa.bit_size != 1); + compile_assert(ctx, alu->def.bit_size != 1); } } - ir3_put_def(ctx, &alu->dest.dest.ssa); + ir3_put_def(ctx, &alu->def); } static void diff --git a/src/freedreno/ir3/ir3_nir_opt_preamble.c b/src/freedreno/ir3/ir3_nir_opt_preamble.c index a26568f..ff9a5a0 100644 --- a/src/freedreno/ir3/ir3_nir_opt_preamble.c +++ b/src/freedreno/ir3/ir3_nir_opt_preamble.c @@ -123,7 +123,7 @@ instr_cost(nir_instr *instr, const void *data) switch (instr->type) { case nir_instr_type_alu: { nir_alu_instr *alu = nir_instr_as_alu(instr); - unsigned components = alu->dest.dest.ssa.num_components; + unsigned components = alu->def.num_components; switch (alu->op) { /* cat4 */ case nir_op_frcp: @@ -145,13 +145,13 @@ instr_cost(nir_instr *instr, const void *data) case nir_op_f2f16: case nir_op_f2fmp: case nir_op_fneg: - return all_uses_float(&alu->dest.dest.ssa, true) ? 0 : 1 * components; + return all_uses_float(&alu->def, true) ? 0 : 1 * components; case nir_op_fabs: - return all_uses_float(&alu->dest.dest.ssa, false) ? 0 : 1 * components; + return all_uses_float(&alu->def, false) ? 0 : 1 * components; case nir_op_inot: - return all_uses_bit(&alu->dest.dest.ssa) ? 0 : 1 * components; + return all_uses_bit(&alu->def) ? 0 : 1 * components; /* Instructions that become vector split/collect */ case nir_op_vec2: diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c b/src/gallium/auxiliary/gallivm/lp_bld_nir.c index 0f78664..a088d53 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c +++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c @@ -1116,7 +1116,7 @@ visit_alu(struct lp_build_nir_context *bld_base, struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef src[NIR_MAX_VEC_COMPONENTS]; unsigned src_bit_size[NIR_MAX_VEC_COMPONENTS]; - const unsigned num_components = instr->dest.dest.ssa.num_components; + const unsigned num_components = instr->def.num_components; unsigned src_components; switch (instr->op) { @@ -1197,10 +1197,10 @@ visit_alu(struct lp_build_nir_context *bld_base, result[c] = do_alu_action(bld_base, instr, src_bit_size, src_chan); result[c] = cast_type(bld_base, result[c], nir_op_infos[instr->op].output_type, - instr->dest.dest.ssa.bit_size); + instr->def.bit_size); } } - assign_ssa_dest(bld_base, &instr->dest.dest.ssa, result); + assign_ssa_dest(bld_base, &instr->def, result); } diff --git a/src/gallium/auxiliary/nir/nir_to_tgsi.c b/src/gallium/auxiliary/nir/nir_to_tgsi.c index b194f57..f042968 100644 --- a/src/gallium/auxiliary/nir/nir_to_tgsi.c +++ b/src/gallium/auxiliary/nir/nir_to_tgsi.c @@ -1271,7 +1271,7 @@ ntt_get_alu_src(struct ntt_compile *c, nir_alu_instr *instr, int i) !(src.src.is_ssa && src.src.ssa->parent_instr->type == nir_instr_type_ssa_undef)) { int chan1 = 1; if (nir_op_infos[instr->op].input_sizes[i] == 0) { - chan1 = instr->dest.dest.ssa.num_components > 1 ? 1 : 0; + chan1 = instr->def.num_components > 1 ? 1 : 0; } usrc = ureg_swizzle(usrc, src.swizzle[0] * 2, @@ -1442,7 +1442,7 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr *instr) struct ureg_src src[4]; struct ureg_dst dst; unsigned i; - int dst_64 = instr->dest.dest.ssa.bit_size == 64; + int dst_64 = instr->def.bit_size == 64; int src_64 = nir_src_bit_size(instr->src[0].src) == 64; int num_srcs = nir_op_infos[instr->op].num_inputs; @@ -1458,7 +1458,7 @@ ntt_emit_alu(struct ntt_compile *c, nir_alu_instr *instr) for (; i < ARRAY_SIZE(src); i++) src[i] = ureg_src_undef(); - dst = ntt_get_alu_dest(c, &instr->dest.dest.ssa); + dst = ntt_get_alu_dest(c, &instr->def); static enum tgsi_opcode op_map[][2] = { [nir_op_mov] = { TGSI_OPCODE_MOV, TGSI_OPCODE_MOV }, @@ -3226,7 +3226,7 @@ ntt_should_vectorize_instr(const nir_instr *instr, const void *data) } int src_bit_size = nir_src_bit_size(alu->src[0].src); - int dst_bit_size = alu->dest.dest.ssa.bit_size; + int dst_bit_size = alu->def.bit_size; if (src_bit_size == 64 || dst_bit_size == 64) { /* Avoid vectorizing 64-bit instructions at all. Despite tgsi.rst @@ -3366,7 +3366,7 @@ scalarize_64bit(const nir_instr *instr, const void *data) { const nir_alu_instr *alu = nir_instr_as_alu(instr); - return (alu->dest.dest.ssa.bit_size == 64 || + return (alu->def.bit_size == 64 || nir_src_bit_size(alu->src[0].src) == 64); } @@ -3824,7 +3824,7 @@ ntt_vec_to_mov_writemask_cb(const nir_instr *instr, unsigned writemask, UNUSED c return false; nir_alu_instr *alu = nir_instr_as_alu(instr); - int dst_32 = alu->dest.dest.ssa.bit_size == 32; + int dst_32 = alu->def.bit_size == 32; int src_64 = nir_src_bit_size(alu->src[0].src) == 64; if (src_64 && dst_32) { diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c index d1b9d90..09e04c8 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c @@ -415,7 +415,7 @@ get_src(struct etna_compile *c, nir_src *src) static bool vec_dest_has_swizzle(nir_alu_instr *vec, nir_def *ssa) { - for (unsigned i = 0; i < vec->dest.dest.ssa.num_components; i++) { + for (unsigned i = 0; i < vec->def.num_components; i++) { if (vec->src[i].src.ssa != ssa) continue; @@ -477,7 +477,7 @@ emit_alu(struct etna_compile *c, nir_alu_instr * alu) assert(!(alu->op >= nir_op_vec2 && alu->op <= nir_op_vec4)); unsigned dst_swiz; - hw_dst dst = ra_def(c, &alu->dest.dest.ssa, &dst_swiz); + hw_dst dst = ra_def(c, &alu->def, &dst_swiz); switch (alu->op) { case nir_op_fdot2: @@ -718,7 +718,7 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader) unsigned num_components = 1; - for (unsigned i = start_idx + 1; i < vec->dest.dest.ssa.num_components; i++) { + for (unsigned i = start_idx + 1; i < vec->def.num_components; i++) { if (nir_srcs_equal(vec->src[i].src, vec->src[start_idx].src) && is_src_mod_neg(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx) && is_src_mod_abs(&vec->instr, i) == is_src_mod_neg(&vec->instr, start_idx)) { @@ -728,14 +728,14 @@ insert_vec_mov(nir_alu_instr *vec, unsigned start_idx, nir_shader *shader) } } - nir_def_init(&mov->instr, &mov->dest.dest.ssa, num_components, 32); + nir_def_init(&mov->instr, &mov->def, num_components, 32); /* replace vec srcs with inserted mov */ for (unsigned i = 0, j = 0; i < 4; i++) { if (!(write_mask & (1 << i))) continue; - nir_instr_rewrite_src(&vec->instr, &vec->src[i].src, nir_src_for_ssa(&mov->dest.dest.ssa)); + nir_instr_rewrite_src(&vec->instr, &vec->src[i].src, nir_src_for_ssa(&mov->def)); vec->src[i].swizzle[0] = j++; } @@ -762,7 +762,7 @@ static nir_const_value *get_alu_cv(nir_alu_src *src) if (cv) { /* Validate that we are only using ETNA_UNIFORM_CONSTANT const_values. */ - for (unsigned i = 0; i < parent->dest.dest.ssa.num_components; i++) { + for (unsigned i = 0; i < parent->def.num_components; i++) { if (cv[i].u64 >> 32 != ETNA_UNIFORM_CONSTANT) { cv = NULL; break; @@ -809,7 +809,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu) if (!cv) continue; - unsigned num_components = info->input_sizes[i] ?: alu->dest.dest.ssa.num_components; + unsigned num_components = info->input_sizes[i] ?: alu->def.num_components; for (unsigned j = 0; j < num_components; j++) { int idx = const_add(&value[0].u64, cv[alu->src[i].swizzle[j]].u64); swizzle[i][j] = idx; @@ -878,7 +878,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu) nir_def *def = nir_build_imm(&b, num_components, 32, value); if (num_components == info->num_inputs) { - nir_def_rewrite_uses(&alu->dest.dest.ssa, def); + nir_def_rewrite_uses(&alu->def, def); nir_instr_remove(&alu->instr); return; } @@ -894,7 +894,7 @@ lower_alu(struct etna_compile *c, nir_alu_instr *alu) } unsigned finished_write_mask = 0; - for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; i++) { + for (unsigned i = 0; i < alu->def.num_components; i++) { nir_def *ssa = alu->src[i].src.ssa; /* check that vecN instruction is only user of this */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.h b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.h index 84615ad..2670c2e 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.h +++ b/src/gallium/drivers/etnaviv/etnaviv_compiler_nir.h @@ -262,7 +262,7 @@ real_def(nir_def *def, unsigned *swiz, unsigned *mask) assert(!(instr->pass_flags & BYPASS_SRC)); instr->pass_flags |= BYPASS_DST; - return real_def(&alu->dest.dest.ssa, swiz, mask); + return real_def(&alu->def, swiz, mask); } if (can_bypass_src && !(p_instr->pass_flags & BYPASS_DST)) { @@ -281,7 +281,7 @@ def_for_instr(nir_instr *instr) switch (instr->type) { case nir_instr_type_alu: - def = &nir_instr_as_alu(instr)->dest.dest.ssa; + def = &nir_instr_as_alu(instr)->def; break; case nir_instr_type_tex: def = &nir_instr_as_tex(instr)->dest.ssa; diff --git a/src/gallium/drivers/etnaviv/etnaviv_nir.c b/src/gallium/drivers/etnaviv/etnaviv_nir.c index d5e7833..6d2e76a 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_nir.c +++ b/src/gallium/drivers/etnaviv/etnaviv_nir.c @@ -132,10 +132,10 @@ etna_lower_io(nir_shader *shader, struct etna_shader_variant *v) for (unsigned i = tex->coord_components; i < 4; i++) vec->src[i].src = nir_src_for_ssa(src1->ssa); - nir_def_init(&vec->instr, &vec->dest.dest.ssa, 4, 32); + nir_def_init(&vec->instr, &vec->def, 4, 32); nir_tex_instr_remove_src(tex, src1_idx); - nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(&vec->dest.dest.ssa)); + nir_instr_rewrite_src(&tex->instr, coord, nir_src_for_ssa(&vec->def)); tex->coord_components = 4; nir_instr_insert_before(&tex->instr, &vec->instr); @@ -178,7 +178,7 @@ etna_lower_alu_impl(nir_function_impl *impl, bool has_new_transcendentals) if (has_new_transcendentals && ( alu->op == nir_op_fdiv || alu->op == nir_op_flog2 || alu->op == nir_op_fsin || alu->op == nir_op_fcos)) { - nir_def *ssa = &alu->dest.dest.ssa; + nir_def *ssa = &alu->def; assert(ssa->num_components == 1); @@ -186,14 +186,14 @@ etna_lower_alu_impl(nir_function_impl *impl, bool has_new_transcendentals) mul->src[0].src = mul->src[1].src = nir_src_for_ssa(ssa); mul->src[1].swizzle[0] = 1; - nir_def_init(&mul->instr, &mul->dest.dest.ssa, 1, 32); + nir_def_init(&mul->instr, &mul->def, 1, 32); alu->src[0].swizzle[1] = 0; ssa->num_components = 2; nir_instr_insert_after(instr, &mul->instr); - nir_def_rewrite_uses_after(ssa, &mul->dest.dest.ssa, + nir_def_rewrite_uses_after(ssa, &mul->def, &mul->instr); } } diff --git a/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c b/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c index 1bdae32..570be29 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c +++ b/src/gallium/drivers/etnaviv/etnaviv_nir_lower_source_mods.c @@ -96,7 +96,7 @@ nir_lower_to_source_mods_instr(nir_builder *b, nir_instr *instr, alu->src[i].swizzle[j] = parent->src[0].swizzle[alu->src[i].swizzle[j]]; } - if (nir_def_is_unused(&parent->dest.dest.ssa)) + if (nir_def_is_unused(&parent->def)) nir_instr_remove(&parent->instr); progress = true; diff --git a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c index 614da47..976f39d 100644 --- a/src/gallium/drivers/freedreno/a2xx/ir2_nir.c +++ b/src/gallium/drivers/freedreno/a2xx/ir2_nir.c @@ -419,7 +419,7 @@ static void emit_alu(struct ir2_context *ctx, nir_alu_instr *alu) { const nir_op_info *info = &nir_op_infos[alu->op]; - nir_def *def = &alu->dest.dest.ssa; + nir_def *def = &alu->def; struct ir2_instr *instr; struct ir2_src tmp; unsigned ncomp; @@ -438,7 +438,7 @@ emit_alu(struct ir2_context *ctx, nir_alu_instr *alu) instr = instr_create_alu(ctx, alu->op, ncomp); nir_legacy_alu_dest legacy_dest = - nir_legacy_chase_alu_dest(&alu->dest.dest.ssa); + nir_legacy_chase_alu_dest(&alu->def); set_legacy_index(ctx, legacy_dest.dest, instr); instr->alu.saturate = legacy_dest.fsat; instr->alu.write_mask = legacy_dest.write_mask; diff --git a/src/gallium/drivers/lima/ir/gp/nir.c b/src/gallium/drivers/lima/ir/gp/nir.c index cdbead4..3ea8904 100644 --- a/src/gallium/drivers/lima/ir/gp/nir.c +++ b/src/gallium/drivers/lima/ir/gp/nir.c @@ -153,7 +153,7 @@ static bool gpir_emit_alu(gpir_block *block, nir_instr *ni) if (instr->op == nir_op_mov) { gpir_node *child = gpir_node_find(block, &instr->src[0].src, instr->src[0].swizzle[0]); - register_node_ssa(block, child, &instr->dest.dest.ssa); + register_node_ssa(block, child, &instr->def); return true; } @@ -182,7 +182,7 @@ static bool gpir_emit_alu(gpir_block *block, nir_instr *ni) } list_addtail(&node->node.list, &block->node_list); - register_node_ssa(block, &node->node, &instr->dest.dest.ssa); + register_node_ssa(block, &node->node, &instr->def); return true; } diff --git a/src/gallium/drivers/lima/ir/lima_nir_split_load_input.c b/src/gallium/drivers/lima/ir/lima_nir_split_load_input.c index 7b19730..c0bb785 100644 --- a/src/gallium/drivers/lima/ir/lima_nir_split_load_input.c +++ b/src/gallium/drivers/lima/ir/lima_nir_split_load_input.c @@ -49,19 +49,19 @@ lima_nir_split_load_input_instr(nir_builder *b, uint8_t swizzle = alu->src[0].swizzle[0]; int i; - for (i = 1; i < alu->dest.dest.ssa.num_components; i++) + for (i = 1; i < alu->def.num_components; i++) if (alu->src[0].swizzle[i] != (swizzle + i)) break; - if (i != alu->dest.dest.ssa.num_components) + if (i != alu->def.num_components) return false; /* mali4xx can't access unaligned vec3, don't split load input */ - if (alu->dest.dest.ssa.num_components == 3 && swizzle > 0) + if (alu->def.num_components == 3 && swizzle > 0) return false; /* mali4xx can't access unaligned vec2, don't split load input */ - if (alu->dest.dest.ssa.num_components == 2 && + if (alu->def.num_components == 2 && swizzle != 0 && swizzle != 2) return false; @@ -70,8 +70,8 @@ lima_nir_split_load_input_instr(nir_builder *b, b->shader, intrin->intrinsic); nir_def_init(&new_intrin->instr, &new_intrin->dest.ssa, - alu->dest.dest.ssa.num_components, ssa->bit_size); - new_intrin->num_components = alu->dest.dest.ssa.num_components; + alu->def.num_components, ssa->bit_size); + new_intrin->num_components = alu->def.num_components; nir_intrinsic_set_base(new_intrin, nir_intrinsic_base(intrin)); nir_intrinsic_set_component(new_intrin, nir_intrinsic_component(intrin) + swizzle); nir_intrinsic_set_dest_type(new_intrin, nir_intrinsic_dest_type(intrin)); @@ -80,7 +80,7 @@ lima_nir_split_load_input_instr(nir_builder *b, nir_src_copy(&new_intrin->src[0], &intrin->src[0], &new_intrin->instr); nir_builder_instr_insert(b, &new_intrin->instr); - nir_def_rewrite_uses(&alu->dest.dest.ssa, + nir_def_rewrite_uses(&alu->def, &new_intrin->dest.ssa); nir_instr_remove(&alu->instr); return true; diff --git a/src/gallium/drivers/lima/ir/pp/nir.c b/src/gallium/drivers/lima/ir/pp/nir.c index 384f344..f7f7a69 100644 --- a/src/gallium/drivers/lima/ir/pp/nir.c +++ b/src/gallium/drivers/lima/ir/pp/nir.c @@ -159,7 +159,7 @@ static int nir_to_ppir_opcodes[nir_num_opcodes] = { static bool ppir_emit_alu(ppir_block *block, nir_instr *ni) { nir_alu_instr *instr = nir_instr_as_alu(ni); - nir_def *def = &instr->dest.dest.ssa; + nir_def *def = &instr->def; int op = nir_to_ppir_opcodes[instr->op]; if (op == ppir_op_unsupported) { diff --git a/src/gallium/drivers/lima/lima_program.c b/src/gallium/drivers/lima/lima_program.c index 41abce6..7e1d539 100644 --- a/src/gallium/drivers/lima/lima_program.c +++ b/src/gallium/drivers/lima/lima_program.c @@ -196,7 +196,7 @@ lima_alu_to_scalar_filter_cb(const nir_instr *instr, const void *data) return false; } - int num_components = alu->dest.dest.ssa.num_components; + int num_components = alu->def.num_components; uint8_t swizzle = alu->src[0].swizzle[0]; diff --git a/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp b/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp index e0be844..0b53852 100644 --- a/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_instr_alu.cpp @@ -1903,7 +1903,7 @@ AluInstr::from_nir(nir_alu_instr *alu, Shader& shader) static Pin pin_for_components(const nir_alu_instr& alu) { - return alu.dest.dest.ssa.num_components == 1 ? pin_free : pin_none; + return alu.def.num_components == 1 ? pin_free : pin_none; } static bool @@ -1924,15 +1924,15 @@ emit_alu_op1_64bit(const nir_alu_instr& alu, swz[1] = 0; } - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_chan), + value_factory.dest(alu.def, 2 * i, pin_chan), value_factory.src64(alu.src[0], i, swz[0]), {alu_write}); group->add_instruction(ir); ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, 2 * i + 1, pin_chan), + value_factory.dest(alu.def, 2 * i + 1, pin_chan), value_factory.src64(alu.src[0], i, swz[1]), {alu_write}); group->add_instruction(ir); @@ -1950,10 +1950,10 @@ emit_alu_mov_64bit(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { for (unsigned c = 0; c < 2; ++c) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_free), + value_factory.dest(alu.def, 2 * i + c, pin_free), value_factory.src64(alu.src[0], i, c), {alu_write}); shader.emit_instruction(ir); @@ -1971,10 +1971,10 @@ emit_alu_neg(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { for (unsigned c = 0; c < 2; ++c) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 2 * i + c, pin_chan), + value_factory.dest(alu.def, 2 * i + c, pin_chan), value_factory.src64(alu.src[0], i, c), {alu_write}); shader.emit_instruction(ir); @@ -1992,15 +1992,15 @@ emit_alu_abs64(const nir_alu_instr& alu, Shader& shader) { auto& value_factory = shader.value_factory(); - assert(alu.dest.dest.ssa.num_components == 1); + assert(alu.def.num_components == 1); shader.emit_instruction(new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 0, pin_chan), + value_factory.dest(alu.def, 0, pin_chan), value_factory.src64(alu.src[0], 0, 0), AluInstr::write)); auto ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 1, pin_chan), + value_factory.dest(alu.def, 1, pin_chan), value_factory.src64(alu.src[0], 0, 1), AluInstr::last_write); ir->set_source_mod(0, AluInstr::mod_abs); @@ -2044,17 +2044,17 @@ emit_alu_fsat64(const nir_alu_instr& alu, Shader& shader) { auto& value_factory = shader.value_factory(); - assert(alu.dest.dest.ssa.num_components == 1); + assert(alu.def.num_components == 1); if (try_propagat_fsat64(alu, shader)) { auto ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 0, pin_chan), + value_factory.dest(alu.def, 0, pin_chan), value_factory.src64(alu.src[0], 0, 0), AluInstr::write); shader.emit_instruction(ir); shader.emit_instruction(new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 1, pin_chan), + value_factory.dest(alu.def, 1, pin_chan), value_factory.src64(alu.src[0], 0, 1), AluInstr::last_write)); } else { @@ -2064,7 +2064,7 @@ emit_alu_fsat64(const nir_alu_instr& alu, Shader& shader) auto group = new AluGroup(); auto ir = new AluInstr(op2_add_64, - value_factory.dest(alu.dest.dest.ssa, 0, pin_chan), + value_factory.dest(alu.def, 0, pin_chan), value_factory.src64(alu.src[0], 0, 1), value_factory.literal(0), AluInstr::write); @@ -2072,7 +2072,7 @@ emit_alu_fsat64(const nir_alu_instr& alu, Shader& shader) group->add_instruction(ir); group->add_instruction(new AluInstr(op2_add_64, - value_factory.dest(alu.dest.dest.ssa, 1, pin_chan), + value_factory.dest(alu.def, 1, pin_chan), value_factory.src64(alu.src[0], 0, 0), value_factory.literal(0), AluInstr::last_write)); @@ -2100,12 +2100,12 @@ emit_alu_op2_64bit(const nir_alu_instr& alu, int num_emit0 = opcode == op2_mul_64 ? 3 : 1; - assert(num_emit0 == 1 || alu.dest.dest.ssa.num_components == 1); + assert(num_emit0 == 1 || alu.def.num_components == 1); - for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) { + for (unsigned k = 0; k < alu.def.num_components; ++k) { int i = 0; for (; i < num_emit0; ++i) { - auto dest = i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) + auto dest = i < 2 ? value_factory.dest(alu.def, i, pin_chan) : value_factory.dummy_dest(i); ir = new AluInstr(opcode, @@ -2117,7 +2117,7 @@ emit_alu_op2_64bit(const nir_alu_instr& alu, } auto dest = - i == 1 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) : value_factory.dummy_dest(i); + i == 1 ? value_factory.dest(alu.def, i, pin_chan) : value_factory.dummy_dest(i); ir = new AluInstr(opcode, dest, @@ -2149,8 +2149,8 @@ emit_alu_op2_64bit_one_dst(const nir_alu_instr& alu, AluInstr::SrcValues src(4); - for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) { - auto dest = value_factory.dest(alu.dest.dest.ssa, 2 * k, pin_chan); + for (unsigned k = 0; k < alu.def.num_components; ++k) { + auto dest = value_factory.dest(alu.def, 2 * k, pin_chan); src[0] = value_factory.src64(alu.src[order[0]], k, 1); src[1] = value_factory.src64(alu.src[order[1]], k, 1); src[2] = value_factory.src64(alu.src[order[0]], k, 0); @@ -2175,7 +2175,7 @@ emit_alu_op1_64bit_trans(const nir_alu_instr& alu, EAluOp opcode, Shader& shader AluInstr *ir = nullptr; for (unsigned i = 0; i < 3; ++i) { ir = new AluInstr(opcode, - i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) + i < 2 ? value_factory.dest(alu.def, i, pin_chan) : value_factory.dummy_dest(i), value_factory.src64(alu.src[0], 0, 1), value_factory.src64(alu.src[0], 0, 0), @@ -2201,7 +2201,7 @@ emit_alu_fma_64bit(const nir_alu_instr& alu, EAluOp opcode, Shader& shader) int chan = i < 3 ? 1 : 0; auto dest = - i < 2 ? value_factory.dest(alu.dest.dest.ssa, i, pin_chan) : value_factory.dummy_dest(i); + i < 2 ? value_factory.dest(alu.def, i, pin_chan) : value_factory.dummy_dest(i); ir = new AluInstr(opcode, dest, @@ -2224,16 +2224,16 @@ emit_alu_b2f64(const nir_alu_instr& alu, Shader& shader) auto group = new AluGroup(); AluInstr *ir = nullptr; - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(op2_and_int, - value_factory.dest(alu.dest.dest.ssa, 2 * i, pin_group), + value_factory.dest(alu.def, 2 * i, pin_group), value_factory.src(alu.src[0], i), value_factory.zero(), {alu_write}); group->add_instruction(ir); ir = new AluInstr(op2_and_int, - value_factory.dest(alu.dest.dest.ssa, 2 * i + 1, pin_group), + value_factory.dest(alu.def, 2 * i + 1, pin_group), value_factory.src(alu.src[0], i), value_factory.literal(0x3ff00000), {alu_write}); @@ -2253,7 +2253,7 @@ emit_alu_i2f64(const nir_alu_instr& alu, EAluOp op, Shader& shader) auto group = new AluGroup(); AluInstr *ir = nullptr; - assert(alu.dest.dest.ssa.num_components == 1); + assert(alu.def.num_components == 1); auto tmpx = value_factory.temp_register(); shader.emit_instruction(new AluInstr(op2_and_int, @@ -2292,13 +2292,13 @@ emit_alu_i2f64(const nir_alu_instr& alu, EAluOp op, Shader& shader) group = new AluGroup(); ir = new AluInstr(op2_add_64, - value_factory.dest(alu.dest.dest.ssa, 0, pin_chan), + value_factory.dest(alu.def, 0, pin_chan), tmpy3, tmpw3, AluInstr::write); group->add_instruction(ir); ir = new AluInstr(op2_add_64, - value_factory.dest(alu.dest.dest.ssa, 1, pin_chan), + value_factory.dest(alu.def, 1, pin_chan), tmpx3, tmpz3, AluInstr::write); @@ -2315,15 +2315,15 @@ emit_alu_f2f64(const nir_alu_instr& alu, Shader& shader) auto group = new AluGroup(); AluInstr *ir = nullptr; - assert(alu.dest.dest.ssa.num_components == 1); + assert(alu.def.num_components == 1); ir = new AluInstr(op1_flt32_to_flt64, - value_factory.dest(alu.dest.dest.ssa, 0, pin_chan), + value_factory.dest(alu.def, 0, pin_chan), value_factory.src(alu.src[0], 0), AluInstr::write); group->add_instruction(ir); ir = new AluInstr(op1_flt32_to_flt64, - value_factory.dest(alu.dest.dest.ssa, 1, pin_chan), + value_factory.dest(alu.def, 1, pin_chan), value_factory.zero(), AluInstr::last_write); group->add_instruction(ir); @@ -2339,7 +2339,7 @@ emit_alu_f2f32(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; ir = new AluInstr(op1v_flt64_to_flt32, - value_factory.dest(alu.dest.dest.ssa, 0, pin_chan), + value_factory.dest(alu.def, 0, pin_chan), value_factory.src64(alu.src[0], 0, 1), {alu_write}); group->add_instruction(ir); @@ -2359,10 +2359,10 @@ emit_alu_b2x(const nir_alu_instr& alu, AluInlineConstants mask, Shader& shader) AluInstr *ir = nullptr; auto pin = pin_for_components(alu); - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { auto src = value_factory.src(alu.src[0], i); ir = new AluInstr(op2_and_int, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), src, value_factory.inline_const(mask, 0), {alu_write}); @@ -2384,9 +2384,9 @@ emit_alu_op1(const nir_alu_instr& alu, AluInstr *ir = nullptr; auto pin = pin_for_components(alu); - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), value_factory.src(alu.src[0], i), {alu_write}); switch (mod) { @@ -2426,9 +2426,9 @@ emit_alu_op2(const nir_alu_instr& alu, auto pin = pin_for_components(alu); AluInstr *ir = nullptr; - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), value_factory.src(*src0, i), value_factory.src(*src1, i), {alu_write}); @@ -2464,9 +2464,9 @@ emit_alu_op3(const nir_alu_instr& alu, auto pin = pin_for_components(alu); AluInstr *ir = nullptr; - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), value_factory.src(*src[0], i), value_factory.src(*src[1], i), value_factory.src(*src[2], i), @@ -2501,7 +2501,7 @@ emit_any_all_fcomp2(const nir_alu_instr& alu, EAluOp opcode, Shader& shader) opcode = (opcode == op2_setne_dx10) ? op2_or_int : op2_and_int; ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, 0, pin_free), + value_factory.dest(alu.def, 0, pin_free), tmp[0], tmp[1], AluInstr::last_write); @@ -2556,7 +2556,7 @@ emit_any_all_fcomp(const nir_alu_instr& alu, EAluOp op, int nc, bool all, Shader op = (op == op2_sete) ? op2_setne_dx10 : op2_sete_dx10; ir = new AluInstr(op, - value_factory.dest(alu.dest.dest.ssa, 0, pin_free), + value_factory.dest(alu.def, 0, pin_free), max_val, value_factory.inline_const(ALU_SRC_1, 0), AluInstr::last_write); @@ -2576,7 +2576,7 @@ emit_any_all_icomp(const nir_alu_instr& alu, EAluOp op, int nc, bool all, Shader AluInstr *ir = nullptr; PRegister v[6]; - auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free); + auto dest = value_factory.dest(alu.def, 0, pin_free); for (int i = 0; i < nc + nc / 2; ++i) v[i] = value_factory.temp_register(); @@ -2628,7 +2628,7 @@ emit_dot(const nir_alu_instr& alu, int n, Shader& shader) const nir_alu_src& src0 = alu.src[0]; const nir_alu_src& src1 = alu.src[1]; - auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_chan); + auto dest = value_factory.dest(alu.def, 0, pin_chan); AluInstr::SrcValues srcs(2 * n); @@ -2652,7 +2652,7 @@ emit_dot4(const nir_alu_instr& alu, int nelm, Shader& shader) const nir_alu_src& src0 = alu.src[0]; const nir_alu_src& src1 = alu.src[1]; - auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free); + auto dest = value_factory.dest(alu.def, 0, pin_free); AluInstr::SrcValues srcs(8); @@ -2679,7 +2679,7 @@ emit_fdph(const nir_alu_instr& alu, Shader& shader) const nir_alu_src& src0 = alu.src[0]; const nir_alu_src& src1 = alu.src[1]; - auto dest = value_factory.dest(alu.dest.dest.ssa, 0, pin_free); + auto dest = value_factory.dest(alu.def, 0, pin_free); AluInstr::SrcValues srcs(8); @@ -2704,7 +2704,7 @@ emit_create_vec(const nir_alu_instr& instr, unsigned nc, Shader& shader) for (unsigned i = 0; i < nc; ++i) { auto src = value_factory.src(instr.src[i].src, instr.src[i].swizzle[0]); - auto dst = value_factory.dest(instr.dest.dest.ssa, i, pin_none); + auto dst = value_factory.dest(instr.def, i, pin_none); shader.emit_instruction(new AluInstr(op1_mov, dst, src, {alu_write})); } @@ -2719,9 +2719,9 @@ emit_alu_comb_with_zero(const nir_alu_instr& alu, EAluOp opcode, Shader& shader) auto& value_factory = shader.value_factory(); AluInstr *ir = nullptr; auto pin = pin_for_components(alu); - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), value_factory.zero(), value_factory.src(alu.src[0], i), AluInstr::write); @@ -2740,7 +2740,7 @@ emit_pack_64_2x32_split(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; for (unsigned i = 0; i < 2; ++i) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, i, pin_none), + value_factory.dest(alu.def, i, pin_none), value_factory.src(alu.src[i], 0), AluInstr::write); shader.emit_instruction(ir); @@ -2756,7 +2756,7 @@ emit_pack_64_2x32(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; for (unsigned i = 0; i < 2; ++i) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, i, pin_none), + value_factory.dest(alu.def, i, pin_none), value_factory.src(alu.src[0], i), AluInstr::write); shader.emit_instruction(ir); @@ -2772,7 +2772,7 @@ emit_unpack_64_2x32(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; for (unsigned i = 0; i < 2; ++i) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, i, pin_none), + value_factory.dest(alu.def, i, pin_none), value_factory.src64(alu.src[0], 0, i), AluInstr::write); shader.emit_instruction(ir); @@ -2788,14 +2788,14 @@ emit_alu_vec2_64(const nir_alu_instr& alu, Shader& shader) AluInstr *ir = nullptr; for (unsigned i = 0; i < 2; ++i) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, i, pin_chan), + value_factory.dest(alu.def, i, pin_chan), value_factory.src64(alu.src[0], 0, i), AluInstr::write); shader.emit_instruction(ir); } for (unsigned i = 0; i < 2; ++i) { ir = new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, i + 2, pin_chan), + value_factory.dest(alu.def, i + 2, pin_chan), value_factory.src64(alu.src[1], 1, i), AluInstr::write); shader.emit_instruction(ir); @@ -2823,7 +2823,7 @@ emit_pack_32_2x16_split(const nir_alu_instr& alu, Shader& shader) new AluInstr(op2_lshl_int, yy, y, value_factory.literal(16), AluInstr::last_write)); shader.emit_instruction(new AluInstr(op2_or_int, - value_factory.dest(alu.dest.dest.ssa, 0, pin_free), + value_factory.dest(alu.def, 0, pin_free), x, yy, AluInstr::last_write)); @@ -2835,7 +2835,7 @@ emit_unpack_64_2x32_split(const nir_alu_instr& alu, int comp, Shader& shader) { auto& value_factory = shader.value_factory(); shader.emit_instruction(new AluInstr(op1_mov, - value_factory.dest(alu.dest.dest.ssa, 0, pin_free), + value_factory.dest(alu.def, 0, pin_free), value_factory.src64(alu.src[0], 0, comp), AluInstr::last_write)); return true; @@ -2846,7 +2846,7 @@ emit_unpack_32_2x16_split_x(const nir_alu_instr& alu, Shader& shader) { auto& value_factory = shader.value_factory(); shader.emit_instruction(new AluInstr(op1_flt16_to_flt32, - value_factory.dest(alu.dest.dest.ssa, 0, pin_free), + value_factory.dest(alu.def, 0, pin_free), value_factory.src(alu.src[0], 0), AluInstr::last_write)); return true; @@ -2863,7 +2863,7 @@ emit_unpack_32_2x16_split_y(const nir_alu_instr& alu, Shader& shader) AluInstr::last_write)); shader.emit_instruction(new AluInstr(op1_flt16_to_flt32, - value_factory.dest(alu.dest.dest.ssa, 0, pin_free), + value_factory.dest(alu.def, 0, pin_free), tmp, AluInstr::last_write)); return true; @@ -2878,9 +2878,9 @@ emit_alu_trans_op1_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader) AluInstr *ir = nullptr; auto pin = pin_for_components(alu); - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), value_factory.src(src0, i), AluInstr::last_write); ir->set_alu_flag(alu_is_trans); @@ -2898,7 +2898,7 @@ emit_alu_f2i32_or_u32_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader PRegister reg[4]; - int num_comp = alu.dest.dest.ssa.num_components; + int num_comp = alu.def.num_components; for (int i = 0; i < num_comp; ++i) { reg[i] = value_factory.temp_register(); @@ -2912,7 +2912,7 @@ emit_alu_f2i32_or_u32_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader auto pin = pin_for_components(alu); for (int i = 0; i < num_comp; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), reg[i], AluInstr::write); if (opcode == op1_flt_to_uint) { @@ -2935,11 +2935,11 @@ emit_alu_trans_op1_cayman(const nir_alu_instr& alu, EAluOp opcode, Shader& shade const std::set flags({alu_write, alu_last_instr, alu_is_cayman_trans}); - for (unsigned j = 0; j < alu.dest.dest.ssa.num_components; ++j) { + for (unsigned j = 0; j < alu.def.num_components; ++j) { unsigned ncomp = j == 3 ? 4 : 3; AluInstr::SrcValues srcs(ncomp); - PRegister dest = value_factory.dest(alu.dest.dest.ssa, j, pin, (1 << ncomp) - 1); + PRegister dest = value_factory.dest(alu.def, j, pin, (1 << ncomp) - 1); for (unsigned i = 0; i < ncomp; ++i) srcs[i] = value_factory.src(src0, j); @@ -2961,9 +2961,9 @@ emit_alu_trans_op2_eg(const nir_alu_instr& alu, EAluOp opcode, Shader& shader) AluInstr *ir = nullptr; auto pin = pin_for_components(alu); - for (unsigned i = 0; i < alu.dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu.def.num_components; ++i) { ir = new AluInstr(opcode, - value_factory.dest(alu.dest.dest.ssa, i, pin), + value_factory.dest(alu.def, i, pin), value_factory.src(src0, i), value_factory.src(src1, i), AluInstr::last_write); @@ -2985,9 +2985,9 @@ emit_alu_trans_op2_cayman(const nir_alu_instr& alu, EAluOp opcode, Shader& shade const std::set flags({alu_write, alu_last_instr, alu_is_cayman_trans}); - for (unsigned k = 0; k < alu.dest.dest.ssa.num_components; ++k) { + for (unsigned k = 0; k < alu.def.num_components; ++k) { AluInstr::SrcValues srcs(2 * last_slot); - PRegister dest = value_factory.dest(alu.dest.dest.ssa, k, pin_free); + PRegister dest = value_factory.dest(alu.def, k, pin_free); for (unsigned i = 0; i < last_slot; ++i) { srcs[2 * i] = value_factory.src(src0, k); @@ -3006,7 +3006,7 @@ emit_tex_fdd(const nir_alu_instr& alu, TexInstr::Opcode opcode, bool fine, Shade { auto& value_factory = shader.value_factory(); - int ncomp = alu.dest.dest.ssa.num_components; + int ncomp = alu.def.num_components; RegisterVec4::Swizzle src_swz = {7, 7, 7, 7}; RegisterVec4::Swizzle tmp_swz = {7, 7, 7, 7}; for (auto i = 0; i < ncomp; ++i) { @@ -3025,7 +3025,7 @@ emit_tex_fdd(const nir_alu_instr& alu, TexInstr::Opcode opcode, bool fine, Shade if (mv) mv->set_alu_flag(alu_last_instr); - auto dst = value_factory.dest_vec4(alu.dest.dest.ssa, pin_group); + auto dst = value_factory.dest_vec4(alu.def, pin_group); RegisterVec4::Swizzle dst_swz = {7, 7, 7, 7}; for (auto i = 0; i < ncomp; ++i) { dst_swz[i] = i; @@ -3055,7 +3055,7 @@ emit_alu_cube(const nir_alu_instr& alu, Shader& shader) for (int i = 0; i < 4; ++i) { ir = new AluInstr(op2_cube, - value_factory.dest(alu.dest.dest.ssa, i, pin_chan), + value_factory.dest(alu.def, i, pin_chan), value_factory.src(alu.src[0], src0_chan[i]), value_factory.src(alu.src[0], src1_chan[i]), AluInstr::write); diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp index ef00033..654cf7c 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_64bit.cpp @@ -156,7 +156,7 @@ class LowerSplit64op : public NirLowerInstruction { auto alu = nir_instr_as_alu(instr); switch (alu->op) { case nir_op_bcsel: - return alu->dest.dest.ssa.bit_size == 64; + return alu->def.bit_size == 64; case nir_op_f2i32: case nir_op_f2u32: case nir_op_f2i64: @@ -304,9 +304,9 @@ LowerSplit64BitVar::filter(const nir_instr *instr) const auto alu = nir_instr_as_alu(instr); switch (alu->op) { case nir_op_bcsel: - if (alu->dest.dest.ssa.num_components < 3) + if (alu->def.num_components < 3) return false; - return alu->dest.dest.ssa.bit_size == 64; + return alu->def.bit_size == 64; case nir_op_bany_fnequal3: case nir_op_bany_fnequal4: case nir_op_ball_fequal3: @@ -700,13 +700,13 @@ nir_def * LowerSplit64BitVar::split_bcsel(nir_alu_instr *alu) { static nir_def *dest[4]; - for (unsigned i = 0; i < alu->dest.dest.ssa.num_components; ++i) { + for (unsigned i = 0; i < alu->def.num_components; ++i) { dest[i] = nir_bcsel(b, nir_channel(b, alu->src[0].src.ssa, i), nir_channel(b, alu->src[1].src.ssa, i), nir_channel(b, alu->src[2].src.ssa, i)); } - return nir_vec(b, dest, alu->dest.dest.ssa.num_components); + return nir_vec(b, dest, alu->def.num_components); } nir_def * @@ -850,7 +850,7 @@ Lower64BitToVec2::filter(const nir_instr *instr) const } case nir_instr_type_alu: { auto alu = nir_instr_as_alu(instr); - return alu->dest.dest.ssa.bit_size == 64; + return alu->def.bit_size == 64; } case nir_instr_type_phi: { auto phi = nir_instr_as_phi(instr); @@ -896,8 +896,8 @@ Lower64BitToVec2::lower(nir_instr *instr) } case nir_instr_type_alu: { auto alu = nir_instr_as_alu(instr); - alu->dest.dest.ssa.bit_size = 32; - alu->dest.dest.ssa.num_components *= 2; + alu->def.bit_size = 32; + alu->def.num_components *= 2; switch (alu->op) { case nir_op_pack_64_2x32_split: alu->op = nir_op_vec2; diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp index 1132fe9..22c03ba 100644 --- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp +++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_fs_out_to_vector.cpp @@ -486,9 +486,9 @@ NirLowerFSOutToVector::create_combined_vector(nir_builder *b, k += s->num_components; } - nir_def_init(&instr->instr, &instr->dest.dest.ssa, num_comp, 32); + nir_def_init(&instr->instr, &instr->def, num_comp, 32); nir_builder_instr_insert(b, &instr->instr); - return &instr->dest.dest.ssa; + return &instr->def; } } // namespace r600 diff --git a/src/gallium/drivers/r600/sfn/tests/sfn_valuefactory_test.cpp b/src/gallium/drivers/r600/sfn/tests/sfn_valuefactory_test.cpp index 779d20f..c102c9d 100644 --- a/src/gallium/drivers/r600/sfn/tests/sfn_valuefactory_test.cpp +++ b/src/gallium/drivers/r600/sfn/tests/sfn_valuefactory_test.cpp @@ -55,8 +55,8 @@ TEST_F(ValuefactoryTest, test_create_ssa) auto sum = nir_fadd(&b, c1, c2); auto alu = nir_instr_as_alu(sum->parent_instr); - sfn_log << SfnLog::reg << "Search (test) " << &alu->dest << "\n"; - auto dest_value = factory->dest(alu->dest.dest.ssa, 0, pin_none); + sfn_log << SfnLog::reg << "Search (test) " << &alu->def << "\n"; + auto dest_value = factory->dest(alu->def, 0, pin_none); EXPECT_EQ(dest_value->sel(), 1024); EXPECT_EQ(dest_value->chan(), 0); EXPECT_EQ(dest_value->pin(), pin_none); @@ -76,7 +76,7 @@ TEST_F(ValuefactoryTest, test_create_ssa_pinned_chan) auto sum = nir_fadd(&b, c1, c2); auto alu = nir_instr_as_alu(sum->parent_instr); - auto dest_value = factory->dest(alu->dest.dest.ssa, 0, pin_chan); + auto dest_value = factory->dest(alu->def, 0, pin_chan); EXPECT_EQ(dest_value->sel(), 1024); EXPECT_EQ(dest_value->chan(), 0); EXPECT_EQ(dest_value->pin(), pin_chan); @@ -94,7 +94,7 @@ TEST_F(ValuefactoryTest, test_create_ssa_pinned_chan_and_reg) auto sum = nir_fadd(&b, c1, c2); auto alu = nir_instr_as_alu(sum->parent_instr); - auto dest_value = factory->dest(alu->dest.dest.ssa, 1, pin_chan); + auto dest_value = factory->dest(alu->def, 1, pin_chan); EXPECT_EQ(dest_value->sel(), 1024); EXPECT_EQ(dest_value->chan(), 1); EXPECT_EQ(dest_value->pin(), pin_chan); diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index 6789780..7ac7775 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -15,8 +15,8 @@ bool si_alu_to_scalar_packed_math_filter(const nir_instr *instr, const void *dat if (instr->type == nir_instr_type_alu) { nir_alu_instr *alu = nir_instr_as_alu(instr); - if (alu->dest.dest.ssa.bit_size == 16 && - alu->dest.dest.ssa.num_components == 2) + if (alu->def.bit_size == 16 && + alu->def.num_components == 2) return false; } @@ -29,7 +29,7 @@ static uint8_t si_vectorize_callback(const nir_instr *instr, const void *data) return 0; nir_alu_instr *alu = nir_instr_as_alu(instr); - if (alu->dest.dest.ssa.bit_size == 16) { + if (alu->def.bit_size == 16) { switch (alu->op) { case nir_op_unpack_32_2x16_split_x: case nir_op_unpack_32_2x16_split_y: @@ -52,7 +52,7 @@ static unsigned si_lower_bit_size_callback(const nir_instr *instr, void *data) switch (alu->op) { case nir_op_imul_high: case nir_op_umul_high: - if (alu->dest.dest.ssa.bit_size < 32) + if (alu->def.bit_size < 32) return 32; break; default: diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c index bd90307..1e3441f 100644 --- a/src/gallium/drivers/vc4/vc4_program.c +++ b/src/gallium/drivers/vc4/vc4_program.c @@ -841,7 +841,7 @@ ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr) struct qreg rep = ntq_get_src(c, instr->src[0].src, instr->src[0].swizzle[0]); - ntq_store_def(c, &instr->dest.dest.ssa, 0, qir_PACK_8888_F(c, rep)); + ntq_store_def(c, &instr->def, 0, qir_PACK_8888_F(c, rep)); return; } @@ -871,7 +871,7 @@ ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr) qir_PACK_8_F(c, result, src, i); } - ntq_store_def(c, &instr->dest.dest.ssa, 0, qir_MOV(c, result)); + ntq_store_def(c, &instr->def, 0, qir_MOV(c, result)); } /** Handles sign-extended bitfield extracts for 16 bits. */ @@ -1072,7 +1072,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) srcs[i] = ntq_get_src(c, instr->src[i].src, instr->src[i].swizzle[0]); for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) - ntq_store_def(c, &instr->dest.dest.ssa, i, + ntq_store_def(c, &instr->def, i, qir_MOV(c, srcs[i])); return; } @@ -1085,9 +1085,9 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) if (instr->op == nir_op_unpack_unorm_4x8) { struct qreg src = ntq_get_src(c, instr->src[0].src, instr->src[0].swizzle[0]); - unsigned count = instr->dest.dest.ssa.num_components; + unsigned count = instr->def.num_components; for (int i = 0; i < count; i++) { - ntq_store_def(c, &instr->dest.dest.ssa, i, + ntq_store_def(c, &instr->def, i, qir_UNPACK_8_F(c, src, i)); } return; @@ -1302,7 +1302,7 @@ ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr) abort(); } - ntq_store_def(c, &instr->dest.dest.ssa, 0, result); + ntq_store_def(c, &instr->def, 0, result); } static void diff --git a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c index e1bd21d..700a057 100644 --- a/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c +++ b/src/gallium/drivers/zink/nir_to_spirv/nir_to_spirv.c @@ -179,7 +179,7 @@ infer_nir_alu_type_from_use(nir_src *src) } /* ignore typeless ops */ if (alu_op_is_typeless(alu->op)) { - atype = infer_nir_alu_type_from_uses_ssa(&alu->dest.dest.ssa); + atype = infer_nir_alu_type_from_uses_ssa(&alu->def); break; } for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { @@ -2037,7 +2037,7 @@ alu_instr_src_components(const nir_alu_instr *instr, unsigned src) if (nir_op_infos[instr->op].input_sizes[src] > 0) return nir_op_infos[instr->op].input_sizes[src]; - return instr->dest.dest.ssa.num_components; + return instr->def.num_components; } static SpvId @@ -2077,7 +2077,7 @@ get_alu_src(struct ntv_context *ctx, nir_alu_instr *alu, unsigned src, SpvId *ra static void store_alu_result(struct ntv_context *ctx, nir_alu_instr *alu, SpvId result, nir_alu_type atype) { - store_def(ctx, &alu->dest.dest.ssa, result, atype); + store_def(ctx, &alu->def, result, atype); } static SpvId @@ -2158,12 +2158,12 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) } } - unsigned bit_size = alu->dest.dest.ssa.bit_size; - unsigned num_components = alu->dest.dest.ssa.num_components; + unsigned bit_size = alu->def.bit_size; + unsigned num_components = alu->def.num_components; nir_alu_type atype = bit_size == 1 ? nir_type_bool : (alu_op_is_typeless(alu->op) ? typeless_type : nir_op_infos[alu->op].output_type); - SpvId dest_type = get_def_type(ctx, &alu->dest.dest.ssa, atype); + SpvId dest_type = get_def_type(ctx, &alu->def, atype); if (needs_derivative_control(alu)) spirv_builder_emit_cap(&ctx->builder, SpvCapabilityDerivativeControl); @@ -2265,7 +2265,7 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) #define BUILTIN_UNOPF(nir_op, spirv_op) \ case nir_op: \ assert(nir_op_infos[alu->op].num_inputs == 1); \ - result = emit_builtin_unop(ctx, spirv_op, get_def_type(ctx, &alu->dest.dest.ssa, nir_type_float), src[0]); \ + result = emit_builtin_unop(ctx, spirv_op, get_def_type(ctx, &alu->def, nir_type_float), src[0]); \ atype = nir_type_float; \ break; @@ -2290,12 +2290,12 @@ emit_alu(struct ntv_context *ctx, nir_alu_instr *alu) case nir_op_pack_half_2x16: assert(nir_op_infos[alu->op].num_inputs == 1); - result = emit_builtin_unop(ctx, GLSLstd450PackHalf2x16, get_def_type(ctx, &alu->dest.dest.ssa, nir_type_uint), src[0]); + result = emit_builtin_unop(ctx, GLSLstd450PackHalf2x16, get_def_type(ctx, &alu->def, nir_type_uint), src[0]); break; case nir_op_unpack_64_2x32: assert(nir_op_infos[alu->op].num_inputs == 1); - result = emit_builtin_unop(ctx, GLSLstd450UnpackDouble2x32, get_def_type(ctx, &alu->dest.dest.ssa, nir_type_uint), src[0]); + result = emit_builtin_unop(ctx, GLSLstd450UnpackDouble2x32, get_def_type(ctx, &alu->def, nir_type_uint), src[0]); break; BUILTIN_UNOPF(nir_op_unpack_half_2x16, GLSLstd450UnpackHalf2x16) diff --git a/src/gallium/drivers/zink/zink_compiler.c b/src/gallium/drivers/zink/zink_compiler.c index ef4085e..9cc119b 100644 --- a/src/gallium/drivers/zink/zink_compiler.c +++ b/src/gallium/drivers/zink/zink_compiler.c @@ -1183,7 +1183,7 @@ lower_64bit_pack_instr(nir_builder *b, nir_instr *instr, void *data) default: unreachable("Impossible opcode"); } - nir_def_rewrite_uses(&alu_instr->dest.dest.ssa, dest); + nir_def_rewrite_uses(&alu_instr->def, dest); nir_instr_remove(&alu_instr->instr); return true; } @@ -4509,7 +4509,7 @@ split_bitfields_instr(nir_builder *b, nir_instr *in, void *data) default: return false; } - unsigned num_components = alu->dest.dest.ssa.num_components; + unsigned num_components = alu->def.num_components; if (num_components == 1) return false; b->cursor = nir_before_instr(in); @@ -4533,7 +4533,7 @@ split_bitfields_instr(nir_builder *b, nir_instr *in, void *data) nir_channel(b, alu->src[2].src.ssa, alu->src[2].swizzle[i])); } nir_def *dest = nir_vec(b, dests, num_components); - nir_def_rewrite_uses_after(&alu->dest.dest.ssa, dest, in); + nir_def_rewrite_uses_after(&alu->def, dest, in); nir_instr_remove(in); return true; } diff --git a/src/imagination/rogue/rogue_compile.c b/src/imagination/rogue/rogue_compile.c index bd1e317..2a204d8 100644 --- a/src/imagination/rogue/rogue_compile.c +++ b/src/imagination/rogue/rogue_compile.c @@ -78,8 +78,8 @@ static rogue_ref nir_ssa_reg_alu_src(rogue_shader *shader, static rogue_ref nir_ssa_reg_alu_dst(rogue_shader *shader, const nir_alu_instr *alu, bool vec) { - unsigned num_components = alu->dest.dest.ssa.num_components; - unsigned index = alu->dest.dest.ssa.index; + unsigned num_components = alu->def.num_components; + unsigned index = alu->def.index; assert(num_components == 1); @@ -605,7 +605,7 @@ static void trans_nir_alu_ffma(rogue_builder *b, nir_alu_instr *alu) static void trans_nir_alu_vecN(rogue_builder *b, nir_alu_instr *alu, unsigned n) { - unsigned dst_index = alu->dest.dest.ssa.index; + unsigned dst_index = alu->def.index; rogue_regarray *dst; rogue_reg *src; @@ -618,7 +618,7 @@ static void trans_nir_alu_vecN(rogue_builder *b, nir_alu_instr *alu, unsigned n) static void trans_nir_alu_iadd64(rogue_builder *b, nir_alu_instr *alu) { - unsigned dst_index = alu->dest.dest.ssa.index; + unsigned dst_index = alu->def.index; rogue_regarray *dst[2] = { rogue_ssa_vec_regarray(b->shader, 1, dst_index, 0), rogue_ssa_vec_regarray(b->shader, 1, dst_index, 1), @@ -650,7 +650,7 @@ static void trans_nir_alu_iadd64(rogue_builder *b, nir_alu_instr *alu) static void trans_nir_alu_iadd(rogue_builder *b, nir_alu_instr *alu) { - unsigned bit_size = alu->dest.dest.ssa.bit_size; + unsigned bit_size = alu->def.bit_size; switch (bit_size) { /* TODO: case 32: */ diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 18cfcc3..0a5fdf1 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -640,11 +640,11 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld, bool need_dest) { fs_reg result = - need_dest ? get_nir_def(instr->dest.dest.ssa) : bld.null_reg_ud(); + need_dest ? get_nir_def(instr->def) : bld.null_reg_ud(); result.type = brw_type_for_nir_type(devinfo, (nir_alu_type)(nir_op_infos[instr->op].output_type | - instr->dest.dest.ssa.bit_size)); + instr->def.bit_size)); for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { op[i] = get_nir_src(instr->src[i].src); @@ -679,7 +679,7 @@ fs_visitor::prepare_alu_destination_and_sources(const fs_builder &bld, /* Since NIR is doing the scalarizing for us, we should only ever see * vectorized operations with a single channel. */ - nir_component_mask_t write_mask = get_nir_write_mask(instr->dest.dest.ssa); + nir_component_mask_t write_mask = get_nir_write_mask(instr->def); assert(util_bitcount(write_mask) == 1); channel = ffs(write_mask) - 1; @@ -732,7 +732,7 @@ fs_visitor::try_emit_b2fi_of_inot(const fs_builder &bld, * The source restriction is just because I was lazy about generating the * constant below. */ - if (instr->dest.dest.ssa.bit_size != 32 || + if (instr->def.bit_size != 32 || nir_src_bit_size(inot_instr->src[0].src) != 32) return false; @@ -791,7 +791,7 @@ fs_visitor::emit_fsign(const fs_builder &bld, const nir_alu_instr *instr, /* Since NIR is doing the scalarizing for us, we should only ever see * vectorized operations with a single channel. */ - nir_component_mask_t write_mask = get_nir_write_mask(instr->dest.dest.ssa); + nir_component_mask_t write_mask = get_nir_write_mask(instr->def); assert(util_bitcount(write_mask) == 1); channel = ffs(write_mask) - 1; } @@ -978,7 +978,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, bool need_extra_copy = false; nir_intrinsic_instr *store_reg = - nir_store_reg_for_def(&instr->dest.dest.ssa); + nir_store_reg_for_def(&instr->def); if (store_reg != NULL) { nir_def *dest_reg = store_reg->src[1].ssa; for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { @@ -995,7 +995,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, } } - nir_component_mask_t write_mask = get_nir_write_mask(instr->dest.dest.ssa); + nir_component_mask_t write_mask = get_nir_write_mask(instr->def); unsigned last_bit = util_last_bit(write_mask); for (unsigned i = 0; i < last_bit; i++) { @@ -1234,13 +1234,13 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, case nir_op_irhadd: case nir_op_urhadd: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); inst = bld.AVG(result, op[0], op[1]); break; case nir_op_ihadd: case nir_op_uhadd: { - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); fs_reg tmp = bld.vgrf(result.type); if (devinfo->ver >= 8) { @@ -1292,7 +1292,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, const enum brw_reg_type dword_type = ud ? BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_D; - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); /* Before copy propagation there are no immediate values. */ assert(op[0].file != IMM && op[1].file != IMM); @@ -1308,14 +1308,14 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, } case nir_op_imul: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); bld.MUL(result, op[0], op[1]); break; case nir_op_imul_high: case nir_op_umul_high: - assert(instr->dest.dest.ssa.bit_size < 64); - if (instr->dest.dest.ssa.bit_size == 32) { + assert(instr->def.bit_size < 64); + if (instr->def.bit_size == 32) { bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]); } else { fs_reg tmp = bld.vgrf(brw_reg_type_from_bit_size(32, op[0].type)); @@ -1326,7 +1326,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, case nir_op_idiv: case nir_op_udiv: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]); break; @@ -1342,7 +1342,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, * appears that our hardware just does the right thing for signed * remainder. */ - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]); break; @@ -1458,7 +1458,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, result.type = brw_type_for_nir_type(devinfo, (nir_alu_type)(nir_type_int | - instr->dest.dest.ssa.bit_size)); + instr->def.bit_size)); op[0].type = brw_type_for_nir_type(devinfo, (nir_alu_type)(nir_type_int | @@ -1673,25 +1673,25 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, break; case nir_op_bitfield_reverse: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); bld.BFREV(result, op[0]); break; case nir_op_bit_count: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) < 64); bld.CBIT(result, op[0]); break; case nir_op_uclz: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); bld.LZD(retype(result, BRW_REGISTER_TYPE_UD), op[0]); break; case nir_op_ifind_msb: { - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); @@ -1711,7 +1711,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, } case nir_op_find_lsb: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); bld.FBL(result, op[0]); @@ -1722,15 +1722,15 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, unreachable("should have been lowered"); case nir_op_ubfe: case nir_op_ibfe: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); bld.BFE(result, op[2], op[1], op[0]); break; case nir_op_bfm: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); bld.BFI1(result, op[0], op[1]); break; case nir_op_bfi: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); /* bfi is ((...) | (~src0 & src2)). The second part is zero when src2 is * either 0 or src0. Replacing the 0 with another value can eliminate a @@ -1870,7 +1870,7 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr, * There is no direct conversion from B/UB to Q/UQ or Q/UQ to B/UB. * Use two instructions and a word or DWord intermediate integer type. */ - if (instr->dest.dest.ssa.bit_size == 64) { + if (instr->def.bit_size == 64) { const brw_reg_type type = brw_int_type(1, instr->op == nir_op_extract_i8); if (instr->op == nir_op_extract_i8) { diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 0317d2d..d9e0170 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -767,7 +767,7 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) break; } - if (alu->dest.dest.ssa.bit_size >= 32) + if (alu->def.bit_size >= 32) return 0; /* Note: nir_op_iabs and nir_op_ineg are not lowered here because the @@ -801,7 +801,7 @@ lower_bit_size_callback(const nir_instr *instr, UNUSED void *data) return 0; default: if (nir_op_infos[alu->op].num_inputs >= 2 && - alu->dest.dest.ssa.bit_size == 8) + alu->def.bit_size == 8) return 16; if (nir_alu_instr_is_comparison(alu) && diff --git a/src/intel/compiler/brw_nir_lower_conversions.c b/src/intel/compiler/brw_nir_lower_conversions.c index 6e30c86..329aa9d 100644 --- a/src/intel/compiler/brw_nir_lower_conversions.c +++ b/src/intel/compiler/brw_nir_lower_conversions.c @@ -46,7 +46,7 @@ split_conversion(nir_builder *b, nir_alu_instr *alu, nir_alu_type src_type, nir_def *src = nir_ssa_for_alu_src(b, alu, 0); nir_def *tmp = nir_type_convert(b, src, src_type, tmp_type, nir_rounding_mode_undef); nir_def *res = nir_type_convert(b, tmp, tmp_type, dst_type, rnd); - nir_def_rewrite_uses(&alu->dest.dest.ssa, res); + nir_def_rewrite_uses(&alu->def, res); nir_instr_remove(&alu->instr); } @@ -57,7 +57,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu) nir_alu_type src_type = nir_op_infos[alu->op].input_types[0]; nir_alu_type src_full_type = (nir_alu_type) (src_type | src_bit_size); - unsigned dst_bit_size = alu->dest.dest.ssa.bit_size; + unsigned dst_bit_size = alu->def.bit_size; nir_alu_type dst_full_type = nir_op_infos[alu->op].output_type; nir_alu_type dst_type = nir_alu_type_get_base_type(dst_full_type); diff --git a/src/intel/compiler/brw_nir_opt_peephole_ffma.c b/src/intel/compiler/brw_nir_opt_peephole_ffma.c index 26437a0..5a7f629 100644 --- a/src/intel/compiler/brw_nir_opt_peephole_ffma.c +++ b/src/intel/compiler/brw_nir_opt_peephole_ffma.c @@ -48,7 +48,7 @@ are_all_uses_fadd(nir_def *def) case nir_op_mov: case nir_op_fneg: case nir_op_fabs: - if (!are_all_uses_fadd(&use_alu->dest.dest.ssa)) + if (!are_all_uses_fadd(&use_alu->def)) return false; break; @@ -84,18 +84,18 @@ get_mul_for_src(nir_alu_src *src, unsigned num_components, switch (alu->op) { case nir_op_mov: - alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components, + alu = get_mul_for_src(&alu->src[0], alu->def.num_components, swizzle, negate, abs); break; case nir_op_fneg: - alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components, + alu = get_mul_for_src(&alu->src[0], alu->def.num_components, swizzle, negate, abs); *negate = !*negate; break; case nir_op_fabs: - alu = get_mul_for_src(&alu->src[0], alu->dest.dest.ssa.num_components, + alu = get_mul_for_src(&alu->src[0], alu->def.num_components, swizzle, negate, abs); *negate = false; *abs = true; @@ -106,7 +106,7 @@ get_mul_for_src(nir_alu_src *src, unsigned num_components, * operations. This prevents us from being too aggressive with our * fusing which can actually lead to more instructions. */ - if (!are_all_uses_fadd(&alu->dest.dest.ssa)) + if (!are_all_uses_fadd(&alu->def)) return NULL; break; @@ -188,7 +188,7 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b, abs = false; mul = get_mul_for_src(&add->src[add_mul_src], - add->dest.dest.ssa.num_components, + add->def.num_components, swizzle, &negate, &abs); if (mul != NULL) @@ -198,7 +198,7 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b, if (mul == NULL) return false; - unsigned bit_size = add->dest.dest.ssa.bit_size; + unsigned bit_size = add->def.bit_size; nir_def *mul_src[2]; mul_src[0] = mul->src[0].src.ssa; @@ -227,17 +227,17 @@ brw_nir_opt_peephole_ffma_instr(nir_builder *b, for (unsigned i = 0; i < 2; i++) { ffma->src[i].src = nir_src_for_ssa(mul_src[i]); - for (unsigned j = 0; j < add->dest.dest.ssa.num_components; j++) + for (unsigned j = 0; j < add->def.num_components; j++) ffma->src[i].swizzle[j] = mul->src[i].swizzle[swizzle[j]]; } nir_alu_src_copy(&ffma->src[2], &add->src[1 - add_mul_src], ffma); - nir_def_init(&ffma->instr, &ffma->dest.dest.ssa, - add->dest.dest.ssa.num_components, bit_size); - nir_def_rewrite_uses(&add->dest.dest.ssa, &ffma->dest.dest.ssa); + nir_def_init(&ffma->instr, &ffma->def, + add->def.num_components, bit_size); + nir_def_rewrite_uses(&add->def, &ffma->def); nir_builder_instr_insert(b, &ffma->instr); - assert(list_is_empty(&add->dest.dest.ssa.uses)); + assert(list_is_empty(&add->def.uses)); nir_instr_remove(&add->instr); return true; diff --git a/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c b/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c index a2a1c20..89a20d6 100644 --- a/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c +++ b/src/intel/compiler/brw_nir_opt_peephole_imul32x16.c @@ -45,11 +45,11 @@ replace_imul_instr(nir_builder *b, nir_alu_instr *imul, unsigned small_val, nir_alu_src_copy(&imul_32x16->src[0], &imul->src[1 - small_val], imul_32x16); nir_alu_src_copy(&imul_32x16->src[1], &imul->src[small_val], imul_32x16); - nir_def_init(&imul_32x16->instr, &imul_32x16->dest.dest.ssa, - imul->dest.dest.ssa.num_components, 32); + nir_def_init(&imul_32x16->instr, &imul_32x16->def, + imul->def.num_components, 32); - nir_def_rewrite_uses(&imul->dest.dest.ssa, - &imul_32x16->dest.dest.ssa); + nir_def_rewrite_uses(&imul->def, + &imul_32x16->def); nir_builder_instr_insert(b, &imul_32x16->instr); @@ -198,7 +198,7 @@ brw_nir_opt_peephole_imul32x16_instr(nir_builder *b, if (imul->op != nir_op_imul) return false; - if (imul->dest.dest.ssa.bit_size != 32) + if (imul->def.bit_size != 32) return false; nir_op new_opcode = nir_num_opcodes; @@ -211,7 +211,7 @@ brw_nir_opt_peephole_imul32x16_instr(nir_builder *b, int64_t lo = INT64_MAX; int64_t hi = INT64_MIN; - for (unsigned comp = 0; comp < imul->dest.dest.ssa.num_components; comp++) { + for (unsigned comp = 0; comp < imul->def.num_components; comp++) { int64_t v = nir_src_comp_as_int(imul->src[i].src, comp); if (v < lo) @@ -235,10 +235,10 @@ brw_nir_opt_peephole_imul32x16_instr(nir_builder *b, return true; } - if (imul->dest.dest.ssa.num_components > 1) + if (imul->def.num_components > 1) return false; - const nir_scalar imul_scalar = { &imul->dest.dest.ssa, 0 }; + const nir_scalar imul_scalar = { &imul->def, 0 }; int idx = -1; enum root_operation prev_root = invalid_root; diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 8f9c961..336c0f8 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1082,9 +1082,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) vec4_instruction *inst; nir_alu_type dst_type = (nir_alu_type) (nir_op_infos[instr->op].output_type | - instr->dest.dest.ssa.bit_size); - dst_reg dst = get_nir_def(instr->dest.dest.ssa, dst_type); - dst.writemask &= nir_component_mask(instr->dest.dest.ssa.num_components); + instr->def.bit_size); + dst_reg dst = get_nir_def(instr->def, dst_type); + dst.writemask &= nir_component_mask(instr->def.num_components); src_reg op[4]; for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { @@ -1153,7 +1153,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_iadd: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); FALLTHROUGH; case nir_op_fadd: try_immediate_source(instr, op, true); @@ -1161,7 +1161,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_uadd_sat: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); inst = emit(ADD(dst, op[0], op[1])); inst->saturate = true; break; @@ -1172,7 +1172,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_imul: { - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); /* For integer multiplication, the MUL uses the low 16 bits of one of * the operands (src0 through SNB, src1 on IVB and later). The MACH @@ -1206,7 +1206,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_imul_high: case nir_op_umul_high: { - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); struct brw_reg acc = retype(brw_acc_reg(8), dst.type); emit(MUL(acc, op[0], op[1])); @@ -1236,7 +1236,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_idiv: case nir_op_udiv: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit_math(SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]); break; @@ -1246,7 +1246,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) * appears that our hardware just does the right thing for signed * remainder. */ - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]); break; @@ -1297,7 +1297,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_uadd_carry: { - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD); emit(ADDC(dst_null_ud(), op[0], op[1])); @@ -1306,7 +1306,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } case nir_op_usub_borrow: { - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD); emit(SUBB(dst_null_ud(), op[0], op[1])); @@ -1379,7 +1379,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_imin: case nir_op_umin: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); FALLTHROUGH; case nir_op_fmin: try_immediate_source(instr, op, true); @@ -1388,7 +1388,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_imax: case nir_op_umax: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); FALLTHROUGH; case nir_op_fmax: try_immediate_source(instr, op, true); @@ -1409,7 +1409,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_uge32: case nir_op_ieq32: case nir_op_ine32: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); FALLTHROUGH; case nir_op_flt32: case nir_op_fge32: @@ -1444,7 +1444,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_b32all_iequal2: case nir_op_b32all_iequal3: case nir_op_b32all_iequal4: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); FALLTHROUGH; case nir_op_b32all_fequal2: case nir_op_b32all_fequal3: @@ -1463,7 +1463,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_b32any_inequal2: case nir_op_b32any_inequal3: case nir_op_b32any_inequal4: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); FALLTHROUGH; case nir_op_b32any_fnequal2: case nir_op_b32any_fnequal3: @@ -1481,24 +1481,24 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } case nir_op_inot: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit(NOT(dst, op[0])); break; case nir_op_ixor: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); try_immediate_source(instr, op, true); emit(XOR(dst, op[0], op[1])); break; case nir_op_ior: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); try_immediate_source(instr, op, true); emit(OR(dst, op[0], op[1])); break; case nir_op_iand: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); try_immediate_source(instr, op, true); emit(AND(dst, op[0], op[1])); break; @@ -1506,7 +1506,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) case nir_op_b2i32: case nir_op_b2f32: case nir_op_b2f64: - if (instr->dest.dest.ssa.bit_size > 32) { + if (instr->def.bit_size > 32) { assert(dst.type == BRW_REGISTER_TYPE_DF); emit_conversion_to_double(dst, negate(op[0])); } else { @@ -1584,39 +1584,39 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_unpack_unorm_4x8: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit_unpack_unorm_4x8(dst, op[0]); break; case nir_op_pack_unorm_4x8: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit_pack_unorm_4x8(dst, op[0]); break; case nir_op_unpack_snorm_4x8: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit_unpack_snorm_4x8(dst, op[0]); break; case nir_op_pack_snorm_4x8: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit_pack_snorm_4x8(dst, op[0]); break; case nir_op_bitfield_reverse: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); emit(BFREV(dst, op[0])); break; case nir_op_bit_count: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) < 64); emit(CBIT(dst, op[0])); break; case nir_op_ifind_msb: { - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); @@ -1639,13 +1639,13 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } case nir_op_uclz: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); emit(LZD(dst, op[0])); break; case nir_op_find_lsb: - assert(instr->dest.dest.ssa.bit_size == 32); + assert(instr->def.bit_size == 32); assert(nir_src_bit_size(instr->src[0].src) == 32); assert(devinfo->ver >= 7); emit(FBL(dst, op[0])); @@ -1656,7 +1656,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) unreachable("should have been lowered"); case nir_op_ubfe: case nir_op_ibfe: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); op[0] = fix_3src_operand(op[0]); op[1] = fix_3src_operand(op[1]); op[2] = fix_3src_operand(op[2]); @@ -1665,12 +1665,12 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_bfm: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); emit(BFI1(dst, op[0], op[1])); break; case nir_op_bfi: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); op[0] = fix_3src_operand(op[0]); op[1] = fix_3src_operand(op[1]); op[2] = fix_3src_operand(op[2]); @@ -1733,19 +1733,19 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) break; case nir_op_ishl: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); try_immediate_source(instr, op, false); emit(SHL(dst, op[0], op[1])); break; case nir_op_ishr: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); try_immediate_source(instr, op, false); emit(ASR(dst, op[0], op[1])); break; case nir_op_ushr: - assert(instr->dest.dest.ssa.bit_size < 64); + assert(instr->def.bit_size < 64); try_immediate_source(instr, op, false); emit(SHR(dst, op[0], op[1])); break; diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c index 1835768..573f52b 100644 --- a/src/mesa/program/prog_to_nir.c +++ b/src/mesa/program/prog_to_nir.c @@ -178,12 +178,12 @@ ptn_get_src(struct ptn_compile *c, const struct prog_src_register *prog_src) } else { assert(swizzle != SWIZZLE_NIL); nir_alu_instr *mov = nir_alu_instr_create(b->shader, nir_op_mov); - nir_def_init(&mov->instr, &mov->dest.dest.ssa, 1, 32); + nir_def_init(&mov->instr, &mov->def, 1, 32); mov->src[0] = src; mov->src[0].swizzle[0] = swizzle; nir_builder_instr_insert(b, &mov->instr); - chans[i] = &mov->dest.dest.ssa; + chans[i] = &mov->def; } if (prog_src->Negate & (1 << i)) diff --git a/src/microsoft/clc/clc_compiler.c b/src/microsoft/clc/clc_compiler.c index 1155344..aa95baa 100644 --- a/src/microsoft/clc/clc_compiler.c +++ b/src/microsoft/clc/clc_compiler.c @@ -577,7 +577,7 @@ static bool shader_has_double(nir_shader *nir) const nir_op_info *info = &nir_op_infos[alu->op]; if (info->output_type & nir_type_float && - alu->dest.dest.ssa.bit_size == 64) + alu->def.bit_size == 64) return true; } } diff --git a/src/microsoft/compiler/dxil_nir.c b/src/microsoft/compiler/dxil_nir.c index d436cbe..1c36355 100644 --- a/src/microsoft/compiler/dxil_nir.c +++ b/src/microsoft/compiler/dxil_nir.c @@ -1047,7 +1047,7 @@ dxil_nir_lower_double_math_instr(nir_builder *b, alu->src[i].src.ssa->bit_size == 64) { unsigned num_components = nir_op_infos[alu->op].input_sizes[i]; if (!num_components) - num_components = alu->dest.dest.ssa.num_components; + num_components = alu->def.num_components; nir_def *components[NIR_MAX_VEC_COMPONENTS]; for (unsigned c = 0; c < num_components; ++c) { nir_def *packed_double = nir_channel(b, alu->src[i].src.ssa, alu->src[i].swizzle[c]); @@ -1061,16 +1061,16 @@ dxil_nir_lower_double_math_instr(nir_builder *b, } if (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) == nir_type_float && - alu->dest.dest.ssa.bit_size == 64) { + alu->def.bit_size == 64) { b->cursor = nir_after_instr(&alu->instr); nir_def *components[NIR_MAX_VEC_COMPONENTS]; - for (unsigned c = 0; c < alu->dest.dest.ssa.num_components; ++c) { - nir_def *packed_double = nir_channel(b, &alu->dest.dest.ssa, c); + for (unsigned c = 0; c < alu->def.num_components; ++c) { + nir_def *packed_double = nir_channel(b, &alu->def, c); nir_def *unpacked_double = nir_unpack_double_2x32_dxil(b, packed_double); components[c] = nir_pack_64_2x32(b, unpacked_double); } - nir_def *repacked_dvec = nir_vec(b, components, alu->dest.dest.ssa.num_components); - nir_def_rewrite_uses_after(&alu->dest.dest.ssa, repacked_dvec, repacked_dvec->parent_instr); + nir_def *repacked_dvec = nir_vec(b, components, alu->def.num_components); + nir_def_rewrite_uses_after(&alu->def, repacked_dvec, repacked_dvec->parent_instr); progress = true; } diff --git a/src/microsoft/compiler/nir_to_dxil.c b/src/microsoft/compiler/nir_to_dxil.c index 51a182e..2c1ae59 100644 --- a/src/microsoft/compiler/nir_to_dxil.c +++ b/src/microsoft/compiler/nir_to_dxil.c @@ -2176,7 +2176,7 @@ static void store_alu_dest(struct ntd_context *ctx, nir_alu_instr *alu, unsigned chan, const struct dxil_value *value) { - store_def(ctx, &alu->dest.dest.ssa, chan, value); + store_def(ctx, &alu->def, chan, value); } static const struct dxil_value * @@ -2291,7 +2291,7 @@ emit_shift(struct ntd_context *ctx, nir_alu_instr *alu, 0); } else { uint64_t val = nir_scalar_as_uint( - nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->dest.dest.ssa, 0), 1)); + nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->def, 0), 1)); op1 = dxil_module_get_int_const(&ctx->mod, val & shift_mask, op0_bit_size); } @@ -2318,7 +2318,7 @@ emit_cmp(struct ntd_context *ctx, nir_alu_instr *alu, static enum dxil_cast_opcode get_cast_op(nir_alu_instr *alu) { - unsigned dst_bits = alu->dest.dest.ssa.bit_size; + unsigned dst_bits = alu->def.bit_size; unsigned src_bits = nir_src_bit_size(alu->src[0].src); switch (alu->op) { @@ -2399,7 +2399,7 @@ get_cast_op(nir_alu_instr *alu) static const struct dxil_type * get_cast_dest_type(struct ntd_context *ctx, nir_alu_instr *alu) { - unsigned dst_bits = alu->dest.dest.ssa.bit_size; + unsigned dst_bits = alu->def.bit_size; switch (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type)) { case nir_type_bool: assert(dst_bits == 1); @@ -2436,7 +2436,7 @@ emit_cast(struct ntd_context *ctx, nir_alu_instr *alu, switch (opcode) { case DXIL_CAST_UITOFP: case DXIL_CAST_SITOFP: - if (is_double(info->output_type, alu->dest.dest.ssa.bit_size)) + if (is_double(info->output_type, alu->def.bit_size)) ctx->mod.feats.dx11_1_double_extensions = true; break; case DXIL_CAST_FPTOUI: @@ -2448,7 +2448,7 @@ emit_cast(struct ntd_context *ctx, nir_alu_instr *alu, break; } - if (alu->dest.dest.ssa.bit_size == 16) { + if (alu->def.bit_size == 16) { switch (alu->op) { case nir_op_f2fmp: case nir_op_i2imp: @@ -2540,7 +2540,7 @@ emit_binary_intin(struct ntd_context *ctx, nir_alu_instr *alu, const nir_op_info *info = &nir_op_infos[alu->op]; assert(info->output_type == info->input_types[0]); assert(info->output_type == info->input_types[1]); - unsigned dst_bits = alu->dest.dest.ssa.bit_size; + unsigned dst_bits = alu->def.bit_size; assert(nir_src_bit_size(alu->src[0].src) == dst_bits); assert(nir_src_bit_size(alu->src[1].src) == dst_bits); enum overload_type overload = get_overload(info->output_type, dst_bits); @@ -2561,7 +2561,7 @@ emit_tertiary_intin(struct ntd_context *ctx, nir_alu_instr *alu, const struct dxil_value *op2) { const nir_op_info *info = &nir_op_infos[alu->op]; - unsigned dst_bits = alu->dest.dest.ssa.bit_size; + unsigned dst_bits = alu->def.bit_size; assert(nir_src_bit_size(alu->src[0].src) == dst_bits); assert(nir_src_bit_size(alu->src[1].src) == dst_bits); assert(nir_src_bit_size(alu->src[2].src) == dst_bits); @@ -2796,7 +2796,7 @@ emit_make_double(struct ntd_context *ctx, nir_alu_instr *alu) const struct dxil_value *v = dxil_emit_call(&ctx->mod, func, args, ARRAY_SIZE(args)); if (!v) return false; - store_def(ctx, &alu->dest.dest.ssa, 0, v); + store_def(ctx, &alu->def, 0, v); return true; } @@ -2827,8 +2827,8 @@ emit_split_double(struct ntd_context *ctx, nir_alu_instr *alu) if (!hi || !lo) return false; - store_def(ctx, &alu->dest.dest.ssa, 0, hi); - store_def(ctx, &alu->dest.dest.ssa, 1, lo); + store_def(ctx, &alu->def, 0, hi); + store_def(ctx, &alu->def, 1, lo); return true; } @@ -2846,8 +2846,8 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu) case nir_op_vec16: return emit_vec(ctx, alu, nir_op_infos[alu->op].num_inputs); case nir_op_mov: { - assert(alu->dest.dest.ssa.num_components == 1); - store_ssa_def(ctx, &alu->dest.dest.ssa, 0, get_src_ssa(ctx, + assert(alu->def.num_components == 1); + store_ssa_def(ctx, &alu->def, 0, get_src_ssa(ctx, alu->src->src.ssa, alu->src->swizzle[0])); return true; } @@ -2890,7 +2890,7 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu) case nir_op_fmul: return emit_binop(ctx, alu, DXIL_BINOP_MUL, src[0], src[1]); case nir_op_fdiv: - if (alu->dest.dest.ssa.bit_size == 64) + if (alu->def.bit_size == 64) ctx->mod.feats.dx11_1_double_extensions = 1; return emit_binop(ctx, alu, DXIL_BINOP_SDIV, src[0], src[1]); @@ -2898,10 +2898,10 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu) case nir_op_udiv: if (nir_src_is_const(alu->src[1].src)) { /* It's illegal to emit a literal divide by 0 in DXIL */ - nir_scalar divisor = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->dest.dest.ssa, 0), 1); + nir_scalar divisor = nir_scalar_chase_alu_src(nir_get_ssa_scalar(&alu->def, 0), 1); if (nir_scalar_as_int(divisor) == 0) { store_alu_dest(ctx, alu, 0, - dxil_module_get_int_const(&ctx->mod, 0, alu->dest.dest.ssa.bit_size)); + dxil_module_get_int_const(&ctx->mod, 0, alu->def.bit_size)); return true; } } @@ -2917,7 +2917,7 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu) case nir_op_ior: return emit_binop(ctx, alu, DXIL_BINOP_OR, src[0], src[1]); case nir_op_ixor: return emit_binop(ctx, alu, DXIL_BINOP_XOR, src[0], src[1]); case nir_op_inot: { - unsigned bit_size = alu->dest.dest.ssa.bit_size; + unsigned bit_size = alu->def.bit_size; intmax_t val = bit_size == 1 ? 1 : -1; const struct dxil_value *negative_one = dxil_module_get_int_const(&ctx->mod, val, bit_size); return emit_binop(ctx, alu, DXIL_BINOP_XOR, src[0], negative_one); @@ -2954,7 +2954,7 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu) case nir_op_fround_even: return emit_unary_intin(ctx, alu, DXIL_INTR_ROUND_NE, src[0]); case nir_op_frcp: { const struct dxil_value *one; - switch (alu->dest.dest.ssa.bit_size) { + switch (alu->def.bit_size) { case 16: one = dxil_module_get_float16_const(&ctx->mod, 0x3C00); break; @@ -2983,7 +2983,7 @@ emit_alu(struct ntd_context *ctx, nir_alu_instr *alu) case nir_op_fmax: return emit_binary_intin(ctx, alu, DXIL_INTR_FMAX, src[0], src[1]); case nir_op_fmin: return emit_binary_intin(ctx, alu, DXIL_INTR_FMIN, src[0], src[1]); case nir_op_ffma: - if (alu->dest.dest.ssa.bit_size == 64) + if (alu->def.bit_size == 64) ctx->mod.feats.dx11_1_double_extensions = 1; return emit_tertiary_intin(ctx, alu, DXIL_INTR_FMA, src[0], src[1], src[2]); diff --git a/src/nouveau/codegen/nv50_ir_from_nir.cpp b/src/nouveau/codegen/nv50_ir_from_nir.cpp index fae2aaf..0c5ef4c 100644 --- a/src/nouveau/codegen/nv50_ir_from_nir.cpp +++ b/src/nouveau/codegen/nv50_ir_from_nir.cpp @@ -254,7 +254,7 @@ Converter::isResultSigned(nir_op op) DataType Converter::getDType(nir_alu_instr *insn) { - return getDType(insn->op, insn->dest.dest.ssa.bit_size); + return getDType(insn->op, insn->def.bit_size); } DataType @@ -2433,7 +2433,7 @@ Converter::visit(nir_load_const_instr *insn) } #define DEFAULT_CHECKS \ - if (insn->dest.dest.ssa.num_components > 1) { \ + if (insn->def.num_components > 1) { \ ERROR("nir_alu_instr only supported with 1 component!\n"); \ return false; \ } @@ -2503,7 +2503,7 @@ Converter::visit(nir_alu_instr *insn) case nir_op_ishl: case nir_op_ixor: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); operation preOp = preOperationNeeded(op); if (preOp != OP_NOP) { assert(info.num_inputs < 2); @@ -2540,14 +2540,14 @@ Converter::visit(nir_alu_instr *insn) case nir_op_ifind_msb: case nir_op_ufind_msb: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); dType = sTypes[0]; mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0])); break; } case nir_op_fround_even: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkCvt(OP_CVT, dType, newDefs[0], dType, getSrc(&insn->src[0]))->rnd = ROUND_NI; break; } @@ -2575,7 +2575,7 @@ Converter::visit(nir_alu_instr *insn) case nir_op_u2f64: case nir_op_u2u64: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); DataType stype = sTypes[0]; Instruction *i = mkOp1(getOperation(op), dType, newDefs[0], getSrc(&insn->src[0])); if (::isFloatType(stype) && isIntType(dType)) @@ -2607,7 +2607,7 @@ Converter::visit(nir_alu_instr *insn) case nir_op_fneu32: case nir_op_ine32: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Instruction *i = mkCmp(getOperation(op), getCondCode(op), dType, @@ -2621,7 +2621,7 @@ Converter::visit(nir_alu_instr *insn) break; } case nir_op_mov: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); for (LValues::size_type c = 0u; c < newDefs.size(); ++c) { mkMov(newDefs[c], getSrc(&insn->src[0], c), dType); } @@ -2632,7 +2632,7 @@ Converter::visit(nir_alu_instr *insn) case nir_op_vec4: case nir_op_vec8: case nir_op_vec16: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); for (LValues::size_type c = 0u; c < newDefs.size(); ++c) { mkMov(newDefs[c], getSrc(&insn->src[c]), dType); } @@ -2640,14 +2640,14 @@ Converter::visit(nir_alu_instr *insn) } // (un)pack case nir_op_pack_64_2x32: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Instruction *merge = mkOp(OP_MERGE, dType, newDefs[0]); merge->setSrc(0, getSrc(&insn->src[0], 0)); merge->setSrc(1, getSrc(&insn->src[0], 1)); break; } case nir_op_pack_half_2x16_split: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *tmpH = getSSA(); Value *tmpL = getSSA(); @@ -2658,24 +2658,24 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_unpack_half_2x16_split_x: case nir_op_unpack_half_2x16_split_y: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Instruction *cvt = mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, getSrc(&insn->src[0])); if (op == nir_op_unpack_half_2x16_split_y) cvt->subOp = 1; break; } case nir_op_unpack_64_2x32: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, newDefs[1]); break; } case nir_op_unpack_64_2x32_split_x: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp1(OP_SPLIT, dType, newDefs[0], getSrc(&insn->src[0]))->setDef(1, getSSA()); break; } case nir_op_unpack_64_2x32_split_y: { - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp1(OP_SPLIT, dType, getSSA(), getSrc(&insn->src[0]))->setDef(1, newDefs[0]); break; } @@ -2689,7 +2689,7 @@ Converter::visit(nir_alu_instr *insn) else iType = TYPE_S32; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); LValue *val0 = getScratch(); LValue *val1 = getScratch(); mkCmp(OP_SET, CC_GT, iType, val0, dType, getSrc(&insn->src[0]), zero); @@ -2711,7 +2711,7 @@ Converter::visit(nir_alu_instr *insn) case nir_op_fcsel: case nir_op_b32csel: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkCmp(OP_SLCT, CC_NE, dType, newDefs[0], sTypes[0], getSrc(&insn->src[1]), getSrc(&insn->src[2]), getSrc(&insn->src[0])); break; } @@ -2719,20 +2719,20 @@ Converter::visit(nir_alu_instr *insn) case nir_op_ubitfield_extract: { DEFAULT_CHECKS; Value *tmp = getSSA(); - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp3(OP_INSBF, dType, tmp, getSrc(&insn->src[2]), loadImm(NULL, 0x808), getSrc(&insn->src[1])); mkOp2(OP_EXTBF, dType, newDefs[0], getSrc(&insn->src[0]), tmp); break; } case nir_op_bfm: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp2(OP_BMSK, dType, newDefs[0], getSrc(&insn->src[1]), getSrc(&insn->src[0]))->subOp = NV50_IR_SUBOP_BMSK_W; break; } case nir_op_bitfield_insert: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); LValue *temp = getSSA(); mkOp3(OP_INSBF, TYPE_U32, temp, getSrc(&insn->src[3]), mkImm(0x808), getSrc(&insn->src[2])); mkOp3(OP_INSBF, dType, newDefs[0], getSrc(&insn->src[1]), temp, getSrc(&insn->src[0])); @@ -2740,19 +2740,19 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_bit_count: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp2(OP_POPCNT, dType, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[0])); break; } case nir_op_bitfield_reverse: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp1(OP_BREV, TYPE_U32, newDefs[0], getSrc(&insn->src[0])); break; } case nir_op_find_lsb: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *tmp = getSSA(); mkOp1(OP_BREV, TYPE_U32, tmp, getSrc(&insn->src[0])); mkOp1(OP_BFIND, TYPE_U32, newDefs[0], tmp)->subOp = NV50_IR_SUBOP_BFIND_SAMT; @@ -2760,7 +2760,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_extract_u8: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *prmt = getSSA(); mkOp2(OP_OR, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x4440)); mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0)); @@ -2768,7 +2768,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_extract_i8: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *prmt = getSSA(); mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x1111), loadImm(NULL, 0x8880)); mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0)); @@ -2776,7 +2776,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_extract_u16: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *prmt = getSSA(); mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x22), loadImm(NULL, 0x4410)); mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0)); @@ -2784,7 +2784,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_extract_i16: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *prmt = getSSA(); mkOp3(OP_MAD, TYPE_U32, prmt, getSrc(&insn->src[1]), loadImm(NULL, 0x2222), loadImm(NULL, 0x9910)); mkOp3(OP_PERMT, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), prmt, loadImm(NULL, 0)); @@ -2792,7 +2792,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_fquantize2f16: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *tmp = getSSA(); mkCvt(OP_CVT, TYPE_F16, tmp, TYPE_F32, getSrc(&insn->src[0]))->ftz = 1; mkCvt(OP_CVT, TYPE_F32, newDefs[0], TYPE_F16, tmp); @@ -2800,7 +2800,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_urol: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp3(OP_SHF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[1]), getSrc(&insn->src[0])) ->subOp = NV50_IR_SUBOP_SHF_L | @@ -2810,7 +2810,7 @@ Converter::visit(nir_alu_instr *insn) } case nir_op_uror: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp3(OP_SHF, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), getSrc(&insn->src[1]), getSrc(&insn->src[0])) ->subOp = NV50_IR_SUBOP_SHF_R | @@ -2821,13 +2821,13 @@ Converter::visit(nir_alu_instr *insn) // boolean conversions case nir_op_b2f32: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1.0f)); break; } case nir_op_b2f64: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); Value *tmp = getSSA(4); mkOp2(OP_AND, TYPE_U32, tmp, getSrc(&insn->src[0]), loadImm(NULL, 0x3ff00000)); mkOp2(OP_MERGE, TYPE_U64, newDefs[0], loadImm(NULL, 0), tmp); @@ -2837,13 +2837,13 @@ Converter::visit(nir_alu_instr *insn) case nir_op_b2i16: case nir_op_b2i32: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); mkOp2(OP_AND, TYPE_U32, newDefs[0], getSrc(&insn->src[0]), loadImm(NULL, 1)); break; } case nir_op_b2i64: { DEFAULT_CHECKS; - LValues &newDefs = convert(&insn->dest.dest.ssa); + LValues &newDefs = convert(&insn->def); LValue *def = getScratch(); mkOp2(OP_AND, TYPE_U32, def, getSrc(&insn->src[0]), loadImm(NULL, 1)); mkOp2(OP_MERGE, TYPE_S64, newDefs[0], def, loadImm(NULL, 0)); diff --git a/src/panfrost/compiler/bifrost_compile.c b/src/panfrost/compiler/bifrost_compile.c index 13ba53b..7ab2ef3 100644 --- a/src/panfrost/compiler/bifrost_compile.c +++ b/src/panfrost/compiler/bifrost_compile.c @@ -2093,10 +2093,10 @@ bi_nir_is_replicated(nir_alu_src *src) static void bi_emit_alu(bi_builder *b, nir_alu_instr *instr) { - bi_index dst = bi_def_index(&instr->dest.dest.ssa); + bi_index dst = bi_def_index(&instr->def); unsigned srcs = nir_op_infos[instr->op].num_inputs; - unsigned sz = instr->dest.dest.ssa.bit_size; - unsigned comps = instr->dest.dest.ssa.num_components; + unsigned sz = instr->def.bit_size; + unsigned comps = instr->def.num_components; unsigned src_sz = srcs > 0 ? nir_src_bit_size(instr->src[0].src) : 0; /* Indicate scalarness */ @@ -4230,7 +4230,7 @@ bi_vectorize_filter(const nir_instr *instr, const void *data) } /* Vectorized instructions cannot write more than 32-bit */ - int dst_bit_size = alu->dest.dest.ssa.bit_size; + int dst_bit_size = alu->def.bit_size; if (dst_bit_size == 16) return 2; else diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 30a498c..50c8010 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -286,7 +286,7 @@ mdg_should_scalarize(const nir_instr *instr, const void *_unused) if (nir_src_bit_size(alu->src[0].src) == 64) return true; - if (alu->dest.dest.ssa.bit_size == 64) + if (alu->def.bit_size == 64) return true; switch (alu->op) { @@ -319,7 +319,7 @@ midgard_vectorize_filter(const nir_instr *instr, const void *data) const nir_alu_instr *alu = nir_instr_as_alu(instr); int src_bit_size = nir_src_bit_size(alu->src[0].src); - int dst_bit_size = alu->dest.dest.ssa.bit_size; + int dst_bit_size = alu->def.bit_size; if (src_bit_size == 64 || dst_bit_size == 64) return 2; @@ -632,7 +632,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) return; } - unsigned nr_components = instr->dest.dest.ssa.num_components; + unsigned nr_components = instr->def.num_components; unsigned nr_inputs = nir_op_infos[instr->op].num_inputs; unsigned op = 0; @@ -647,7 +647,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) bool flip_src12 = false; ASSERTED unsigned src_bitsize = nir_src_bit_size(instr->src[0].src); - unsigned dst_bitsize = instr->dest.dest.ssa.bit_size; + unsigned dst_bitsize = instr->def.bit_size; enum midgard_roundmode roundmode = MIDGARD_RTE; @@ -875,7 +875,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) .roundmode = roundmode, }; - ins.dest = nir_def_index_with_mask(&instr->dest.dest.ssa, &ins.mask); + ins.dest = nir_def_index_with_mask(&instr->def, &ins.mask); for (unsigned i = nr_inputs; i < ARRAY_SIZE(ins.src); ++i) ins.src[i] = ~0; diff --git a/src/panfrost/midgard/midgard_derivatives.c b/src/panfrost/midgard/midgard_derivatives.c index fc0c1e6..858df71 100644 --- a/src/panfrost/midgard/midgard_derivatives.c +++ b/src/panfrost/midgard/midgard_derivatives.c @@ -122,7 +122,7 @@ midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr) }, }; - ins.dest = nir_def_index_with_mask(&instr->dest.dest.ssa, &ins.mask); + ins.dest = nir_def_index_with_mask(&instr->def, &ins.mask); emit_mir_instruction(ctx, ins); } diff --git a/src/panfrost/midgard/midgard_nir_type_csel.c b/src/panfrost/midgard/midgard_nir_type_csel.c index e2cd8c6..dbf9426 100644 --- a/src/panfrost/midgard/midgard_nir_type_csel.c +++ b/src/panfrost/midgard/midgard_nir_type_csel.c @@ -19,7 +19,7 @@ pass(nir_builder *b, nir_instr *instr, void *data) return false; BITSET_WORD *float_types = data; - if (BITSET_TEST(float_types, alu->dest.dest.ssa.index)) { + if (BITSET_TEST(float_types, alu->def.index)) { alu->op = nir_op_b32fcsel_mdg; return true; } else { -- 2.7.4