From 6c0b70e7740b30ee46ae28f6b3b7fe7223621ebd Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 29 Dec 2011 23:26:48 -0800 Subject: [PATCH] i965/gen7: Fix up the transform feedback buffer pointers on later batches. Fixes piglit EXT_transform_feedback/intervening-read Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_vtbl.c | 6 ++++++ src/mesa/drivers/dri/i965/gen6_sol.c | 1 + src/mesa/drivers/dri/i965/gen7_sol_state.c | 13 ++++++++++--- 4 files changed, 18 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 873e172..9f9b113 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -988,6 +988,7 @@ struct brw_context struct brw_sol_state { uint32_t svbi_0_starting_index; uint32_t svbi_0_max_index; + uint32_t offset_0_batch_start; uint32_t primitives_generated; uint32_t primitives_written; } sol; diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index d348806..be975d1 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -177,6 +177,12 @@ static void brw_new_batch( struct intel_context *intel ) brw->state_batch_count = 0; + /* Gen7 needs to track what the real transform feedback vertex count was at + * the start of the batch, since the kernel will be resetting the offset to + * 0. + */ + brw->sol.offset_0_batch_start = brw->sol.svbi_0_starting_index; + brw->vb.nr_current_buffers = 0; brw->ib.type = -1; diff --git a/src/mesa/drivers/dri/i965/gen6_sol.c b/src/mesa/drivers/dri/i965/gen6_sol.c index f724802..41923b7 100644 --- a/src/mesa/drivers/dri/i965/gen6_sol.c +++ b/src/mesa/drivers/dri/i965/gen6_sol.c @@ -132,6 +132,7 @@ brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, brw->state.dirty.brw |= BRW_NEW_SOL_INDICES; brw->sol.svbi_0_starting_index = 0; brw->sol.svbi_0_max_index = max_index; + brw->sol.offset_0_batch_start = 0; } void diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c b/src/mesa/drivers/dri/i965/gen7_sol_state.c index 81ffc0e..04783ec 100644 --- a/src/mesa/drivers/dri/i965/gen7_sol_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c @@ -56,6 +56,7 @@ upload_3dstate_so_buffers(struct brw_context *brw) struct gl_buffer_object *bufferobj = xfb_obj->Buffers[i]; drm_intel_bo *bo; uint32_t start, end; + uint32_t stride; if (!xfb_obj->Buffers[i]) { /* The pitch of 0 in this command indicates that the buffer is @@ -72,17 +73,23 @@ upload_3dstate_so_buffers(struct brw_context *brw) } bo = intel_buffer_object(bufferobj)->buffer; + stride = linked_xfb_info->BufferStride[i] * 4; start = xfb_obj->Offset[i]; assert(start % 4 == 0); end = ALIGN(start + xfb_obj->Size[i], 4); assert(end <= bo->size); + /* Offset the starting offset by the current vertex index into the + * feedback buffer, offset register is always set to 0 at the start of the + * batchbuffer. + */ + start += brw->sol.offset_0_batch_start * stride; + assert(start <= end); + BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_SO_BUFFER << 16 | (4 - 2)); - OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | - ((linked_xfb_info->BufferStride[i] * 4) << - SO_BUFFER_PITCH_SHIFT)); + OUT_BATCH((i << SO_BUFFER_INDEX_SHIFT) | stride); OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, start); OUT_RELOC(bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, end); ADVANCE_BATCH(); -- 2.7.4