From 6c06ad34eda9e1990313ff80999e1a75a02fa1c0 Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Fri, 1 Jul 2022 17:32:41 +0800 Subject: [PATCH] ASoC: dt-bindings: fsl-sai: Add two PLL clock source Add two PLL clock source, they are the parent clocks of root clock one is for 8kHz series rates, another one is for 11kHz series rates. They are optional clocks, if there are such clocks, then driver can switch between them for supporting more accurate rates. Signed-off-by: Shengjiu Wang Acked-by: Rob Herring Link: https://lore.kernel.org/r/1656667961-1799-7-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 4c66e6a..fbdefc3 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -21,6 +21,9 @@ Required properties: - clock-names : Must include the "bus" for register access and "mclk1", "mclk2", "mclk3" for bit clock and frame clock providing. + "pll8k", "pll11k" are optional, they are the clock + source for root clock, one is for 8kHz series rates + another one is for 11kHz series rates. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt. -- 2.7.4