From 6be41ea4e6ff5aceff152a8480ce1c93427b1247 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Mon, 16 May 2022 16:02:19 +0200 Subject: [PATCH] arm64: zynqmp: zynqmp-sm-k26-revA: Fix DP PLL configuration This patch fixes the DP audio and video PLL configurations for the zynqmp-sm-k26-revA som. The Linux DP driver expects the DP to be using the following PLL config: - DP video PLL should use the VPLL (0x0) - DP audio PLL should use the RPLL (0x3) - DP system time clock PLL should use RPLL (0x3) Register 0xFD1A0070 configures the DP video PLL. Register 0xFD1A0074 configures the DP audio PLL. Register 0xFD1A007C configures the DP system time clock PLL. Signed-off-by: Neal Frager Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/fa7e9abc419c9d7648405d1c62367dbe701d09b8.1652709736.git.michal.simek@amd.com --- board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c index ed02579..e559880 100644 --- a/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c +++ b/board/xilinx/zynqmp/zynqmp-sm-k26-revA/psu_init_gpl.c @@ -74,6 +74,9 @@ static unsigned long psu_clock_init_data(void) psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000A00U); psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); + psu_mask_write(0xFD1A0070, 0x013F3F07U, 0x01010500U); + psu_mask_write(0xFD1A0074, 0x013F3F07U, 0x01013C03U); + psu_mask_write(0xFD1A007C, 0x013F3F07U, 0x01013803U); psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U); -- 2.7.4