From 6ba5cbf3ea2315acf1b7f1c39c6fec6cca5560ca Mon Sep 17 00:00:00 2001 From: =?utf8?q?Milo=C5=A1=20Stojanovi=C4=87?= Date: Thu, 21 Nov 2019 15:17:21 +0100 Subject: [PATCH] [mips] Add a 'generic' Mips CPU Having a generic CPU removes a warning when creating a subtarget without the CPU being explicitly specified. Differential Revision: https://reviews.llvm.org/D70490 --- llvm/lib/Target/Mips/Mips.td | 1 + llvm/test/CodeGen/Mips/cpus.ll | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index a0569ed..b8a6981 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -232,6 +232,7 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", class Proc Features> : ProcessorModel; +def : Proc<"generic", [FeatureMips32]>; def : Proc<"mips1", [FeatureMips1]>; def : Proc<"mips2", [FeatureMips2]>; def : Proc<"mips32", [FeatureMips32]>; diff --git a/llvm/test/CodeGen/Mips/cpus.ll b/llvm/test/CodeGen/Mips/cpus.ll index b8844c4..d937704 100644 --- a/llvm/test/CodeGen/Mips/cpus.ll +++ b/llvm/test/CodeGen/Mips/cpus.ll @@ -1,5 +1,9 @@ ; Check that the CPU names work. +; RUN: llc -mtriple=mips -mcpu=generic -filetype=obj < %s \ +; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=GENERIC +; GENERIC: ISA: MIPS32 + ; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s \ ; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS2 ; MIPS2: ISA: MIPS2 -- 2.7.4