From 6b4d184dc943ba57697dbbc9c05c829fce24ebff Mon Sep 17 00:00:00 2001 From: Daniel Jacobowitz Date: Thu, 21 Sep 2006 21:01:02 +0000 Subject: [PATCH] * sysdeps/mips/fpu_control.h: If soft-float, don't use floating-point registers. * sysdeps/mips/__longjmp.c, sysdeps/mips/setjmp_aux.c, sysdeps/mips/mips64/__longjmp.c, sysdeps/mips/mips64/setjmp_aux.c: Likewise. --- ChangeLog.mips | 8 ++++++++ sysdeps/mips/__longjmp.c | 2 ++ sysdeps/mips/fpu_control.h | 13 +++++++++++++ sysdeps/mips/mips64/__longjmp.c | 2 ++ sysdeps/mips/mips64/setjmp_aux.c | 4 ++++ sysdeps/mips/setjmp_aux.c | 4 ++++ 6 files changed, 33 insertions(+) diff --git a/ChangeLog.mips b/ChangeLog.mips index b3bf090..b849ffa 100644 --- a/ChangeLog.mips +++ b/ChangeLog.mips @@ -1,3 +1,11 @@ +2006-09-21 Joseph Myers + + * sysdeps/mips/fpu_control.h: If soft-float, don't use + floating-point registers. + * sysdeps/mips/__longjmp.c, sysdeps/mips/setjmp_aux.c, + sysdeps/mips/mips64/__longjmp.c, sysdeps/mips/mips64/setjmp_aux.c: + Likewise. + 2006-08-04 Joseph Myers * sysdeps/unix/sysv/linux/mips/nptl/lowlevellock.h (FUTEX_LOCK_PI, diff --git a/sysdeps/mips/__longjmp.c b/sysdeps/mips/__longjmp.c index 750a71f..386c056 100644 --- a/sysdeps/mips/__longjmp.c +++ b/sysdeps/mips/__longjmp.c @@ -37,6 +37,7 @@ __longjmp (env, val_arg) along the way. */ register int val asm ("a1"); +#ifdef __mips_hard_float /* Pull back the floating point callee-saved registers. */ asm volatile ("l.d $f20, %0" : : "m" (env[0].__fpregs[0])); asm volatile ("l.d $f22, %0" : : "m" (env[0].__fpregs[1])); @@ -48,6 +49,7 @@ __longjmp (env, val_arg) /* Get and reconstruct the floating point csr. */ asm volatile ("lw $2, %0" : : "m" (env[0].__fpc_csr)); asm volatile ("ctc1 $2, $31"); +#endif /* Get the GP. */ asm volatile ("lw $gp, %0" : : "m" (env[0].__gp)); diff --git a/sysdeps/mips/fpu_control.h b/sysdeps/mips/fpu_control.h index da18dea..5712ac5 100644 --- a/sysdeps/mips/fpu_control.h +++ b/sysdeps/mips/fpu_control.h @@ -58,6 +58,17 @@ #include +#ifdef __mips_soft_float + +#define _FPU_RESERVED 0xffffffff +#define _FPU_DEFAULT 0x00000000 +typedef unsigned int fpu_control_t; +#define _FPU_GETCW(cw) 0 +#define _FPU_SETCW(cw) do { } while (0) +extern fpu_control_t __fpu_control; + +#else /* __mips_soft_float */ + /* masking of interrupts */ #define _FPU_MASK_V 0x0800 /* Invalid operation */ #define _FPU_MASK_Z 0x0400 /* Division by zero */ @@ -95,4 +106,6 @@ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__))); /* Default control word set at startup. */ extern fpu_control_t __fpu_control; +#endif /* __mips_soft_float */ + #endif /* fpu_control.h */ diff --git a/sysdeps/mips/mips64/__longjmp.c b/sysdeps/mips/mips64/__longjmp.c index 546493f..973b078 100644 --- a/sysdeps/mips/mips64/__longjmp.c +++ b/sysdeps/mips/mips64/__longjmp.c @@ -39,6 +39,7 @@ __longjmp (env, val_arg) along the way. */ register int val asm ("a1"); +#ifdef __mips_hard_float /* Pull back the floating point callee-saved registers. */ #if _MIPS_SIM == _ABI64 asm volatile ("l.d $f24, %0" : : "m" (env[0].__fpregs[0])); @@ -61,6 +62,7 @@ __longjmp (env, val_arg) /* Get and reconstruct the floating point csr. */ asm volatile ("lw $2, %0" : : "m" (env[0].__fpc_csr)); asm volatile ("ctc1 $2, $31"); +#endif /* Get the GP. */ asm volatile ("ld $gp, %0" : : "m" (env[0].__gp)); diff --git a/sysdeps/mips/mips64/setjmp_aux.c b/sysdeps/mips/mips64/setjmp_aux.c index 26b4739..49d0915 100644 --- a/sysdeps/mips/mips64/setjmp_aux.c +++ b/sysdeps/mips/mips64/setjmp_aux.c @@ -29,6 +29,7 @@ int __sigsetjmp_aux (jmp_buf env, int savemask, long long sp, long long fp, long long gp) { +#ifdef __mips_hard_float /* Store the floating point callee-saved registers... */ #if _MIPS_SIM == _ABI64 asm volatile ("s.d $f24, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[0])); @@ -47,6 +48,7 @@ __sigsetjmp_aux (jmp_buf env, int savemask, long long sp, long long fp, asm volatile ("s.d $f28, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[4])); asm volatile ("s.d $f30, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[5])); #endif +#endif /* .. and the PC; */ asm volatile ("sd $31, %0" : : "m" (env[0].__jmpbuf[0].__pc)); @@ -70,8 +72,10 @@ __sigsetjmp_aux (jmp_buf env, int savemask, long long sp, long long fp, asm volatile ("sd $22, %0" : : "m" (env[0].__jmpbuf[0].__regs[6])); asm volatile ("sd $23, %0" : : "m" (env[0].__jmpbuf[0].__regs[7])); +#ifdef __mips_hard_float /* .. and finally get and reconstruct the floating point csr. */ asm ("cfc1 %0, $31" : "=r" (env[0].__jmpbuf[0].__fpc_csr)); +#endif /* Save the signal mask if requested. */ return __sigjmp_save (env, savemask); diff --git a/sysdeps/mips/setjmp_aux.c b/sysdeps/mips/setjmp_aux.c index 7125cc4..269d0fd 100644 --- a/sysdeps/mips/setjmp_aux.c +++ b/sysdeps/mips/setjmp_aux.c @@ -27,6 +27,7 @@ int __sigsetjmp_aux (jmp_buf env, int savemask, int sp, int fp) { +#ifdef __mips_hard_float /* Store the floating point callee-saved registers... */ asm volatile ("s.d $f20, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[0])); asm volatile ("s.d $f22, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[1])); @@ -34,6 +35,7 @@ __sigsetjmp_aux (jmp_buf env, int savemask, int sp, int fp) asm volatile ("s.d $f26, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[3])); asm volatile ("s.d $f28, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[4])); asm volatile ("s.d $f30, %0" : : "m" (env[0].__jmpbuf[0].__fpregs[5])); +#endif /* .. and the PC; */ asm volatile ("sw $31, %0" : : "m" (env[0].__jmpbuf[0].__pc)); @@ -57,8 +59,10 @@ __sigsetjmp_aux (jmp_buf env, int savemask, int sp, int fp) asm volatile ("sw $22, %0" : : "m" (env[0].__jmpbuf[0].__regs[6])); asm volatile ("sw $23, %0" : : "m" (env[0].__jmpbuf[0].__regs[7])); +#ifdef __mips_hard_float /* .. and finally get and reconstruct the floating point csr. */ asm ("cfc1 %0, $31" : "=r" (env[0].__jmpbuf[0].__fpc_csr)); +#endif /* Save the signal mask if requested. */ return __sigjmp_save (env, savemask); -- 2.7.4