From 6b34051b3370b409e9081345b98005cb43b0a22e Mon Sep 17 00:00:00 2001 From: Ana Pazos Date: Thu, 30 Aug 2018 19:43:19 +0000 Subject: [PATCH] [RISCV] Fixed SmallVector.h Assertion `idx < size()' Summary: RISCVAsmParser needs to handle the case the error message is of specific type, other than the generic Match_InvalidOperand, and the corresponding operand is missing. This bug was uncovered by a LLVM MC Assembler Protocol Buffer Fuzzer for the RISC-V assembly language. Reviewers: asb Reviewed By: asb Subscribers: llvm-commits, jocewei, asb, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX Differential Revision: https://reviews.llvm.org/D50790 llvm-svn: 341104 --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 18 +++++++++++++++++- llvm/test/MC/RISCV/rv32i-invalid.s | 2 ++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 831dcbc..3e469c8 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -684,7 +684,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, bool MatchingInlineAsm) { MCInst Inst; - switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { + auto Result = + MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); + switch (Result) { default: break; case Match_Success: @@ -705,6 +707,20 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } return Error(ErrorLoc, "invalid operand for instruction"); } + } + + // Handle the case when the error message is of specific type + // other than the generic Match_InvalidOperand, and the + // corresponding operand is missing. + if (Result > FIRST_TARGET_MATCH_RESULT_TY) { + SMLoc ErrorLoc = IDLoc; + if (ErrorInfo != ~0U && ErrorInfo >= Operands.size()) + return Error(ErrorLoc, "too few operands for instruction"); + } + + switch(Result) { + default: + break; case Match_InvalidImmXLen: if (isRV64()) { SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc(); diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s index aa1ce40..f786806 100644 --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -138,6 +138,8 @@ lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the # Too few operands ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction +# FIXME: Fix jal behavior to interpret a3 as a symbol rather than a register. +jal a3 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Instruction not in the base ISA mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled -- 2.7.4