From 6b28be873e05d62c2aa0f213239c50a5037070b8 Mon Sep 17 00:00:00 2001 From: Carol Eidt Date: Tue, 8 Dec 2015 18:15:15 -0800 Subject: [PATCH] Enable FEATURE_SIMD on Linux. Most of the changes involve checking varTypeIsStruct instead of TYP_STRUCT in cases where the SIMD types are treated like other structs, and then adding a few special cases for SIMD types. The UNIX ABI implementation currently requires that struct handles be preserved through code generation, so this required some additional changes. Finally, the code that "homes" incoming arguments required changes to handle incoming SIMD register args that need to be reassembled into their assigned registers. That method was slightly refactored, primarily because it had cases that should have been ifdef'd out for 64 bits. It needs further refactoring, but that is left for future work. This fixes half of issue #983. A previous version of this PR exposed issues with JIT/SIMD tests being inconsistently compiled wrt optimization. This change modifies those tests to always compile both with and without optimization. --- src/jit/CMakeLists.txt | 7 +- src/jit/codegencommon.cpp | 183 +++++++++++---------- src/jit/codegenxarch.cpp | 86 +++++++--- src/jit/compiler.h | 29 +++- src/jit/ee_il_dll.cpp | 4 +- src/jit/flowgraph.cpp | 34 ++-- src/jit/gentree.cpp | 13 +- src/jit/importer.cpp | 49 +++--- src/jit/lclvars.cpp | 46 +++--- src/jit/lower.cpp | 20 ++- src/jit/lowerxarch.cpp | 43 +++-- src/jit/lsra.cpp | 4 +- src/jit/morph.cpp | 52 +++--- src/jit/optcse.cpp | 11 +- src/jit/rationalize.cpp | 37 +++-- src/jit/scopeinfo.cpp | 2 +- src/jit/simd.cpp | 22 +-- src/jit/simd.h | 2 +- .../{AbsGeneric.csproj => AbsGeneric_r.csproj} | 8 +- tests/src/JIT/SIMD/AbsGeneric_ro.csproj | 49 ++++++ .../JIT/SIMD/{AbsSqrt.csproj => AbsSqrt_r.csproj} | 8 +- tests/src/JIT/SIMD/AbsSqrt_ro.csproj | 49 ++++++ ...dingSequence.csproj => AddingSequence_r.csproj} | 8 +- tests/src/JIT/SIMD/AddingSequence_ro.csproj | 49 ++++++ ...perations.csproj => BitwiseOperations_r.csproj} | 8 +- tests/src/JIT/SIMD/BitwiseOperations_ro.csproj | 50 ++++++ .../SIMD/{BoxUnbox.csproj => BoxUnbox_r.csproj} | 8 +- tests/src/JIT/SIMD/BoxUnbox_ro.csproj | 49 ++++++ .../{BugWithAVX.csproj => BugWithAVX_r.csproj} | 8 +- tests/src/JIT/SIMD/BugWithAVX_ro.csproj | 49 ++++++ ...rcleInConvex.csproj => CircleInConvex_r.csproj} | 8 +- tests/src/JIT/SIMD/CircleInConvex_ro.csproj | 49 ++++++ ...CreateGeneric.csproj => CreateGeneric_r.csproj} | 8 +- tests/src/JIT/SIMD/CreateGeneric_ro.csproj | 49 ++++++ ...CtorFromArray.csproj => CtorFromArray_r.csproj} | 8 +- tests/src/JIT/SIMD/CtorFromArray_ro.csproj | 49 ++++++ .../src/JIT/SIMD/{Ctors.csproj => Ctors_r.csproj} | 8 +- tests/src/JIT/SIMD/Ctors_ro.csproj | 49 ++++++ ...dTest.csproj => DivSignedUnsignedTest_r.csproj} | 8 +- tests/src/JIT/SIMD/DivSignedUnsignedTest_ro.csproj | 49 ++++++ tests/src/JIT/SIMD/{Dup.csproj => Dup_r.csproj} | 8 +- tests/src/JIT/SIMD/Dup_ro.csproj | 49 ++++++ ...ic.csproj => Haar-likeFeaturesGeneric_r.csproj} | 8 +- .../JIT/SIMD/Haar-likeFeaturesGeneric_ro.csproj | 49 ++++++ .../{LdfldGeneric.csproj => LdfldGeneric_r.csproj} | 8 +- tests/src/JIT/SIMD/LdfldGeneric_ro.csproj | 49 ++++++ .../src/JIT/SIMD/{Ldfld.csproj => Ldfld_r.csproj} | 8 +- tests/src/JIT/SIMD/Ldfld_ro.csproj | 49 ++++++ .../src/JIT/SIMD/{Ldind.csproj => Ldind_r.csproj} | 8 +- tests/src/JIT/SIMD/Ldind_ro.csproj | 50 ++++++ .../JIT/SIMD/{MinMax.csproj => MinMax_r.csproj} | 8 +- tests/src/JIT/SIMD/MinMax_ro.csproj | 49 ++++++ tests/src/JIT/SIMD/{Mul.csproj => Mul_r.csproj} | 8 +- tests/src/JIT/SIMD/Mul_ro.csproj | 49 ++++++ .../{SqrtGeneric.csproj => SqrtGeneric_r.csproj} | 8 +- tests/src/JIT/SIMD/SqrtGeneric_ro.csproj | 49 ++++++ .../{StoreElement.csproj => StoreElement_r.csproj} | 8 +- tests/src/JIT/SIMD/StoreElement_ro.csproj | 49 ++++++ tests/src/JIT/SIMD/{Sums.csproj => Sums_r.csproj} | 8 +- tests/src/JIT/SIMD/Sums_ro.csproj | 49 ++++++ .../JIT/SIMD/{Vector3.csproj => Vector3_r.csproj} | 8 +- tests/src/JIT/SIMD/Vector3_ro.csproj | 49 ++++++ .../JIT/SIMD/{Vector4.csproj => Vector4_r.csproj} | 8 +- tests/src/JIT/SIMD/Vector4_ro.csproj | 49 ++++++ .../SIMD/{VectorAbs.csproj => VectorAbs_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorAbs_ro.csproj | 50 ++++++ .../SIMD/{VectorAdd.csproj => VectorAdd_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorAdd_ro.csproj | 50 ++++++ .../{VectorArgs.csproj => VectorArgs_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorArgs_ro.csproj | 50 ++++++ ...orArrayInit.csproj => VectorArrayInit_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorArrayInit_ro.csproj | 50 ++++++ .../{VectorArray.csproj => VectorArray_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorArray_ro.csproj | 50 ++++++ ...pyToArray.csproj => VectorCopyToArray_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorCopyToArray_ro.csproj | 50 ++++++ .../SIMD/{VectorDiv.csproj => VectorDiv_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorDiv_ro.csproj | 50 ++++++ .../SIMD/{VectorDot.csproj => VectorDot_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorDot_ro.csproj | 50 ++++++ .../SIMD/{VectorExp.csproj => VectorExp_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorExp_ro.csproj | 50 ++++++ .../SIMD/{VectorGet.csproj => VectorGet_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorGet_ro.csproj | 50 ++++++ ...ctorHWAccel2.csproj => VectorHWAccel2_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorHWAccel2_ro.csproj | 50 ++++++ ...VectorHWAccel.csproj => VectorHWAccel_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorHWAccel_ro.csproj | 50 ++++++ .../{VectorInitN.csproj => VectorInitN_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorInitN_ro.csproj | 50 ++++++ .../{VectorInit.csproj => VectorInit_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorInit_ro.csproj | 50 ++++++ ...orIntEquals.csproj => VectorIntEquals_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorIntEquals_ro.csproj | 50 ++++++ .../{VectorMatrix.csproj => VectorMatrix_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorMatrix_ro.csproj | 50 ++++++ .../SIMD/{VectorMax.csproj => VectorMax_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorMax_ro.csproj | 50 ++++++ .../SIMD/{VectorMin.csproj => VectorMin_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorMin_ro.csproj | 50 ++++++ .../SIMD/{VectorMul.csproj => VectorMul_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorMul_ro.csproj | 50 ++++++ .../{VectorRelOp.csproj => VectorRelOp_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorRelOp_ro.csproj | 50 ++++++ .../{VectorReturn.csproj => VectorReturn_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorReturn_ro.csproj | 50 ++++++ .../SIMD/{VectorSet.csproj => VectorSet_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorSet_ro.csproj | 50 ++++++ .../{VectorSqrt.csproj => VectorSqrt_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorSqrt_ro.csproj | 50 ++++++ .../SIMD/{VectorSub.csproj => VectorSub_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorSub_ro.csproj | 50 ++++++ .../{VectorUnused.csproj => VectorUnused_r.csproj} | 8 +- tests/src/JIT/SIMD/VectorUnused_ro.csproj | 50 ++++++ 114 files changed, 3101 insertions(+), 306 deletions(-) rename tests/src/JIT/SIMD/{AbsGeneric.csproj => AbsGeneric_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/AbsGeneric_ro.csproj rename tests/src/JIT/SIMD/{AbsSqrt.csproj => AbsSqrt_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/AbsSqrt_ro.csproj rename tests/src/JIT/SIMD/{AddingSequence.csproj => AddingSequence_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/AddingSequence_ro.csproj rename tests/src/JIT/SIMD/{BitwiseOperations.csproj => BitwiseOperations_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/BitwiseOperations_ro.csproj rename tests/src/JIT/SIMD/{BoxUnbox.csproj => BoxUnbox_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/BoxUnbox_ro.csproj rename tests/src/JIT/SIMD/{BugWithAVX.csproj => BugWithAVX_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/BugWithAVX_ro.csproj rename tests/src/JIT/SIMD/{CircleInConvex.csproj => CircleInConvex_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/CircleInConvex_ro.csproj rename tests/src/JIT/SIMD/{CreateGeneric.csproj => CreateGeneric_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/CreateGeneric_ro.csproj rename tests/src/JIT/SIMD/{CtorFromArray.csproj => CtorFromArray_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/CtorFromArray_ro.csproj rename tests/src/JIT/SIMD/{Ctors.csproj => Ctors_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Ctors_ro.csproj rename tests/src/JIT/SIMD/{DivSignedUnsignedTest.csproj => DivSignedUnsignedTest_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/DivSignedUnsignedTest_ro.csproj rename tests/src/JIT/SIMD/{Dup.csproj => Dup_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Dup_ro.csproj rename tests/src/JIT/SIMD/{Haar-likeFeaturesGeneric.csproj => Haar-likeFeaturesGeneric_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_ro.csproj rename tests/src/JIT/SIMD/{LdfldGeneric.csproj => LdfldGeneric_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/LdfldGeneric_ro.csproj rename tests/src/JIT/SIMD/{Ldfld.csproj => Ldfld_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Ldfld_ro.csproj rename tests/src/JIT/SIMD/{Ldind.csproj => Ldind_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Ldind_ro.csproj rename tests/src/JIT/SIMD/{MinMax.csproj => MinMax_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/MinMax_ro.csproj rename tests/src/JIT/SIMD/{Mul.csproj => Mul_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Mul_ro.csproj rename tests/src/JIT/SIMD/{SqrtGeneric.csproj => SqrtGeneric_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/SqrtGeneric_ro.csproj rename tests/src/JIT/SIMD/{StoreElement.csproj => StoreElement_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/StoreElement_ro.csproj rename tests/src/JIT/SIMD/{Sums.csproj => Sums_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Sums_ro.csproj rename tests/src/JIT/SIMD/{Vector3.csproj => Vector3_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Vector3_ro.csproj rename tests/src/JIT/SIMD/{Vector4.csproj => Vector4_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/Vector4_ro.csproj rename tests/src/JIT/SIMD/{VectorAbs.csproj => VectorAbs_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorAbs_ro.csproj rename tests/src/JIT/SIMD/{VectorAdd.csproj => VectorAdd_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorAdd_ro.csproj rename tests/src/JIT/SIMD/{VectorArgs.csproj => VectorArgs_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorArgs_ro.csproj rename tests/src/JIT/SIMD/{VectorArrayInit.csproj => VectorArrayInit_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorArrayInit_ro.csproj rename tests/src/JIT/SIMD/{VectorArray.csproj => VectorArray_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorArray_ro.csproj rename tests/src/JIT/SIMD/{VectorCopyToArray.csproj => VectorCopyToArray_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorCopyToArray_ro.csproj rename tests/src/JIT/SIMD/{VectorDiv.csproj => VectorDiv_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorDiv_ro.csproj rename tests/src/JIT/SIMD/{VectorDot.csproj => VectorDot_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorDot_ro.csproj rename tests/src/JIT/SIMD/{VectorExp.csproj => VectorExp_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorExp_ro.csproj rename tests/src/JIT/SIMD/{VectorGet.csproj => VectorGet_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorGet_ro.csproj rename tests/src/JIT/SIMD/{VectorHWAccel2.csproj => VectorHWAccel2_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorHWAccel2_ro.csproj rename tests/src/JIT/SIMD/{VectorHWAccel.csproj => VectorHWAccel_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorHWAccel_ro.csproj rename tests/src/JIT/SIMD/{VectorInitN.csproj => VectorInitN_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorInitN_ro.csproj rename tests/src/JIT/SIMD/{VectorInit.csproj => VectorInit_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorInit_ro.csproj rename tests/src/JIT/SIMD/{VectorIntEquals.csproj => VectorIntEquals_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorIntEquals_ro.csproj rename tests/src/JIT/SIMD/{VectorMatrix.csproj => VectorMatrix_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorMatrix_ro.csproj rename tests/src/JIT/SIMD/{VectorMax.csproj => VectorMax_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorMax_ro.csproj rename tests/src/JIT/SIMD/{VectorMin.csproj => VectorMin_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorMin_ro.csproj rename tests/src/JIT/SIMD/{VectorMul.csproj => VectorMul_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorMul_ro.csproj rename tests/src/JIT/SIMD/{VectorRelOp.csproj => VectorRelOp_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorRelOp_ro.csproj rename tests/src/JIT/SIMD/{VectorReturn.csproj => VectorReturn_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorReturn_ro.csproj rename tests/src/JIT/SIMD/{VectorSet.csproj => VectorSet_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorSet_ro.csproj rename tests/src/JIT/SIMD/{VectorSqrt.csproj => VectorSqrt_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorSqrt_ro.csproj rename tests/src/JIT/SIMD/{VectorSub.csproj => VectorSub_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorSub_ro.csproj rename tests/src/JIT/SIMD/{VectorUnused.csproj => VectorUnused_r.csproj} (93%) create mode 100644 tests/src/JIT/SIMD/VectorUnused_ro.csproj diff --git a/src/jit/CMakeLists.txt b/src/jit/CMakeLists.txt index 9576195..e9d5d39 100644 --- a/src/jit/CMakeLists.txt +++ b/src/jit/CMakeLists.txt @@ -6,11 +6,12 @@ include_directories("../inc") # Enable the following for UNIX altjit on Windows # add_definitions(-DALT_JIT) -if (WIN32) if (CLR_CMAKE_PLATFORM_ARCH_AMD64) - add_definitions(-DFEATURE_SIMD -DFEATURE_AVX_SUPPORT) -endif (CLR_CMAKE_PLATFORM_ARCH_AMD64) + add_definitions(-DFEATURE_SIMD) +if (WIN32) + add_definitions(-DFEATURE_AVX_SUPPORT) endif (WIN32) +endif (CLR_CMAKE_PLATFORM_ARCH_AMD64) set( JIT_SOURCES alloc.cpp diff --git a/src/jit/codegencommon.cpp b/src/jit/codegencommon.cpp index 40dec4a..4830342 100644 --- a/src/jit/codegencommon.cpp +++ b/src/jit/codegencommon.cpp @@ -3827,7 +3827,21 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, // 2 means the second part of a register argument (e.g., for a TYP_DOUBLE on ARM) bool stackArg; // true if the argument gets homed to the stack bool processed; // true after we've processed the argument (and it is in its final location) - bool circular; // true if this register participates in a circular dependency loop + bool circular; // true if this register participates in a circular dependency loop. + + // For UNIX AMD64 struct passing, the type of the register argument slot can differ from + // the type of the lclVar in ways that are not ascertainable from lvType. + // So, for that case we retain the type of the register in the regArgTab. + // In other cases, we simply use the type of the lclVar to determine the type of the register. + + var_types getRegType(Compiler* compiler) + { +#if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) + return type; +#else // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) + return compiler->lvaTable[varNum].lvType; +#endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) + } } regArgTab [max(MAX_REG_ARG,MAX_FLOAT_REG_ARG)] = { }; unsigned varNum; @@ -3891,7 +3905,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, #endif // !_TARGET_ARM_ #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (regType != TYP_STRUCT) + if (!varTypeIsStruct(regType)) #endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) { // A struct might be passed partially in XMM register for System V calls. @@ -3905,7 +3919,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, int slots = 0; #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (varDsc->TypeGet() == TYP_STRUCT) + if (varTypeIsStruct(varDsc)) { CORINFO_CLASS_HANDLE typeHnd = varDsc->lvVerTypeInfo.GetClassHandle(); assert(typeHnd != nullptr); @@ -4020,14 +4034,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, for (int i = 0; i < slots; i ++) { -#if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - // For structs passed in registers on System V systems, - // get the regType from the table for each slot. - if (regType == TYP_STRUCT) - { - regType = regArgTab[regArgNum + i].type; - } -#endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) + regType = regArgTab[regArgNum + i].getRegType(compiler); regNumber regNum = genMapRegArgNumToRegNum(regArgNum + i, regType); // lvArgReg could be INT or FLOAT reg. So the following assertion doesn't hold. @@ -4101,13 +4108,12 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, goto NON_DEP; } -#if !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if ((i == 1) && (varDsc->TypeGet() == TYP_STRUCT) && +#if !defined(_TARGET_64BIT_) + if ((i == 1) && varTypeIsStruct(varDsc) && (varDsc->lvOtherReg == regNum)) { goto NON_DEP; } -#endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) if ((i == 1) && (genActualType(varDsc->TypeGet()) == TYP_LONG) && (varDsc->lvOtherReg == regNum)) { @@ -4119,6 +4125,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, { goto NON_DEP; } +#endif // !defined(_TARGET_64BIT_) regArgTab[regArgNum+i].circular = true; } else @@ -4169,20 +4176,28 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, noway_assert(varDsc->lvIsInReg()); noway_assert(!regArgTab[argNum].stackArg); - regNumber regNum = genMapRegArgNumToRegNum(argNum, varDsc->TypeGet()); + var_types regType = regArgTab[argNum].getRegType(compiler); + regNumber regNum = genMapRegArgNumToRegNum(argNum, regType); - regNumber destRegNum; + regNumber destRegNum = REG_NA; if (regArgTab[argNum].slot == 1) { destRegNum = varDsc->lvRegNum; } -#if FEATURE_MULTIREG_STRUCT_ARGS && !defined(_TARGET_ARM_) +#if FEATURE_MULTIREG_STRUCT_ARGS && defined(FEATURE_SIMD) && defined(_TARGET_AMD64_) else { assert(regArgTab[argNum].slot == 2); - destRegNum = varDsc->lvOtherReg; + assert(argNum > 0); + assert(regArgTab[argNum - 1].slot == 1); + assert(regArgTab[argNum - 1].varNum == varNum); + assert((varDsc->lvType == TYP_SIMD12) || (varDsc->lvType == TYP_SIMD16)); + regArgMaskLive &= ~genRegMask(regNum); + regArgTab[argNum].circular = false; + change = true; + continue; } -#else // FEATURE_MULTIREG_STRUCT_ARGS && !defined(_TARGET_ARM_) +#elif !defined(_TARGET_64BIT_) else if (regArgTab[argNum].slot == 2 && genActualType(varDsc->TypeGet()) == TYP_LONG) { @@ -4194,11 +4209,12 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, assert(varDsc->TypeGet() == TYP_DOUBLE); destRegNum = REG_NEXT(varDsc->lvRegNum); } -#endif // FEATURE_MULTIREG_STRUCT_ARGS && !defined(_TARGET_ARM_) +#endif // !defined(_TARGET_64BIT_) + noway_assert(destRegNum != REG_NA); if (genRegMask(destRegNum) & regArgMaskLive) { /* we are trashing a live argument register - record it */ - unsigned destRegArgNum = genMapRegNumToRegArgNum(destRegNum, varDsc->TypeGet()); + unsigned destRegArgNum = genMapRegNumToRegArgNum(destRegNum, regType); noway_assert(destRegArgNum < regState->rsCalleeRegArgNum); regArgTab[destRegArgNum].trashBy = argNum; } @@ -4316,15 +4332,15 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, { size = EA_SIZE(varDsc->lvSize()); #if defined(_TARGET_AMD64_) -#ifndef FEATURE_UNIX_AMD64_STRUCT_PASSING +#ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING + storeType = regArgTab[argNum].type; + size = emitActualTypeSize(storeType); +#else // !FEATURE_UNIX_AMD64_STRUCT_PASSING storeType = (var_types)((size <= 4) ? TYP_INT : TYP_I_IMPL); // Must be 1, 2, 4, or 8, or else it wouldn't be passed in a register noway_assert(EA_SIZE_IN_BYTES(size) <= 8); assert((EA_SIZE_IN_BYTES(size) & (EA_SIZE_IN_BYTES(size) - 1)) == 0); -#else // !FEATURE_UNIX_AMD64_STRUCT_PASSING - storeType = regArgTab[argNum].type; - size = emitActualTypeSize(storeType); -#endif // FEATURE_UNIX_AMD64_STRUCT_PASSING +#endif // !FEATURE_UNIX_AMD64_STRUCT_PASSING #elif defined(_TARGET_ARM64_) // Must be <= 16 bytes or else it wouldn't be passed in registers noway_assert(EA_SIZE_IN_BYTES(size) <= MAX_PASS_MULTIREG_BYTES); @@ -4683,20 +4699,21 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, varNum = regArgTab[argNum].varNum; noway_assert(varNum < compiler->lvaCount); varDsc = compiler->lvaTable + varNum; - regNumber regNum = genMapRegArgNumToRegNum(argNum, varDsc->TypeGet()); + var_types regType = regArgTab[argNum].getRegType(compiler); + regNumber regNum = genMapRegArgNumToRegNum(argNum, regType); - // If this is the wrong register file, just continue. #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (regArgTab[argNum].type == TYP_UNDEF) + if (regType == TYP_UNDEF) { // This could happen if the reg in regArgTab[argNum] is of the other register file - - // for System V register passed structs where the first reg is GPR and the second an XMM reg. + // for System V register passed structs where the first reg is GPR and the second an XMM reg. // The next register file processing will process it. regArgMaskLive &= ~genRegMask(regNum); continue; } #endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) + noway_assert(varDsc->lvIsParam && varDsc->lvIsRegArg); #ifndef _WIN64 //Right now we think that incoming arguments are not pointer sized. When we eventually @@ -4711,7 +4728,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, noway_assert(varDsc->lvIsInReg() && !regArgTab[argNum].circular); /* Register argument - hopefully it stays in the same register */ - regNumber destRegNum; + regNumber destRegNum = REG_NA; var_types destMemType = varDsc->TypeGet(); if (regArgTab[argNum].slot == 1) @@ -4726,6 +4743,7 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, } #endif // _TARGET_ARM_ } +#ifndef _TARGET_64BIT_ else if (regArgTab[argNum].slot == 2 && genActualType(destMemType) == TYP_LONG) { @@ -4782,7 +4800,20 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, destMemType = TYP_FLOAT; destRegNum = REG_NEXT(varDsc->lvRegNum); } - +#endif // !_TARGET_64BIT_ +#if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) && defined(FEATURE_SIMD) + else + { + assert(regArgTab[argNum].slot == 2); + assert(argNum > 0); + assert(regArgTab[argNum - 1].slot == 1); + assert((varDsc->lvType == TYP_SIMD12) || (varDsc->lvType == TYP_SIMD16)); + destRegNum = varDsc->lvRegNum; + noway_assert(regNum != destRegNum); + continue; + } +#endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) && defined(FEATURE_SIMD) + noway_assert(destRegNum != REG_NA); if (destRegNum != regNum) { /* Cannot trash a currently live register argument. @@ -4816,16 +4847,44 @@ void CodeGen::genFnPrologCalleeRegArgs(regNumber xtraReg, assert(!regArgTab[argNum].processed); regArgTab[argNum].processed = true; regArgMaskLive &= ~genRegMask(regNum); +#ifdef FEATURE_MULTIREG_STRUCTS + int argRegCount = 1; #ifdef _TARGET_ARM_ if (genActualType(destMemType) == TYP_DOUBLE) { - assert(!regArgTab[argNum+1].processed); - regArgTab[argNum+1].processed = true; - regArgMaskLive &= ~genRegMask(REG_NEXT(regNum)); + argRegCount = 2; } #endif +#if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) && defined(FEATURE_SIMD) + if (varTypeIsStruct(varDsc) && + argNum < (regState->rsCalleeRegArgNum - 1) && + regArgTab[argNum+1].slot == 2) + { + argRegCount = 2; + int nextArgNum = argNum + 1; + regNumber nextRegNum = genMapRegArgNumToRegNum(nextArgNum, regArgTab[nextArgNum].getRegType(compiler)); + noway_assert(regArgTab[nextArgNum].varNum == varNum); + // Emit a shufpd with a 0 immediate, which preserves the 0th element of the dest reg + // and moves the 0th element of the src reg into the 1st element of the dest reg. + getEmitter()->emitIns_R_R_I(INS_shufpd, emitActualTypeSize(varDsc->lvType), destRegNum, nextRegNum, 0); + // Set destRegNum to regNum so that we skip the setting of the register below, + // but mark argNum as processed and clear regNum from the live mask. + destRegNum = regNum; + } +#endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) && defined(FEATURE_SIMD) + // Mark the rest of the argument registers corresponding to this multi-reg type as + // being processed and no longer live. + for (int regSlot = 1; regSlot < argRegCount; regSlot++) + { + int nextArgNum = argNum + regSlot; + assert(!regArgTab[nextArgNum].processed); + regArgTab[nextArgNum].processed = true; + regNumber nextRegNum = genMapRegArgNumToRegNum(nextArgNum, regArgTab[nextArgNum].getRegType(compiler)); + regArgMaskLive &= ~genRegMask(nextRegNum); + } +#endif // FEATURE_MULTIREG_STRUCTS } - + noway_assert(regArgMaskLiveSave != regArgMaskLive); // if it doesn't change, we have an infinite loop } } @@ -11106,50 +11165,6 @@ void CodeGen::genRestoreCalleeSavedFltRegs(unsigned lclFrameSize) //------------------------------------------------------------------------ // Methods used to support FEATURE_MULTIREG_STRUCTS and HFA support for ARM32 //------------------------------------------------------------------------ -#if FEATURE_MULTIREG_STRUCTS -CORINFO_CLASS_HANDLE Compiler::GetStructClassHandle(GenTreePtr tree) -{ - if (tree->TypeGet() == TYP_STRUCT) - { - // If the following assert fires (and we have a GT_COMMA), we'll probably need code like this: - // while (tree->OperGet() == GT_COMMA) tree = tree->gtOp.gtOp2; - - assert(tree->OperGet() != GT_COMMA); - - switch (tree->OperGet()) - { - default: - break; - case GT_CALL: - return tree->gtCall.gtRetClsHnd; - - case GT_LDOBJ: - return tree->gtLdObj.gtClass; - - case GT_LCL_VAR: - case GT_LCL_FLD: - return lvaTable[tree->gtLclVarCommon.gtLclNum].lvVerTypeInfo.GetClassHandle(); - - case GT_ARGPLACE: - return tree->gtArgPlace.gtArgPlaceClsHnd; - - case GT_ASG: - assert(tree->gtOp.gtOp1->gtOper == GT_LCL_VAR || tree->gtOp.gtOp1->gtOper == GT_LCL_FLD); - return GetStructClassHandle(tree->gtOp.gtOp1); - -#if FEATURE_MULTIREG_STRUCT_RET - case GT_RET_EXPR: - return tree->gtRetExpr.gtRetClsHnd; - - case GT_RETURN: - assert(tree->gtOp.gtOp1->gtOper == GT_LCL_VAR); - return GetStructClassHandle(tree->gtOp.gtOp1); -#endif - } - } - return NO_CLASS_HANDLE; -} -#endif // FEATURE_MULTIREG_STRUCTS #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING bool Compiler::IsRegisterPassable(CORINFO_CLASS_HANDLE hClass) @@ -11166,7 +11181,7 @@ bool Compiler::IsRegisterPassable(CORINFO_CLASS_HANDLE hClass) bool Compiler::IsRegisterPassable(GenTreePtr tree) { - return IsRegisterPassable(GetStructClassHandle(tree)); + return IsRegisterPassable(gtGetStructHandleIfPresent(tree)); } #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING @@ -11178,17 +11193,17 @@ bool Compiler::IsHfa(CORINFO_CLASS_HANDLE hClass) bool Compiler::IsHfa(GenTreePtr tree) { - return IsHfa(GetStructClassHandle(tree)); + return IsHfa(gtGetStructHandleIfPresent(tree)); } var_types Compiler::GetHfaType(GenTreePtr tree) { - return (tree->TypeGet() == TYP_STRUCT) ? GetHfaType(GetStructClassHandle(tree)) : TYP_UNDEF; + return (tree->TypeGet() == TYP_STRUCT) ? GetHfaType(gtGetStructHandleIfPresent(tree)) : TYP_UNDEF; } unsigned Compiler::GetHfaSlots(GenTreePtr tree) { - return GetHfaSlots(GetStructClassHandle(tree)); + return GetHfaSlots(gtGetStructHandleIfPresent(tree)); } var_types Compiler::GetHfaType(CORINFO_CLASS_HANDLE hClass) diff --git a/src/jit/codegenxarch.cpp b/src/jit/codegenxarch.cpp index 74c8ac0..400a29f 100644 --- a/src/jit/codegenxarch.cpp +++ b/src/jit/codegenxarch.cpp @@ -1797,7 +1797,7 @@ CodeGen::genCodeForTreeNode(GenTreePtr treeNode) else { #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (treeNode->TypeGet() == TYP_STRUCT && + if (varTypeIsStruct(treeNode) && treeNode->gtOp.gtOp1->OperGet() == GT_LCL_VAR) { GenTreeLclVarCommon* lclVarPtr = treeNode->gtOp.gtOp1->AsLclVarCommon(); @@ -2645,12 +2645,28 @@ CodeGen::genCodeForTreeNode(GenTreePtr treeNode) bool CodeGen::genStoreRegisterReturnInLclVar(GenTreePtr treeNode) { - if (treeNode->TypeGet() == TYP_STRUCT) - { - noway_assert(!treeNode->InReg()); + + if (varTypeIsStruct(treeNode)) + { GenTreeLclVarCommon* lclVarPtr = treeNode->AsLclVarCommon(); + // TODO-Cleanup: It is not reasonable to assume that a local store of TYP_STRUCT is always a register return. + // There can be local SIMD references that are NOT args or returns. + // Furthermore, this means that there are contextual semantics for these nodes, + // which is very undesirable. + + if (varTypeIsSIMD(treeNode)) + { + noway_assert(treeNode->OperIsLocalStore()); + if (treeNode->gtGetOp1()->OperGet() != GT_CALL) + { + return false; + } + } + + noway_assert(!treeNode->InReg()); + LclVarDsc * varDsc = &(compiler->lvaTable[lclVarPtr->gtLclNum]); CORINFO_CLASS_HANDLE typeHnd = varDsc->lvVerTypeInfo.GetClassHandle(); @@ -3560,10 +3576,13 @@ void CodeGen::genCodeForCpBlkRepMovs(GenTreeCpBlk* cpBlkNode) // void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseVarNum) { + // We will never call this method for SIMD types, which are stored directly + // in genPutStructArgStk(). noway_assert(putArgNode->TypeGet() == TYP_STRUCT); + // Make sure we got the arguments of the cpblk operation in the right registers GenTreePtr dstAddr = putArgNode; - GenTreePtr srcAddr = putArgNode->gtOp.gtOp1; + GenTreePtr src = putArgNode->gtOp.gtOp1; size_t size = putArgNode->getArgSize(); assert(size <= CPBLK_UNROLL_LIMIT); @@ -3571,12 +3590,13 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseV emitter *emit = getEmitter(); unsigned putArgOffset = putArgNode->getArgOffset(); - assert(srcAddr->isContained()); - assert(srcAddr->gtOper == GT_LDOBJ); + assert(src->isContained()); + + assert(src->gtOper == GT_LDOBJ); - if (!srcAddr->gtOp.gtOp1->isContained()) + if (!src->gtOp.gtOp1->isContained()) { - genConsumeReg(srcAddr->gtOp.gtOp1); + genConsumeReg(src->gtOp.gtOp1); } unsigned offset = 0; @@ -3600,7 +3620,7 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseV while (slots-- > 0) { // Load - genCodeForLoadOffset(INS_movdqu, EA_8BYTE, xmmReg, srcAddr->gtGetOp1(), offset); // Load the address of the child of the LdObj node. + genCodeForLoadOffset(INS_movdqu, EA_8BYTE, xmmReg, src->gtGetOp1(), offset); // Load the address of the child of the LdObj node. // Store emit->emitIns_S_R(INS_movdqu, @@ -3622,7 +3642,7 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseV if ((size & 8) != 0) { - genCodeForLoadOffset(INS_mov, EA_8BYTE, tmpReg, srcAddr->gtOp.gtOp1, offset); + genCodeForLoadOffset(INS_mov, EA_8BYTE, tmpReg, src->gtOp.gtOp1, offset); emit->emitIns_S_R(INS_mov, EA_8BYTE, @@ -3635,7 +3655,7 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseV if ((size & 4) != 0) { - genCodeForLoadOffset(INS_mov, EA_4BYTE, tmpReg, srcAddr->gtOp.gtOp1, offset); + genCodeForLoadOffset(INS_mov, EA_4BYTE, tmpReg, src->gtOp.gtOp1, offset); emit->emitIns_S_R(INS_mov, EA_4BYTE, @@ -3648,7 +3668,7 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseV if ((size & 2) != 0) { - genCodeForLoadOffset(INS_mov, EA_2BYTE, tmpReg, srcAddr->gtOp.gtOp1, offset); + genCodeForLoadOffset(INS_mov, EA_2BYTE, tmpReg, src->gtOp.gtOp1, offset); emit->emitIns_S_R(INS_mov, EA_2BYTE, @@ -3661,7 +3681,7 @@ void CodeGen::genStructPutArgUnroll(GenTreePutArgStk* putArgNode, unsigned baseV if ((size & 1) != 0) { - genCodeForLoadOffset(INS_mov, EA_1BYTE, tmpReg, srcAddr->gtOp.gtOp1, offset); + genCodeForLoadOffset(INS_mov, EA_1BYTE, tmpReg, src->gtOp.gtOp1, offset); emit->emitIns_S_R(INS_mov, EA_1BYTE, tmpReg, @@ -4966,7 +4986,7 @@ void CodeGen::genConsumeOperands(GenTreeOp* tree) void CodeGen::genConsumePutStructArgStk(GenTreePutArgStk* putArgNode, regNumber dstReg, regNumber srcReg, regNumber sizeReg, unsigned baseVarNum) { - assert(putArgNode->TypeGet() == TYP_STRUCT); + assert(varTypeIsStruct(putArgNode)); assert(baseVarNum != BAD_VAR_NUM); // The putArgNode children are always contained. We should not consume any registers. @@ -4976,7 +4996,7 @@ void CodeGen::genConsumePutStructArgStk(GenTreePutArgStk* putArgNode, regNumber // Get the GT_ADDR node, which is GT_LCL_VAR_ADDR (asserted below.) GenTree* src = putArgNode->gtGetOp1(); - assert(src->OperGet() == GT_LDOBJ); + assert((src->gtOper == GT_LDOBJ) || ((src->gtOper == GT_IND && varTypeIsSIMD(src)))); src = src->gtGetOp1(); size_t size = putArgNode->getArgSize(); @@ -5868,7 +5888,22 @@ void CodeGen::genCallInstruction(GenTreePtr node) else #endif // _TARGET_X86_ { - regNumber returnReg = (varTypeIsFloating(returnType) ? REG_FLOATRET : REG_INTRET); + regNumber returnReg; + // TODO-Cleanup: For UNIX AMD64, we should not be allocating a return register for struct + // returns that are on stack. + // For the SIMD case, however, we do want a "return register", as the consumer of the call + // will want the value in a register. In future we should flexibly allocate this return + // register, but that should be done with a general cleanup of the allocation of return + // registers for structs. + if (varTypeIsFloating(returnType) + FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY( || varTypeIsSIMD(returnType))) + { + returnReg = REG_FLOATRET; + } + else + { + returnReg = REG_INTRET; + } if (call->gtRegNum != returnReg) { inst_RV_RV(ins_Copy(returnType), call->gtRegNum, returnReg, returnType); @@ -6159,7 +6194,7 @@ void CodeGen::genJmpMethod(GenTreePtr jmp) continue; #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (varDsc->lvType == TYP_STRUCT) + if (varTypeIsStruct(varDsc)) { CORINFO_CLASS_HANDLE typeHnd = varDsc->lvVerTypeInfo.GetClassHandle(); assert(typeHnd != nullptr); @@ -7965,7 +8000,7 @@ CodeGen::genPutArgStk(GenTreePtr treeNode) #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (targetType == TYP_STRUCT) + if (varTypeIsStruct(targetType)) { genPutStructArgStk(treeNode, baseVarNum); return; @@ -8027,6 +8062,19 @@ CodeGen::genPutStructArgStk(GenTreePtr treeNode, unsigned baseVarNum) assert(baseVarNum != BAD_VAR_NUM); var_types targetType = treeNode->TypeGet(); + + if (varTypeIsSIMD(targetType)) + { + regNumber srcReg = genConsumeReg(treeNode->gtGetOp1()); + assert((srcReg != REG_NA) && (genIsValidFloatReg(srcReg))); + getEmitter()->emitIns_S_R(ins_Store(targetType), + emitTypeSize(targetType), + srcReg, + baseVarNum, + treeNode->AsPutArgStk()->getArgOffset()); + return; + } + assert(targetType == TYP_STRUCT); GenTreePutArgStk* putArgStk = treeNode->AsPutArgStk(); diff --git a/src/jit/compiler.h b/src/jit/compiler.h index 3b6b83f..116af31 100644 --- a/src/jit/compiler.h +++ b/src/jit/compiler.h @@ -1497,9 +1497,6 @@ public: DWORD expensiveDebugCheckLevel; #endif -#if FEATURE_MULTIREG_STRUCTS - CORINFO_CLASS_HANDLE GetStructClassHandle(GenTreePtr tree); -#endif #if FEATURE_MULTIREG_STRUCT_RET GenTreePtr impAssignStructClassToVar(GenTreePtr op, CORINFO_CLASS_HANDLE hClass); #endif @@ -6980,6 +6977,26 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CORINFO_CLASS_HANDLE SIMDVector4Handle; CORINFO_CLASS_HANDLE SIMDVectorHandle; + // Get the handle for a SIMD type. + // For the purposes of type handles, we treat all Vector as Vector in the JIT, + // as the actual instantiation type doesn't impact this code (that is always captured, + // where semantically meaningful, in the "baseType" of SIMD nodes or lclVars. + CORINFO_CLASS_HANDLE getStructHandleForSIMDType(var_types type) + { + noway_assert(varTypeIsSIMD(type)); + CORINFO_CLASS_HANDLE structHnd; + switch (type) + { + case TYP_SIMD8: structHnd = SIMDVector2Handle; break; + case TYP_SIMD12: structHnd = SIMDVector3Handle; break; + case TYP_SIMD16: structHnd = SIMDVector4Handle; break; +#ifdef FEATURE_AVX_SUPPORT + case TYP_SIMD32: structHnd = SIMDFloatHandle; break; +#endif // FEATURE_AVX_SUPPORT + default: unreached(); + } + return structHnd; + } // SIMD Methods CORINFO_METHOD_HANDLE SIMDVectorFloat_set_Item; CORINFO_METHOD_HANDLE SIMDVectorFloat_get_Length; @@ -7200,8 +7217,8 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // Get the the number of elements of basetype of SIMD vector given by its type handle int getSIMDVectorLength(CORINFO_CLASS_HANDLE typeHnd); - // Get preferred alignment of SIMD type given by its type handle - int getSIMDTypeAlignment(CORINFO_CLASS_HANDLE typeHnd); + // Get preferred alignment of SIMD type. + int getSIMDTypeAlignment(var_types simdType); // Get the number of bytes in a SIMD Vector for the current compilation. unsigned getSIMDVectorRegisterByteLength() @@ -7330,7 +7347,7 @@ private: bool ebpBased; int off = lvaFrameAddress(varNum, &ebpBased); // TODO-Cleanup: Can't this use the lvExactSize on the varDsc? - int alignment = getSIMDTypeAlignment(lvaTable[varNum].lvVerTypeInfo.GetClassHandle()); + int alignment = getSIMDTypeAlignment(lvaTable[varNum].lvType); bool isAligned = ((off % alignment) == 0); noway_assert (isAligned || lvaTable[varNum].lvIsParam); return isAligned; diff --git a/src/jit/ee_il_dll.cpp b/src/jit/ee_il_dll.cpp index da2a187..55d3cae 100644 --- a/src/jit/ee_il_dll.cpp +++ b/src/jit/ee_il_dll.cpp @@ -300,7 +300,7 @@ unsigned Compiler::eeGetArgSize(CORINFO_ARG_LIST_HANDLE list, CORINFO_ CORINFO_CLASS_HANDLE argClass; CorInfoType argTypeJit = strip(info.compCompHnd->getArgType(sig, list, &argClass)); var_types argType = JITtype2varType(argTypeJit); - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { unsigned structSize = info.compCompHnd->getClassSize(argClass); return structSize; // TODO: roundUp() needed here? @@ -314,7 +314,7 @@ unsigned Compiler::eeGetArgSize(CORINFO_ARG_LIST_HANDLE list, CORINFO_ CorInfoType argTypeJit = strip(info.compCompHnd->getArgType(sig, list, &argClass)); var_types argType = JITtype2varType(argTypeJit); - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { unsigned structSize = info.compCompHnd->getClassSize(argClass); diff --git a/src/jit/flowgraph.cpp b/src/jit/flowgraph.cpp index 7547553..c1f1f8f 100755 --- a/src/jit/flowgraph.cpp +++ b/src/jit/flowgraph.cpp @@ -8162,8 +8162,8 @@ void Compiler::fgAddInternal() // native return type is not a struct or the native return type is a struct that is returned // in registers (no RetBuffArg argument.) // If we fold all returns into a single return statement, create a temp for struct type variables as well. - if (genReturnBB && ((info.compRetType != TYP_VOID && info.compRetNativeType != TYP_STRUCT) || - (info.compRetNativeType == TYP_STRUCT && info.compRetBuffArg == BAD_VAR_NUM))) + if (genReturnBB && ((info.compRetType != TYP_VOID && !varTypeIsStruct(info.compRetNativeType)) || + (varTypeIsStruct(info.compRetNativeType) && info.compRetBuffArg == BAD_VAR_NUM))) #else // !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) if (genReturnBB && (info.compRetType != TYP_VOID) && !varTypeIsStruct(info.compRetNativeType)) #endif // !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) @@ -8200,10 +8200,10 @@ void Compiler::fgAddInternal() #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // Handle a struct return type for System V Amd64 systems. - if (info.compRetNativeType == TYP_STRUCT) + if (varTypeIsStruct(info.compRetNativeType)) { // Handle the normalized return type. - if (retLocalType == TYP_STRUCT) + if (varTypeIsStruct(retLocalType)) { lvaSetStruct(genReturnLocal, info.compMethodInfo->args.retTypeClass, true); } @@ -21648,14 +21648,17 @@ void Compiler::fgInline() */ GenTreePtr Compiler::fgGetStructAsStructPtr(GenTreePtr tree) { - noway_assert(tree->gtOper == GT_LCL_VAR || - tree->gtOper == GT_FIELD || - tree->gtOper == GT_IND || - tree->gtOper == GT_LDOBJ || + noway_assert((tree->gtOper == GT_LCL_VAR) || + (tree->gtOper == GT_FIELD) || + (tree->gtOper == GT_IND) || + (tree->gtOper == GT_LDOBJ) || +#ifdef FEATURE_SIMD + (tree->gtOper == GT_SIMD) || // tree->gtOper == GT_CALL || cannot get address of call. // tree->gtOper == GT_MKREFANY || inlining should've been aborted due to mkrefany opcode. // tree->gtOper == GT_RET_EXPR || cannot happen after fgUpdateInlineReturnExpressionPlaceHolder - tree->gtOper == GT_COMMA); + (tree->gtOper == GT_COMMA)); +#endif // FEATURE_SIMD switch (tree->OperGet()) { @@ -21686,8 +21689,9 @@ GenTreePtr Compiler::fgAssignStructInlineeToVar(GenTreePtr child, CORINFO_CLASS_ unsigned tmpNum = lvaGrabTemp(false DEBUGARG("RetBuf for struct inline return candidates.")); lvaSetStruct(tmpNum, retClsHnd, false); + var_types structType = lvaTable[tmpNum].lvType; - GenTreePtr dst = gtNewLclvNode(tmpNum, TYP_STRUCT); + GenTreePtr dst = gtNewLclvNode(tmpNum, structType); // If we have a call, we'd like it to be: V00 = call(), but first check if // we have a ", , , call()" -- this is very defensive as we may never get @@ -21723,8 +21727,8 @@ GenTreePtr Compiler::fgAssignStructInlineeToVar(GenTreePtr child, CORINFO_CLASS_ newInlinee = gtNewCpObjNode(dstAddr, srcAddr, retClsHnd, false); } - GenTreePtr production = gtNewLclvNode(tmpNum, TYP_STRUCT); - return gtNewOperNode(GT_COMMA, TYP_STRUCT, newInlinee, production); + GenTreePtr production = gtNewLclvNode(tmpNum, structType); + return gtNewOperNode(GT_COMMA, structType, newInlinee, production); } /*************************************************************************************************** @@ -21776,7 +21780,7 @@ Compiler::fgWalkResult Compiler::fgUpdateInlineReturnExpressionPlaceHolder( { #if defined(_TARGET_ARM_) || defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // We are going to copy the tree from the inlinee, so save the handle now. - CORINFO_CLASS_HANDLE retClsHnd = (tree->TypeGet() == TYP_STRUCT) + CORINFO_CLASS_HANDLE retClsHnd = varTypeIsStruct(tree) ? tree->gtRetExpr.gtRetClsHnd : NO_CLASS_HANDLE; #endif // defined(_TARGET_ARM_) || defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) @@ -21859,11 +21863,11 @@ Compiler::fgWalkResult Compiler::fgUpdateInlineReturnExpressionPlaceHolder( } #if defined(_TARGET_ARM_) - noway_assert(comma->gtType != TYP_STRUCT || + noway_assert(!varTypeIsStruct(comma) || comma->gtOper != GT_RET_EXPR || (!comp->IsHfa(comma->gtRetExpr.gtRetClsHnd))); #elif defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - noway_assert(comma->gtType != TYP_STRUCT || + noway_assert(!varTypeIsStruct(comma) || comma->gtOper != GT_RET_EXPR || (!comp->IsRegisterPassable(comma->gtRetExpr.gtRetClsHnd))); #endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) diff --git a/src/jit/gentree.cpp b/src/jit/gentree.cpp index 8c937db..ac7bbe6 100644 --- a/src/jit/gentree.cpp +++ b/src/jit/gentree.cpp @@ -5229,7 +5229,7 @@ GenTreePtr Compiler::gtNewInlineCandidateReturnExpr(GenTreePtr inline node->gtRetExpr.gtInlineCandidate = inlineCandidate; - if (inlineCandidate->gtType == TYP_STRUCT) + if (varTypeIsStruct(inlineCandidate)) { node->gtRetExpr.gtRetClsHnd = gtGetStructHandle(inlineCandidate); } @@ -12895,6 +12895,7 @@ CORINFO_CLASS_HANDLE Compiler::gtGetStructHandleIfPresent(GenTree* tree) structHnd = gtGetStructHandle(tree->gtGetOp1()); break; case GT_LCL_VAR: + case GT_LCL_FLD: structHnd = lvaTable[tree->AsLclVarCommon()->gtLclNum].lvVerTypeInfo.GetClassHandle(); assert(structHnd != NO_CLASS_HANDLE); break; @@ -12906,6 +12907,16 @@ CORINFO_CLASS_HANDLE Compiler::gtGetStructHandleIfPresent(GenTree* tree) assert(b); structHnd = EncodeElemType(arrInfo.m_elemType, arrInfo.m_elemStructType); } +#ifdef FEATURE_SIMD + else if (varTypeIsSIMD(tree)) + { + structHnd = getStructHandleForSIMDType(tree->gtType); + } + break; + case GT_SIMD: + structHnd = getStructHandleForSIMDType(tree->gtType); +#endif // FEATURE_SIMD + break; } } return structHnd; diff --git a/src/jit/importer.cpp b/src/jit/importer.cpp index 05c0119..7af7c09 100755 --- a/src/jit/importer.cpp +++ b/src/jit/importer.cpp @@ -91,7 +91,6 @@ void Compiler::impInit() * Pushes the given tree on the stack. */ -inline void Compiler::impPushOnStack(GenTreePtr tree, typeInfo ti) { /* Check for overflow. If inlining, we may be using a bigger stack */ @@ -296,7 +295,6 @@ void Compiler::impResolveToken(const BYTE* addr, CORINFO_RESOLVED_TOKEN * pResol * Pop one tree from the stack. */ -inline StackEntry Compiler::impPopStack() { if (verCurrentState.esStackDepth == 0) @@ -319,7 +317,6 @@ StackEntry Compiler::impPopStack() return verCurrentState.esStack[--verCurrentState.esStackDepth]; } -inline StackEntry Compiler::impPopStack(CORINFO_CLASS_HANDLE& structType) { StackEntry ret = impPopStack(); @@ -327,7 +324,6 @@ StackEntry Compiler::impPopStack(CORINFO_CLASS_HANDLE& structType) return(ret); } -inline GenTreePtr Compiler::impPopStack(typeInfo& ti) { StackEntry ret = impPopStack(); @@ -342,7 +338,6 @@ GenTreePtr Compiler::impPopStack(typeInfo& ti) * Peep at n'th (0-based) tree on the top of the stack. */ -inline StackEntry& Compiler::impStackTop(unsigned n) { if (verCurrentState.esStackDepth <= n) @@ -1170,7 +1165,8 @@ GenTreePtr Compiler::impAssignStructPtr(GenTreePtr dest, src->gtOper == GT_IND || src->gtOper == GT_LDOBJ || src->gtOper == GT_CALL || src->gtOper == GT_MKREFANY || src->gtOper == GT_RET_EXPR || src->gtOper == GT_COMMA || - src->gtOper == GT_ADDR || GenTree::OperIsSIMD(src->gtOper)); + src->gtOper == GT_ADDR || + (src->TypeGet() != TYP_STRUCT && (GenTree::OperIsSIMD(src->gtOper) || src->gtOper == GT_LCL_FLD))); #else // !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) assert(varTypeIsStruct(src)); @@ -1178,7 +1174,7 @@ GenTreePtr Compiler::impAssignStructPtr(GenTreePtr dest, src->gtOper == GT_IND || src->gtOper == GT_LDOBJ || src->gtOper == GT_CALL || src->gtOper == GT_MKREFANY || src->gtOper == GT_RET_EXPR || src->gtOper == GT_COMMA || - GenTree::OperIsSIMD(src->gtOper)); + (src->TypeGet() != TYP_STRUCT && (GenTree::OperIsSIMD(src->gtOper) || src->gtOper == GT_LCL_FLD))); #endif // !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) if (src->gtOper == GT_CALL) @@ -7108,8 +7104,10 @@ GenTreePtr Compiler::impFixupStructReturn(GenTreePtr call, // Not allowed for FEATURE_CORCLR which is the only SKU available for System V OSs. assert(!call->gtCall.IsVarargs() && "varargs not allowed for System V OSs."); - // The return is a struct if not normalized to a single eightbyte return type below. - call->gtCall.gtReturnType = TYP_STRUCT; + // The return type will remain as the incoming struct type unless normalized to a + // single eightbyte return type below. + call->gtCall.gtReturnType = call->gtType; + // Get the classification for the struct. SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; eeGetSystemVAmd64PassStructInRegisterDescriptor(retClsHnd, &structDesc); @@ -7169,11 +7167,9 @@ GenTreePtr Compiler::impFixupStructReturnType(GenTreePtr op, CORINFO_CL assert(info.compRetBuffArg == BAD_VAR_NUM); #if defined(_TARGET_X86_) || defined(_TARGET_AMD64_) -#ifndef FEATURE_UNIX_AMD64_STRUCT_PASSING - assert(info.compRetNativeType != TYP_STRUCT); -#else // !FEATURE_UNIX_AMD64_STRUCT_PASSING +#ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING assert(!info.compIsVarArgs); // No VarArgs for CoreCLR. - if (info.compRetNativeType == TYP_STRUCT) + if (varTypeIsStruct(info.compRetNativeType)) { SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; eeGetSystemVAmd64PassStructInRegisterDescriptor(retClsHnd, &structDesc); @@ -7197,6 +7193,8 @@ GenTreePtr Compiler::impFixupStructReturnType(GenTreePtr op, CORINFO_CL return impAssignStructClassToVar(op, retClsHnd); } } +#else // !FEATURE_UNIX_AMD64_STRUCT_PASSING + assert(info.compRetNativeType != TYP_STRUCT); #endif // !FEATURE_UNIX_AMD64_STRUCT_PASSING #elif defined(_TARGET_ARM_) @@ -7291,7 +7289,7 @@ REDO_RETURN_NODE: { #ifdef DEBUG #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (op->gtType == TYP_STRUCT) + if (varTypeIsStruct(op)) { SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; eeGetSystemVAmd64PassStructInRegisterDescriptor(retClsHnd, &structDesc); @@ -7301,7 +7299,7 @@ REDO_RETURN_NODE: else #else // !FEATURE_UNIX_AMD64_STRUCT_PASSING { - assert(info.compRetNativeType == op->gtCall.gtReturnType); + assert(info.compRetNativeType == op->gtCall.gtReturnType); } #endif // !FEATURE_UNIX_AMD64_STRUCT_PASSING #endif // DEBUG @@ -7314,7 +7312,7 @@ REDO_RETURN_NODE: op->gtOp.gtOp2 = impFixupStructReturnType(op->gtOp.gtOp2, retClsHnd); } #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (op->gtType == TYP_STRUCT) + if (varTypeIsStruct(op)) { SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; eeGetSystemVAmd64PassStructInRegisterDescriptor(retClsHnd, &structDesc); @@ -7324,7 +7322,7 @@ REDO_RETURN_NODE: else #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING { - op->gtType = info.compRetNativeType; + op->gtType = info.compRetNativeType; } return op; @@ -11749,9 +11747,9 @@ DO_LDFTN: lclTyp = JITtype2varType(ciType); -#ifdef _TARGET_AMD64_ +#ifdef _TARGET_AMD64 noway_assert(varTypeIsIntegralOrI(lclTyp) || varTypeIsFloating(lclTyp) || lclTyp == TYP_STRUCT); -#endif // _TARGET_AMD64_ +#endif // TARGET_AMD64 if (compIsForInlining()) { @@ -12790,7 +12788,7 @@ FIELD_DONE: assert(helper == CORINFO_HELP_UNBOX_NULLABLE && "Make sure the helper is nullable!"); #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (op1->gtType == TYP_STRUCT) + if (varTypeIsStruct(op1)) { SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; eeGetSystemVAmd64PassStructInRegisterDescriptor(resolvedToken.hClass, &structDesc); @@ -12821,13 +12819,13 @@ FIELD_DONE: impPushOnStack(op1, tiRetVal); // Load the struct. - oper = GT_LDOBJ; + oper = GT_LDOBJ; assert(op1->gtType == TYP_BYREF); assert(!tiVerificationNeeded || tiRetVal.IsByRef()); - goto LDOBJ; - } + goto LDOBJ; + } else { // If non register passable struct we have it materialized in the RetBuf. @@ -13676,7 +13674,7 @@ GenTreePtr Compiler::impAssignStructClassToVar(GenTreePtr op, CORINFO_CLASS_HAND { unsigned tmpNum = lvaGrabTemp(true DEBUGARG("Return value temp for multireg structs.")); impAssignTempGen(tmpNum, op, hClass, (unsigned) CHECK_SPILL_NONE); - GenTreePtr ret = gtNewLclvNode(tmpNum, TYP_STRUCT); + GenTreePtr ret = gtNewLclvNode(tmpNum, op->gtType); #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) #ifdef DEBUG SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; @@ -13737,7 +13735,8 @@ bool Compiler::impReturnInstruction(BasicBlock *block, int prefixFlags, OPCODE & assertImp((genActualType(op2->TypeGet()) == genActualType(info.compRetType)) || ((op2->TypeGet() == TYP_I_IMPL) && (info.compRetType == TYP_BYREF)) || ((op2->TypeGet() == TYP_BYREF) && (info.compRetType == TYP_I_IMPL)) || - varTypeIsFloating(op2->gtType) && varTypeIsFloating(info.compRetType)); + (varTypeIsFloating(op2->gtType) && varTypeIsFloating(info.compRetType)) || + (varTypeIsStruct(op2) && varTypeIsStruct(info.compRetType))); #ifdef DEBUG if (opts.compGcChecks && info.compRetType == TYP_REF) diff --git a/src/jit/lclvars.cpp b/src/jit/lclvars.cpp index 675be90..3f7c3f0 100644 --- a/src/jit/lclvars.cpp +++ b/src/jit/lclvars.cpp @@ -449,7 +449,7 @@ void Compiler::lvaInitRetBuffArg(InitVarDscInfo * varDscInfo) bool hasRetBuffArg = impMethodInfo_hasRetBuffArg(info.compMethodInfo); #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (info.compRetNativeType == TYP_STRUCT) + if (varTypeIsStruct(info.compRetNativeType)) { if (IsRegisterPassable(info.compMethodInfo->args.retTypeClass)) { @@ -561,7 +561,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) #ifdef _TARGET_ARM_ - var_types hfaType = (argType == TYP_STRUCT) ? GetHfaType(typeHnd) : TYP_UNDEF; + var_types hfaType = (varTypeIsStruct(argType) ? GetHfaType(typeHnd) : TYP_UNDEF; bool isHfaArg = !info.compIsVarArgs && varTypeIsFloating(hfaType); // On ARM we pass the first 4 words of integer arguments and non-HFA structs in registers. @@ -652,7 +652,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) #else // !_TARGET_ARM_ #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { assert(typeHnd != nullptr); eeGetSystemVAmd64PassStructInRegisterDescriptor(typeHnd, &structDesc); @@ -700,7 +700,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) bool canPassArgInRegisters = false; #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { canPassArgInRegisters = structDesc.passedInRegisters; } @@ -728,7 +728,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) var_types firstEightByteType = TYP_UNDEF; var_types secondEightByteType = TYP_UNDEF; - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { if (structDesc.eightByteCount >= 1) { @@ -754,7 +754,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) varDsc->lvIsRegArg = 1; #if FEATURE_MULTIREG_STRUCT_ARGS - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) varDsc->lvArgReg = genMapRegArgNumToRegNum(firstAllocatedRegArgNum, firstEightByteType); @@ -806,7 +806,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // In case of one eightbyte struct the type is already normalized earlier. // The varTypeIsFloating(argType) is good for this case. - if ((argType == TYP_STRUCT) && (structDesc.eightByteCount >= 1)) + if (varTypeIsStruct(argType) && (structDesc.eightByteCount >= 1)) { isFloat = varTypeIsFloating(firstEightByteType); } @@ -818,7 +818,7 @@ void Compiler::lvaInitUserArgs(InitVarDscInfo * varDscInfo) #endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (argType == TYP_STRUCT) + if (varTypeIsStruct(argType)) { // Print both registers, just to be clear if (firstEightByteType == TYP_UNDEF) @@ -1142,7 +1142,7 @@ void Compiler::lvaInitVarDsc(LclVarDsc * varDsc, // we don't want the EE to assert in lvaSetStruct on bad sigs, so change // the JIT type to avoid even trying to call back - if (type == TYP_STRUCT && varDsc->lvVerTypeInfo.IsDead()) + if (varTypeIsStruct(type) && varDsc->lvVerTypeInfo.IsDead()) type = TYP_VOID; } @@ -1169,7 +1169,7 @@ void Compiler::lvaInitVarDsc(LclVarDsc * varDsc, varDsc->lvStructGcCount = 1; // Set the lvType (before this point it is TYP_UNDEF). - if (type == TYP_STRUCT) + if ((varTypeIsStruct(type))) { lvaSetStruct(varNum, typeHnd, typeHnd!=NULL, !tiVerificationNeeded); } @@ -1893,7 +1893,7 @@ void Compiler::lvaSetVarDoNotEnregister(unsigned varNum DEBUG_ARG( } /***************************************************************************** - * Set the lvClass for a local variable of TYP_STRUCT */ + * Set the lvClass for a local variable of a struct type */ void Compiler::lvaSetStruct(unsigned varNum, CORINFO_CLASS_HANDLE typeHnd, bool unsafeValueClsCheck, bool setTypeInfo) { @@ -1904,15 +1904,18 @@ void Compiler::lvaSetStruct(unsigned varNum, CORINFO_CLASS_HANDLE typeHnd, boo varDsc->lvVerTypeInfo = typeInfo(TI_STRUCT, typeHnd); // Set the type and associated info if we haven't already set it. - if ((varDsc->lvType == TYP_UNDEF) || (varDsc->lvType = TYP_STRUCT)) + var_types structType = varDsc->lvType; + if (varDsc->lvType == TYP_UNDEF) + { + varDsc->lvType = TYP_STRUCT; + } + if (varDsc->lvExactSize == 0) { - varDsc->lvType = TYP_STRUCT; - varDsc->lvExactSize = info.compCompHnd->getClassSize(typeHnd); size_t lvSize = varDsc->lvSize(); assert((lvSize % sizeof(void*)) == 0); // The struct needs to be a multiple of sizeof(void*) bytes for getClassGClayout() to be valid. - varDsc->lvGcLayout = (BYTE*) compGetMemA((lvSize / sizeof(void*)) * sizeof(BYTE), CMK_LvaTable); + varDsc->lvGcLayout = (BYTE*)compGetMemA((lvSize / sizeof(void*)) * sizeof(BYTE), CMK_LvaTable); unsigned numGCVars; var_types simdBaseType = TYP_UNKNOWN; varDsc->lvType = impNormStructType(typeHnd, varDsc->lvGcLayout, &numGCVars, &simdBaseType); @@ -1933,6 +1936,9 @@ void Compiler::lvaSetStruct(unsigned varNum, CORINFO_CLASS_HANDLE typeHnd, boo else { assert(varDsc->lvExactSize != 0); +#if FEATURE_SIMD + assert(!varTypeIsSIMD(varDsc) || (varDsc->lvBaseType != TYP_UNKNOWN)); +#endif // FEATURE_SIMD } #ifndef _TARGET_64BIT_ @@ -3036,8 +3042,8 @@ void Compiler::lvaMarkLclRefs(GenTreePtr tree) bool allowStructs = false; #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - // On System V the type of the var could be a TYP_STRUCT. - allowStructs = varDsc->lvType == TYP_STRUCT; + // On System V the type of the var could be a struct type. + allowStructs = varTypeIsStruct(varDsc); #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING /* Variables must be used as the same type throughout the method */ @@ -4300,7 +4306,7 @@ int Compiler::lvaAssignVirtualFrameOffsetToArg(unsigned lclNum, unsigned argSize varDsc->lvStkOffs = *callerArgOffset; // Structs passed on stack could be of size less than TARGET_POINTER_SIZE. // Make sure they get at least TARGET_POINTER_SIZE on the stack - this is required for alignment. - if (varDsc->lvType == TYP_STRUCT) + if (argSize > TARGET_POINTER_SIZE) { *callerArgOffset += (int)roundUp(argSize, TARGET_POINTER_SIZE); } @@ -5310,9 +5316,9 @@ int Compiler::lvaAllocLocalAndSetVirtualOffset(unsigned lclNum, unsigned size, i // alignment padding unsigned pad = 0; #if defined(FEATURE_SIMD) && ALIGN_SIMD_TYPES - if (lclVarIsSIMDType(lclNum)) + if (lclVarIsSIMDType(lclNum) && !lvaIsImplicitByRefLocal(lclNum)) { - int alignment = getSIMDTypeAlignment(lvaTable[lclNum].lvVerTypeInfo.GetClassHandle()); + int alignment = getSIMDTypeAlignment(lvaTable[lclNum].lvType); if (stkOffs % alignment != 0) { diff --git a/src/jit/lower.cpp b/src/jit/lower.cpp index ba06a4d..68fa2c3 100644 --- a/src/jit/lower.cpp +++ b/src/jit/lower.cpp @@ -1109,7 +1109,7 @@ GenTreePtr Lowering::NewPutArg(GenTreeCall* call, GenTreePtr arg, fgArgTabEntryP bool isOnStack = true; #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (type == TYP_STRUCT) + if (varTypeIsStruct(type)) { isOnStack = !fp->structDesc.passedInRegisters; } @@ -1249,7 +1249,7 @@ GenTreePtr Lowering::NewPutArg(GenTreeCall* call, GenTreePtr arg, fgArgTabEntryP // This provides the info to put this argument in in-coming arg area slot // instead of in out-going arg area slot. - FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY(assert(fp->isStruct == (type == TYP_STRUCT))); // Make sure state is correct + FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY(assert(fp->isStruct == varTypeIsStruct(type))); // Make sure state is correct #if FEATURE_FASTTAILCALL putArg = new (comp, GT_PUTARG_STK) GenTreePutArgStk(GT_PUTARG_STK, @@ -1280,11 +1280,19 @@ GenTreePtr Lowering::NewPutArg(GenTreeCall* call, GenTreePtr arg, fgArgTabEntryP // pair copying using XMM registers or rep mov instructions. if (fp->isStruct) { - assert(arg->OperGet() == GT_LDOBJ); - + unsigned numRefs = 0; BYTE* gcLayout = new (comp, CMK_Codegen) BYTE[fp->numSlots]; - - unsigned numRefs = comp->info.compCompHnd->getClassGClayout(arg->gtLdObj.gtClass, gcLayout); + // We use GT_LDOBJ for non-SIMD struct arguments. However, for + // SIMD arguments the GT_LDOBJ has already been transformed. + if (arg->gtOper != GT_LDOBJ) + { + assert(varTypeIsSIMD(arg)); + } + else + { + assert(!varTypeIsSIMD(arg)); + numRefs = comp->info.compCompHnd->getClassGClayout(arg->gtLdObj.gtClass, gcLayout); + } putArg->AsPutArgStk()->setGcPointers(numRefs, gcLayout); } diff --git a/src/jit/lowerxarch.cpp b/src/jit/lowerxarch.cpp index 369f81b..dc9cff4 100644 --- a/src/jit/lowerxarch.cpp +++ b/src/jit/lowerxarch.cpp @@ -298,7 +298,7 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) #endif // !defined(_TARGET_64BIT_) { #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - if (tree->TypeGet() == TYP_STRUCT && + if (varTypeIsStruct(tree) && tree->gtOp.gtOp1->OperGet() == GT_LCL_VAR) { #ifdef DEBUG @@ -876,7 +876,8 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) } // Set destination candidates for return value of the call. - if (varTypeIsFloating(registerType)) + if (varTypeIsFloating(registerType) + FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY( || varTypeIsSIMD(registerType))) { #ifdef _TARGET_X86_ // The return value will be on the X87 stack, and we will need to move it. @@ -938,13 +939,14 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) argNode->gtLsraInfo.dstCount = 0; #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING - // If the node is a struct and it is put on stack with + // If the node is TYP_STRUCT and it is put on stack with // putarg_stk operation, we consume and produce no registers. // In this case the embedded LdObj node should not produce // registers too since it is contained. + // Note that if it is a SIMD type the argument will be in a register. if (argNode->TypeGet() == TYP_STRUCT) { - assert(argNode != nullptr && argNode->gtOp.gtOp1 != nullptr && argNode->gtOp.gtOp1->OperGet() == GT_LDOBJ); + assert(argNode->gtOp.gtOp1 != nullptr && argNode->gtOp.gtOp1->OperGet() == GT_LDOBJ); argNode->gtOp.gtOp1->gtLsraInfo.dstCount = 0; argNode->gtLsraInfo.srcCount = 0; } @@ -978,7 +980,7 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) // If the struct arg is wraped in CPYBLK the type of the param will be TYP_VOID. // Use the curArgTabEntry's isStruct to get whether the param is a struct. - if (argNode->TypeGet() == TYP_STRUCT + if (varTypeIsStruct(argNode) FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY(|| curArgTabEntry->isStruct)) { unsigned originalSize = 0; @@ -1213,18 +1215,27 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) GenTreePutArgStk* putArgStkTree = tree->AsPutArgStk(); - GenTreePtr dstAddr = tree; - GenTreePtr srcAddr = tree->gtOp.gtOp1; + GenTreePtr dst = tree; + GenTreePtr src = tree->gtOp.gtOp1; + GenTreePtr srcAddr = nullptr; - assert(srcAddr->OperGet() == GT_LDOBJ); - info->srcCount = srcAddr->gtLsraInfo.dstCount; + if ((src->OperGet() == GT_LDOBJ) || (src->OperGet() == GT_IND)) + { + srcAddr = src->gtOp.gtOp1; + } + else + { + assert(varTypeIsSIMD(tree)); + } + info->srcCount = src->gtLsraInfo.dstCount; // If this is a stack variable address, // make the op1 contained, so this way // there is no unnecessary copying between registers. // To avoid assertion, increment the parent's source. // It is recovered below. - if (srcAddr->gtGetOp1()->OperIsLocalAddr()) + bool haveLocalAddr = ((srcAddr != nullptr) && (srcAddr->OperIsLocalAddr())); + if (haveLocalAddr) { info->srcCount += 1; } @@ -1278,9 +1289,9 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) info->addInternalCandidates(l, l->internalFloatRegCandidates()); } - if (srcAddr->gtGetOp1()->OperIsLocalAddr()) + if (haveLocalAddr) { - MakeSrcContained(putArgStkTree, srcAddr->gtGetOp1()); + MakeSrcContained(putArgStkTree, srcAddr); } // If src or dst are on stack, we don't have to generate the address into a register @@ -1291,19 +1302,19 @@ void Lowering::TreeNodeInfoInit(GenTree* stmt) { info->internalIntCount += 3; info->setInternalCandidates(l, (RBM_RDI | RBM_RCX | RBM_RSI)); - if (srcAddr->gtGetOp1()->OperIsLocalAddr()) + if (haveLocalAddr) { - MakeSrcContained(putArgStkTree, srcAddr->gtGetOp1()); + MakeSrcContained(putArgStkTree, srcAddr); } putArgStkTree->gtPutArgStkKind = GenTreePutArgStk::PutArgStkKindRepInstr; } // Always mark the LDOBJ and ADDR as contained trees by the putarg_stk. The codegen will deal with this tree. - MakeSrcContained(putArgStkTree, srcAddr); + MakeSrcContained(putArgStkTree, src); // Balance up the inc above. - if (srcAddr->gtGetOp1()->OperIsLocalAddr()) + if (haveLocalAddr) { info->srcCount -= 1; } diff --git a/src/jit/lsra.cpp b/src/jit/lsra.cpp index 7881563..eb8b27c 100644 --- a/src/jit/lsra.cpp +++ b/src/jit/lsra.cpp @@ -3316,7 +3316,7 @@ LinearScan::insertZeroInitRefPositions() void LinearScan::unixAmd64UpdateRegStateForArg(LclVarDsc* argDsc) { - assert(argDsc->lvType == TYP_STRUCT); + assert(varTypeIsStruct(argDsc)); RegState * intRegState = &compiler->codeGen->intRegState; RegState * floatRegState = &compiler->codeGen->floatRegState; @@ -3377,7 +3377,7 @@ LinearScan::updateRegStateForArg(LclVarDsc* argDsc) #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // For System V AMD64 calls the argDsc can have 2 registers (for structs.) // Handle them here. - if (argDsc->lvType == TYP_STRUCT) + if (varTypeIsStruct(argDsc)) { unixAmd64UpdateRegStateForArg(argDsc); } diff --git a/src/jit/morph.cpp b/src/jit/morph.cpp index 35d8b1b..ca9d9e4 100644 --- a/src/jit/morph.cpp +++ b/src/jit/morph.cpp @@ -1178,7 +1178,7 @@ fgArgTabEntryPtr fgArgInfo::AddRegArg(unsigned argNum, // PlaceHolder node (in case of needed late argument, for example.) // This requires using of an extra flag. At creation time the state is right, so // and this assert enforces that. - assert((node->gtType == TYP_STRUCT && isStruct) || (node->gtType != TYP_STRUCT && !isStruct)); + assert((varTypeIsStruct(node) && isStruct) || (!varTypeIsStruct(node) && !isStruct)); curArgTabEntry->otherRegNum = otherRegNum; // Second reg for the struct curArgTabEntry->isStruct = isStruct; // is this a struct arg @@ -1207,7 +1207,7 @@ fgArgTabEntryPtr fgArgInfo::AddStkArg(unsigned argNum, // PlaceHolder node (in case of needed late argument, for example.) // This reqires using of an extra flag. At creation time the state is right, so // and this assert enforces that. - assert((node->gtType == TYP_STRUCT && isStruct) || (node->gtType != TYP_STRUCT && !isStruct)); + assert((varTypeIsStruct(node) && isStruct) || (!varTypeIsStruct(node) && !isStruct)); curArgTabEntry->isStruct = isStruct; // is this a struct arg #endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) @@ -1454,7 +1454,7 @@ void fgArgInfo::ArgsComplete() // In case of copyblk and store operation, the NewPutArg method will // not be invoked and the struct will not be loaded to be passed in // registers or by value on the stack. - if (argx->TypeGet() == TYP_STRUCT FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY( || curArgTabEntry->isStruct)) + if (varTypeIsStruct(argx) FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY( || curArgTabEntry->isStruct)) { curArgTabEntry->needTmp = true; } @@ -1471,7 +1471,7 @@ void fgArgInfo::ArgsComplete() continue; #endif } - else // we have a register argument, next we look for a TYP_STRUCT + else // we have a register argument, next we look for a struct type. { if (varTypeIsStruct(argx) FEATURE_UNIX_AMD64_STRUCT_PASSING_ONLY( || curArgTabEntry->isStruct)) @@ -2017,7 +2017,7 @@ GenTreePtr Compiler::fgMakeTmpArgNode(unsigned tmpVarNum } else { - arg = gtNewOperNode(GT_ADDR, TYP_STRUCT, arg); + arg = gtNewOperNode(GT_ADDR, type, arg); addrNode = arg; } @@ -2891,7 +2891,7 @@ GenTreeCall* Compiler::fgMorphArgs(GenTreeCall* callNode) #ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING if (!hasStructArgument) { - hasStructArgument = (args->gtOp.gtOp1->TypeGet() == TYP_STRUCT); + hasStructArgument = varTypeIsStruct(args->gtOp.gtOp1); } #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING argx = fgMorphTree(*parentArgx); @@ -3193,7 +3193,7 @@ GenTreeCall* Compiler::fgMorphArgs(GenTreeCall* callNode) #ifndef _TARGET_X86_ #ifndef FEATURE_UNIX_AMD64_STRUCT_PASSING - // Check for TYP_STRUCT argument with size 1, 2, 4 or 8 bytes + // Check for struct argument with size 1, 2, 4 or 8 bytes // As we can optimize these by turning them into a GT_IND of the correct type if ((originalSize > TARGET_POINTER_SIZE) || ((originalSize & (originalSize - 1)) != 0)) #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING @@ -3346,7 +3346,7 @@ GenTreeCall* Compiler::fgMorphArgs(GenTreeCall* callNode) #endif // FEATURE_UNIX_AMD64_STRUCT_PASSING #endif // not _TARGET_X86_ - // We still have a TYP_STRUCT unless we converted the GT_LDOBJ into a GT_IND above... + // We still have a struct unless we converted the GT_LDOBJ into a GT_IND above... if ((structBaseType == TYP_STRUCT) && #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) !passStructInRegisters @@ -4006,10 +4006,11 @@ void Compiler::fgMorphSystemVStructArgs(GenTreeCall* call, bool hasStructArgumen var_types type = arg->TypeGet(); - if (type == TYP_STRUCT) + if (varTypeIsStruct(type)) { + var_types originalType = type; // If we have already processed the arg... - if (arg->OperGet() == GT_LIST && arg->TypeGet() == TYP_STRUCT) + if (arg->OperGet() == GT_LIST && varTypeIsStruct(arg)) { continue; } @@ -4050,7 +4051,7 @@ void Compiler::fgMorphSystemVStructArgs(GenTreeCall* call, bool hasStructArgumen lclCommon->gtLclNum, fgEntryPtr->structDesc.eightByteOffsets[1]); GenTreeArgList* secondNode = gtNewListNode(newLclField, nullptr); - secondNode->gtType = TYP_STRUCT; // Preserve the TYP_STRUCT. It is a special case. + secondNode->gtType = originalType; // Preserve the type. It is a special case. newLclField->gtFieldSeq = FieldSeqStore::NotAField(); // First field @@ -4059,7 +4060,7 @@ void Compiler::fgMorphSystemVStructArgs(GenTreeCall* call, bool hasStructArgumen fgEntryPtr->structDesc.eightByteClassifications[0], fgEntryPtr->structDesc.eightByteSizes[0]); arg = gtNewListNode(arg, secondNode); - arg->gtType = TYP_STRUCT; // Preserve the TYP_STRUCT. It is a special case. + arg->gtType = type; // Preserve the type. It is a special case. } else { @@ -4079,8 +4080,6 @@ void Compiler::fgMorphSystemVStructArgs(GenTreeCall* call, bool hasStructArgumen } else { - arg->gtType = TYP_I_IMPL; - // Make sure this is an addr node. if (arg->OperGet() != GT_ADDR && arg->OperGet() != GT_LCL_VAR_ADDR) { @@ -4090,7 +4089,7 @@ void Compiler::fgMorphSystemVStructArgs(GenTreeCall* call, bool hasStructArgumen assert(arg->OperGet() == GT_ADDR || arg->OperGet() == GT_LCL_VAR_ADDR); // Ldobj the temp to use it as a call argument - arg = new (this, GT_LDOBJ) GenTreeLdObj(TYP_STRUCT, arg, lvaGetStruct(lclCommon->gtLclNum)); + arg = new (this, GT_LDOBJ) GenTreeLdObj(originalType, arg, lvaGetStruct(lclCommon->gtLclNum)); arg->gtFlags |= GTF_EXCEPT; flagsSummary |= GTF_EXCEPT; } @@ -4326,13 +4325,13 @@ void Compiler::fgFixupStructReturn(GenTreePtr call) #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; - if (!callHasRetBuffArg && call->TypeGet() == TYP_STRUCT && call->gtCall.gtRetClsHnd != NO_CLASS_HANDLE) + if (!callHasRetBuffArg && varTypeIsStruct(call) && call->gtCall.gtRetClsHnd != NO_CLASS_HANDLE) { - eeGetSystemVAmd64PassStructInRegisterDescriptor(GetStructClassHandle(call), &structDesc); + eeGetSystemVAmd64PassStructInRegisterDescriptor(gtGetStructHandleIfPresent(call), &structDesc); } #endif // defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) - if (!callHasRetBuffArg && call->TypeGet() == TYP_STRUCT) + if (!callHasRetBuffArg && (varTypeIsStruct(call))) { #if defined(_TARGET_ARM_) if (call->gtCall.IsVarargs() || !IsHfa(call)) @@ -4356,11 +4355,11 @@ void Compiler::fgFixupStructReturn(GenTreePtr call) } #ifdef _TARGET_ARM_ // Either we don't have a struct now or if struct, then it is HFA returned in regs. - assert(call->TypeGet() != TYP_STRUCT || (IsHfa(call) && !callHasRetBuffArg)); + assert(varTypeIsStruct(call) || (IsHfa(call) && !callHasRetBuffArg)); #else #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // Either we don't have a struct now or if struct, then it is a struct returned in regs or in return buffer. - assert((call->TypeGet() != TYP_STRUCT) || + assert(!varTypeIsStruct(call) || (structDesc.passedInRegisters) || (callHasRetBuffArg)); #else // !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) @@ -4371,7 +4370,7 @@ void Compiler::fgFixupStructReturn(GenTreePtr call) #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // If there is a struct that is returned in registers there might be a retbuf (homing space for the return) and type struct. - assert(!callHasRetBuffArg || (call->TypeGet() == TYP_VOID) || (call->TypeGet() == TYP_STRUCT)); + assert(!callHasRetBuffArg || (call->TypeGet() == TYP_VOID) || varTypeIsStruct(call)); #else // !defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // If it was a struct return, it has been transformed into a call // with a return buffer (that returns TYP_VOID) or into a return @@ -4623,7 +4622,7 @@ GenTreePtr Compiler::fgMorphArrayIndex(GenTreePtr tree) noway_assert(elemTyp != TYP_STRUCT || elemStructType != nullptr); #ifdef FEATURE_SIMD - if (featureSIMD && elemTyp == TYP_STRUCT && elemSize <= getSIMDVectorRegisterByteLength()) + if (featureSIMD && varTypeIsStruct(elemTyp) && elemSize <= getSIMDVectorRegisterByteLength()) { // If this is a SIMD type, this is the point at which we lose the type information, // so we need to set the correct type on the GT_IND. @@ -5803,7 +5802,7 @@ bool Compiler::fgCanFastTailCall(GenTreeCall* callee) #ifdef _TARGET_AMD64_ unsigned typeSize = 0; - hasMultiByteArgs = !VarTypeIsMultiByteAndCanEnreg(TYP_STRUCT, argx->gtLdObj.gtClass, &typeSize, false); + hasMultiByteArgs = !VarTypeIsMultiByteAndCanEnreg(argx->TypeGet(), argx->gtLdObj.gtClass, &typeSize, false); #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // On System V the args could be a 2 eightbyte struct that is passed in two registers. @@ -6825,9 +6824,10 @@ GenTreePtr Compiler::fgMorphCall(GenTreeCall* call) } #elif defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) // Return a dummy node, as the return is already removed. - if (callType == TYP_STRUCT) + if (varTypeIsStruct(callType)) { - // This is an register-returned struct. Return a 0. + // This is a register-returned struct. Return a 0. + // The actual return registers are hacked in lower and the register allocator. callType = TYP_INT; } #endif @@ -7672,7 +7672,7 @@ GenTreePtr Compiler::fgMorphInitBlock(GenTreePtr tree) noway_assert(initVal->OperGet() == GT_CNS_INT); noway_assert(genActualType(initVal->gtType) == TYP_INT); - // The dest must be of TYP_STRUCT + // The dest must be of a struct type. noway_assert(varTypeIsStruct(destLclVar)); // diff --git a/src/jit/optcse.cpp b/src/jit/optcse.cpp index 3c19dcb..40aee01 100644 --- a/src/jit/optcse.cpp +++ b/src/jit/optcse.cpp @@ -1654,8 +1654,11 @@ public: // we will create a long lifetime temp for the new cse LclVar unsigned cseLclVarNum = m_pCompiler->lvaGrabTemp(false DEBUGARG("ValNumCSE")); - var_types cseLclVarTyp = genActualType(successfulCandidate->Expr()->TypeGet()); - + var_types cseLclVarTyp = genActualType(successfulCandidate->Expr()->TypeGet()); + if (varTypeIsStruct(cseLclVarTyp)) + { + m_pCompiler->lvaSetStruct(cseLclVarNum, m_pCompiler->gtGetStructHandle(successfulCandidate->Expr()), false); + } m_pCompiler->lvaTable[cseLclVarNum].lvType = cseLclVarTyp; m_pCompiler->lvaTable[cseLclVarNum].lvIsCSE = true; @@ -2127,7 +2130,9 @@ bool Compiler::optIsCSEcandidate(GenTreePtr tree) var_types type = tree->TypeGet(); genTreeOps oper = tree->OperGet(); - if (type == TYP_STRUCT || type == TYP_VOID) + // TODO-1stClassStructs: Enable CSE for TYP_SIMD (depends on either transforming + // to use regular assignments, or handling copyObj. + if (varTypeIsStruct(type) || type == TYP_VOID) return false; #ifdef _TARGET_X86_ diff --git a/src/jit/rationalize.cpp b/src/jit/rationalize.cpp index 95cd783..38868a8 100644 --- a/src/jit/rationalize.cpp +++ b/src/jit/rationalize.cpp @@ -1555,19 +1555,21 @@ void Rationalizer::RewriteLdObj(GenTreePtr* ppTree, Compiler::fgWalkData* data) { #ifdef FEATURE_SIMD Compiler* comp = data->compiler; + GenTreeLdObj* ldObj = (*ppTree)->AsLdObj(); + // For UNIX struct passing, we can have LdObj nodes for arguments. + // For other cases, we should never see a non-SIMD type here. +#ifdef FEATURE_UNIX_AMD64_STRUCT_PASSING + if (!varTypeIsSIMD(ldObj)) + { + return; + } +#endif // FEATURE_UNIX_AMD64_STRUCT_PASSING // Should come here only if featureSIMD is enabled noway_assert(comp->featureSIMD); - - GenTreeLdObj* ldObj = (*ppTree)->AsLdObj(); - assert(ldObj->OperGet() == GT_LDOBJ); - - unsigned simdSize = 0; - var_types baseType = comp->getBaseTypeAndSizeOfSIMDType(ldObj->gtClass, &simdSize); - assert(baseType != TYP_UNKNOWN); - var_types simdType = comp->getSIMDTypeForSize(simdSize); - - assert(ldObj->TypeGet() == TYP_STRUCT || ldObj->TypeGet() == simdType); + // On we should only call this with a SIMD type. + noway_assert(varTypeIsSIMD(ldObj)); + var_types simdType = ldObj->TypeGet(); // If the operand of ldobj is a GT_ADDR(GT_LCL_VAR) and LclVar is known to be a SIMD type, // replace ldobj by GT_LCL_VAR. @@ -1596,6 +1598,7 @@ void Rationalizer::RewriteLdObj(GenTreePtr* ppTree, Compiler::fgWalkData* data) { comp->fgSnipInnerNode(ldObj); } + comp->fgFixupIfCallArg(data->parentStack, ldObj, src); src->gtType = simdType; *ppTree = src; @@ -1965,6 +1968,10 @@ Compiler::fgWalkResult Rationalizer::SimpleTransformHelper(GenTree **ppTree, Com unsigned simdSize = 0; switch(tree->gtOper) { + default: + // Nothing to do for most nodes. + break; + case GT_INITBLK: RewriteInitBlk(ppTree, data); break; @@ -2064,7 +2071,6 @@ Compiler::fgWalkResult Rationalizer::SimpleTransformHelper(GenTree **ppTree, Com } } } - break; } if ((*ppTree) != tree) @@ -2109,6 +2115,10 @@ void Rationalizer::FixupIfSIMDLocal(Compiler* comp, GenTreeLclVarCommon* tree) } switch(tree->OperGet()) { + default: + // Nothing to do for most tree nodes. + break; + case GT_LCL_FLD: // We may see a lclFld used for pointer-sized structs that have been morphed, in which // case we can change it to GT_LCL_VAR. @@ -2124,8 +2134,9 @@ void Rationalizer::FixupIfSIMDLocal(Compiler* comp, GenTreeLclVarCommon* tree) } else { - // If we access a field of a SIMD lclVar via GT_LCL_FLD, it must not have been promoted. - assert(varDsc->lvPromoted == false); + // If we access a field of a SIMD lclVar via GT_LCL_FLD, it cannot have been + // independently promoted. + assert(comp->lvaGetPromotionType(varDsc) != Compiler::PROMOTION_TYPE_INDEPENDENT); return; } break; diff --git a/src/jit/scopeinfo.cpp b/src/jit/scopeinfo.cpp index c235dc4..3935141 100644 --- a/src/jit/scopeinfo.cpp +++ b/src/jit/scopeinfo.cpp @@ -949,7 +949,7 @@ void CodeGen::psiBegProlog() bool isStructHandled = false; #if defined(FEATURE_UNIX_AMD64_STRUCT_PASSING) SYSTEMV_AMD64_CORINFO_STRUCT_REG_PASSING_DESCRIPTOR structDesc; - if (lclVarDsc1->TypeGet() == TYP_STRUCT) + if (varTypeIsStruct(lclVarDsc1)) { CORINFO_CLASS_HANDLE typeHnd = lclVarDsc1->lvVerTypeInfo.GetClassHandle(); assert(typeHnd != nullptr); diff --git a/src/jit/simd.cpp b/src/jit/simd.cpp index c90a70e..84944cf 100644 --- a/src/jit/simd.cpp +++ b/src/jit/simd.cpp @@ -79,15 +79,13 @@ int Compiler::getSIMDVectorLength(CORINFO_CLASS_HANDLE typeHnd) // Arguments: // typeHnd - type handle of the SIMD vector // -int Compiler::getSIMDTypeAlignment(CORINFO_CLASS_HANDLE typeHnd) +int Compiler::getSIMDTypeAlignment(var_types simdType) { #ifdef _TARGET_AMD64_ // Fixed length vectors have the following alignment preference // Vector2/3 = 8 byte alignment // Vector4 = 16-byte alignment - unsigned size = 0; - var_types baseType = getBaseTypeAndSizeOfSIMDType(typeHnd, &size); - noway_assert(baseType != TYP_UNKNOWN); + unsigned size = genTypeSize(simdType); // preferred alignment for SSE2 128-bit vectors is 16-bytes if (size == 8) @@ -225,7 +223,7 @@ var_types Compiler::getBaseTypeAndSizeOfSIMDType(CORINFO_CLASS_HANDLE typeHnd, // Obtain base type by parsing fully qualified class name. // // TODO-Throughput: implement product shipping solution to query base type. - WCHAR className[256] = {'\\0'}; + WCHAR className[256] = {0}; WCHAR *pbuf = &className[0]; int len = sizeof(className)/sizeof(className[0]); info.compCompHnd->appendClassName(&pbuf, &len, typeHnd, TRUE, FALSE, FALSE); @@ -1103,6 +1101,9 @@ SIMDIntrinsicID Compiler::impSIMDRelOp(SIMDIntrinsicID relOpIntrinsicId, constVal = 0x8000000000000000LL; *inOutBaseType = TYP_LONG; break; + default: + unreached(); + break; } assert(constVal != 0); @@ -1174,8 +1175,8 @@ GenTreePtr Compiler::impSIMDSelect(CORINFO_CLASS_HANDLE typeHnd, if ((op1->gtFlags & GTF_SIDE_EFFECT) != 0) { unsigned lclNum = lvaGrabTemp(true DEBUGARG("SIMD Select")); - tmp = gtNewLclvNode(lclNum, op1->TypeGet()); lvaSetStruct(lclNum, typeHnd, false); + tmp = gtNewLclvNode(lclNum, op1->TypeGet()); asg = gtNewTempAssign(lclNum, op1); } @@ -1759,15 +1760,6 @@ GenTreePtr Compiler::impSIMDIntrinsic(OPCODE opcode, return nullptr; } - // For now SIMD Intrinsics are disabled in debuggable code. - // TODO-Cleanup: add support for SIMD intrinsics regardless of debuggable code. - // Note that we can't disable SIMD intrinsics if we are set to use AVX, because the - // reference implementation won't match the vector size. - if (!canUseAVX() && opts.compDbgCode) - { - return nullptr; - } - // Get base type and intrinsic Id var_types baseType = TYP_UNKNOWN; unsigned size = 0; diff --git a/src/jit/simd.h b/src/jit/simd.h index aef2fac..c4079e5 100644 --- a/src/jit/simd.h +++ b/src/jit/simd.h @@ -26,7 +26,7 @@ struct SIMDIntrinsicInfo const char *methodName; bool isInstMethod; var_types retType; - byte argCount; + unsigned char argCount; var_types argType[SIMD_INTRINSIC_MAX_MODELED_PARAM_COUNT]; var_types supportedBaseTypes[SIMD_INTRINSIC_MAX_BASETYPE_COUNT]; }; diff --git a/tests/src/JIT/SIMD/AbsGeneric.csproj b/tests/src/JIT/SIMD/AbsGeneric_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/AbsGeneric.csproj rename to tests/src/JIT/SIMD/AbsGeneric_r.csproj index 6b1e0a9..83f92d2 100644 --- a/tests/src/JIT/SIMD/AbsGeneric.csproj +++ b/tests/src/JIT/SIMD/AbsGeneric_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/AbsGeneric_ro.csproj b/tests/src/JIT/SIMD/AbsGeneric_ro.csproj new file mode 100644 index 0000000..ec28ab0 --- /dev/null +++ b/tests/src/JIT/SIMD/AbsGeneric_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/AbsSqrt.csproj b/tests/src/JIT/SIMD/AbsSqrt_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/AbsSqrt.csproj rename to tests/src/JIT/SIMD/AbsSqrt_r.csproj index ded20a3..1450a7b 100644 --- a/tests/src/JIT/SIMD/AbsSqrt.csproj +++ b/tests/src/JIT/SIMD/AbsSqrt_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/AbsSqrt_ro.csproj b/tests/src/JIT/SIMD/AbsSqrt_ro.csproj new file mode 100644 index 0000000..de32aea --- /dev/null +++ b/tests/src/JIT/SIMD/AbsSqrt_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/AddingSequence.csproj b/tests/src/JIT/SIMD/AddingSequence_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/AddingSequence.csproj rename to tests/src/JIT/SIMD/AddingSequence_r.csproj index 1a30c03..649b344 100644 --- a/tests/src/JIT/SIMD/AddingSequence.csproj +++ b/tests/src/JIT/SIMD/AddingSequence_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/AddingSequence_ro.csproj b/tests/src/JIT/SIMD/AddingSequence_ro.csproj new file mode 100644 index 0000000..be57bc5 --- /dev/null +++ b/tests/src/JIT/SIMD/AddingSequence_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/BitwiseOperations.csproj b/tests/src/JIT/SIMD/BitwiseOperations_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/BitwiseOperations.csproj rename to tests/src/JIT/SIMD/BitwiseOperations_r.csproj index d9835c3..0142042 100644 --- a/tests/src/JIT/SIMD/BitwiseOperations.csproj +++ b/tests/src/JIT/SIMD/BitwiseOperations_r.csproj @@ -19,12 +19,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/BitwiseOperations_ro.csproj b/tests/src/JIT/SIMD/BitwiseOperations_ro.csproj new file mode 100644 index 0000000..90e12df --- /dev/null +++ b/tests/src/JIT/SIMD/BitwiseOperations_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + true + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/BoxUnbox.csproj b/tests/src/JIT/SIMD/BoxUnbox_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/BoxUnbox.csproj rename to tests/src/JIT/SIMD/BoxUnbox_r.csproj index f8b3555..1cd110d 100644 --- a/tests/src/JIT/SIMD/BoxUnbox.csproj +++ b/tests/src/JIT/SIMD/BoxUnbox_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/BoxUnbox_ro.csproj b/tests/src/JIT/SIMD/BoxUnbox_ro.csproj new file mode 100644 index 0000000..6d1b23b --- /dev/null +++ b/tests/src/JIT/SIMD/BoxUnbox_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/BugWithAVX.csproj b/tests/src/JIT/SIMD/BugWithAVX_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/BugWithAVX.csproj rename to tests/src/JIT/SIMD/BugWithAVX_r.csproj index 55c2b23..1eb0731 100644 --- a/tests/src/JIT/SIMD/BugWithAVX.csproj +++ b/tests/src/JIT/SIMD/BugWithAVX_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/BugWithAVX_ro.csproj b/tests/src/JIT/SIMD/BugWithAVX_ro.csproj new file mode 100644 index 0000000..7aa673b --- /dev/null +++ b/tests/src/JIT/SIMD/BugWithAVX_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/CircleInConvex.csproj b/tests/src/JIT/SIMD/CircleInConvex_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/CircleInConvex.csproj rename to tests/src/JIT/SIMD/CircleInConvex_r.csproj index 8961ca6..a1ad4f1 100644 --- a/tests/src/JIT/SIMD/CircleInConvex.csproj +++ b/tests/src/JIT/SIMD/CircleInConvex_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/CircleInConvex_ro.csproj b/tests/src/JIT/SIMD/CircleInConvex_ro.csproj new file mode 100644 index 0000000..91a169a --- /dev/null +++ b/tests/src/JIT/SIMD/CircleInConvex_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/CreateGeneric.csproj b/tests/src/JIT/SIMD/CreateGeneric_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/CreateGeneric.csproj rename to tests/src/JIT/SIMD/CreateGeneric_r.csproj index 886e691..4d306b0 100644 --- a/tests/src/JIT/SIMD/CreateGeneric.csproj +++ b/tests/src/JIT/SIMD/CreateGeneric_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/CreateGeneric_ro.csproj b/tests/src/JIT/SIMD/CreateGeneric_ro.csproj new file mode 100644 index 0000000..e7d9c45 --- /dev/null +++ b/tests/src/JIT/SIMD/CreateGeneric_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/CtorFromArray.csproj b/tests/src/JIT/SIMD/CtorFromArray_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/CtorFromArray.csproj rename to tests/src/JIT/SIMD/CtorFromArray_r.csproj index 846c899..3fdf2d7 100644 --- a/tests/src/JIT/SIMD/CtorFromArray.csproj +++ b/tests/src/JIT/SIMD/CtorFromArray_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/CtorFromArray_ro.csproj b/tests/src/JIT/SIMD/CtorFromArray_ro.csproj new file mode 100644 index 0000000..145255b --- /dev/null +++ b/tests/src/JIT/SIMD/CtorFromArray_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Ctors.csproj b/tests/src/JIT/SIMD/Ctors_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Ctors.csproj rename to tests/src/JIT/SIMD/Ctors_r.csproj index af7ac71..4fe8970 100644 --- a/tests/src/JIT/SIMD/Ctors.csproj +++ b/tests/src/JIT/SIMD/Ctors_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Ctors_ro.csproj b/tests/src/JIT/SIMD/Ctors_ro.csproj new file mode 100644 index 0000000..488946d --- /dev/null +++ b/tests/src/JIT/SIMD/Ctors_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/DivSignedUnsignedTest.csproj b/tests/src/JIT/SIMD/DivSignedUnsignedTest_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/DivSignedUnsignedTest.csproj rename to tests/src/JIT/SIMD/DivSignedUnsignedTest_r.csproj index 62020b7..c053021 100644 --- a/tests/src/JIT/SIMD/DivSignedUnsignedTest.csproj +++ b/tests/src/JIT/SIMD/DivSignedUnsignedTest_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/DivSignedUnsignedTest_ro.csproj b/tests/src/JIT/SIMD/DivSignedUnsignedTest_ro.csproj new file mode 100644 index 0000000..9ad21ae --- /dev/null +++ b/tests/src/JIT/SIMD/DivSignedUnsignedTest_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Dup.csproj b/tests/src/JIT/SIMD/Dup_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Dup.csproj rename to tests/src/JIT/SIMD/Dup_r.csproj index 5510991..7399651 100644 --- a/tests/src/JIT/SIMD/Dup.csproj +++ b/tests/src/JIT/SIMD/Dup_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Dup_ro.csproj b/tests/src/JIT/SIMD/Dup_ro.csproj new file mode 100644 index 0000000..6cc99f7 --- /dev/null +++ b/tests/src/JIT/SIMD/Dup_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric.csproj b/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Haar-likeFeaturesGeneric.csproj rename to tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_r.csproj index ca8d42d..7f50914 100644 --- a/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric.csproj +++ b/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_ro.csproj b/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_ro.csproj new file mode 100644 index 0000000..e2d3b60 --- /dev/null +++ b/tests/src/JIT/SIMD/Haar-likeFeaturesGeneric_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/LdfldGeneric.csproj b/tests/src/JIT/SIMD/LdfldGeneric_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/LdfldGeneric.csproj rename to tests/src/JIT/SIMD/LdfldGeneric_r.csproj index 56ac720..0066ef4 100644 --- a/tests/src/JIT/SIMD/LdfldGeneric.csproj +++ b/tests/src/JIT/SIMD/LdfldGeneric_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/LdfldGeneric_ro.csproj b/tests/src/JIT/SIMD/LdfldGeneric_ro.csproj new file mode 100644 index 0000000..f48f758 --- /dev/null +++ b/tests/src/JIT/SIMD/LdfldGeneric_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Ldfld.csproj b/tests/src/JIT/SIMD/Ldfld_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Ldfld.csproj rename to tests/src/JIT/SIMD/Ldfld_r.csproj index 669922f..a373d88 100644 --- a/tests/src/JIT/SIMD/Ldfld.csproj +++ b/tests/src/JIT/SIMD/Ldfld_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Ldfld_ro.csproj b/tests/src/JIT/SIMD/Ldfld_ro.csproj new file mode 100644 index 0000000..2b059d1 --- /dev/null +++ b/tests/src/JIT/SIMD/Ldfld_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Ldind.csproj b/tests/src/JIT/SIMD/Ldind_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Ldind.csproj rename to tests/src/JIT/SIMD/Ldind_r.csproj index 3bf1cba..3c5ed5b 100644 --- a/tests/src/JIT/SIMD/Ldind.csproj +++ b/tests/src/JIT/SIMD/Ldind_r.csproj @@ -19,12 +19,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Ldind_ro.csproj b/tests/src/JIT/SIMD/Ldind_ro.csproj new file mode 100644 index 0000000..de2be11 --- /dev/null +++ b/tests/src/JIT/SIMD/Ldind_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + true + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/MinMax.csproj b/tests/src/JIT/SIMD/MinMax_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/MinMax.csproj rename to tests/src/JIT/SIMD/MinMax_r.csproj index 8eb2048..c9e9840 100644 --- a/tests/src/JIT/SIMD/MinMax.csproj +++ b/tests/src/JIT/SIMD/MinMax_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/MinMax_ro.csproj b/tests/src/JIT/SIMD/MinMax_ro.csproj new file mode 100644 index 0000000..3e357bb --- /dev/null +++ b/tests/src/JIT/SIMD/MinMax_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Mul.csproj b/tests/src/JIT/SIMD/Mul_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Mul.csproj rename to tests/src/JIT/SIMD/Mul_r.csproj index 367f37b..f6e2267 100644 --- a/tests/src/JIT/SIMD/Mul.csproj +++ b/tests/src/JIT/SIMD/Mul_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Mul_ro.csproj b/tests/src/JIT/SIMD/Mul_ro.csproj new file mode 100644 index 0000000..0f3c314 --- /dev/null +++ b/tests/src/JIT/SIMD/Mul_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/SqrtGeneric.csproj b/tests/src/JIT/SIMD/SqrtGeneric_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/SqrtGeneric.csproj rename to tests/src/JIT/SIMD/SqrtGeneric_r.csproj index 60a797d..df96674 100644 --- a/tests/src/JIT/SIMD/SqrtGeneric.csproj +++ b/tests/src/JIT/SIMD/SqrtGeneric_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/SqrtGeneric_ro.csproj b/tests/src/JIT/SIMD/SqrtGeneric_ro.csproj new file mode 100644 index 0000000..7cab498 --- /dev/null +++ b/tests/src/JIT/SIMD/SqrtGeneric_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/StoreElement.csproj b/tests/src/JIT/SIMD/StoreElement_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/StoreElement.csproj rename to tests/src/JIT/SIMD/StoreElement_r.csproj index 606d6c1..4435334 100644 --- a/tests/src/JIT/SIMD/StoreElement.csproj +++ b/tests/src/JIT/SIMD/StoreElement_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/StoreElement_ro.csproj b/tests/src/JIT/SIMD/StoreElement_ro.csproj new file mode 100644 index 0000000..1fe0583 --- /dev/null +++ b/tests/src/JIT/SIMD/StoreElement_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Sums.csproj b/tests/src/JIT/SIMD/Sums_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Sums.csproj rename to tests/src/JIT/SIMD/Sums_r.csproj index c5476a1..ebf46e7 100644 --- a/tests/src/JIT/SIMD/Sums.csproj +++ b/tests/src/JIT/SIMD/Sums_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Sums_ro.csproj b/tests/src/JIT/SIMD/Sums_ro.csproj new file mode 100644 index 0000000..ed2661f --- /dev/null +++ b/tests/src/JIT/SIMD/Sums_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Vector3.csproj b/tests/src/JIT/SIMD/Vector3_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Vector3.csproj rename to tests/src/JIT/SIMD/Vector3_r.csproj index e8a77b1..fdf5f3b 100644 --- a/tests/src/JIT/SIMD/Vector3.csproj +++ b/tests/src/JIT/SIMD/Vector3_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Vector3_ro.csproj b/tests/src/JIT/SIMD/Vector3_ro.csproj new file mode 100644 index 0000000..c80143d --- /dev/null +++ b/tests/src/JIT/SIMD/Vector3_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/Vector4.csproj b/tests/src/JIT/SIMD/Vector4_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/Vector4.csproj rename to tests/src/JIT/SIMD/Vector4_r.csproj index b8eb31c..ea2d667 100644 --- a/tests/src/JIT/SIMD/Vector4.csproj +++ b/tests/src/JIT/SIMD/Vector4_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -40,4 +46,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/Vector4_ro.csproj b/tests/src/JIT/SIMD/Vector4_ro.csproj new file mode 100644 index 0000000..c81daf0 --- /dev/null +++ b/tests/src/JIT/SIMD/Vector4_ro.csproj @@ -0,0 +1,49 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorAbs.csproj b/tests/src/JIT/SIMD/VectorAbs_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorAbs.csproj rename to tests/src/JIT/SIMD/VectorAbs_r.csproj index ed3bb87..8302fd0 100644 --- a/tests/src/JIT/SIMD/VectorAbs.csproj +++ b/tests/src/JIT/SIMD/VectorAbs_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorAbs_ro.csproj b/tests/src/JIT/SIMD/VectorAbs_ro.csproj new file mode 100644 index 0000000..459820c --- /dev/null +++ b/tests/src/JIT/SIMD/VectorAbs_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorAdd.csproj b/tests/src/JIT/SIMD/VectorAdd_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorAdd.csproj rename to tests/src/JIT/SIMD/VectorAdd_r.csproj index caba852..c593063 100644 --- a/tests/src/JIT/SIMD/VectorAdd.csproj +++ b/tests/src/JIT/SIMD/VectorAdd_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorAdd_ro.csproj b/tests/src/JIT/SIMD/VectorAdd_ro.csproj new file mode 100644 index 0000000..1ab5fd1 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorAdd_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorArgs.csproj b/tests/src/JIT/SIMD/VectorArgs_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorArgs.csproj rename to tests/src/JIT/SIMD/VectorArgs_r.csproj index e2aa8b6..100b241 100644 --- a/tests/src/JIT/SIMD/VectorArgs.csproj +++ b/tests/src/JIT/SIMD/VectorArgs_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorArgs_ro.csproj b/tests/src/JIT/SIMD/VectorArgs_ro.csproj new file mode 100644 index 0000000..9789fb0 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorArgs_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorArrayInit.csproj b/tests/src/JIT/SIMD/VectorArrayInit_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorArrayInit.csproj rename to tests/src/JIT/SIMD/VectorArrayInit_r.csproj index ae6901a..c276bac 100644 --- a/tests/src/JIT/SIMD/VectorArrayInit.csproj +++ b/tests/src/JIT/SIMD/VectorArrayInit_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorArrayInit_ro.csproj b/tests/src/JIT/SIMD/VectorArrayInit_ro.csproj new file mode 100644 index 0000000..5cc72fd --- /dev/null +++ b/tests/src/JIT/SIMD/VectorArrayInit_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorArray.csproj b/tests/src/JIT/SIMD/VectorArray_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorArray.csproj rename to tests/src/JIT/SIMD/VectorArray_r.csproj index 8a34448..a17236b 100644 --- a/tests/src/JIT/SIMD/VectorArray.csproj +++ b/tests/src/JIT/SIMD/VectorArray_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorArray_ro.csproj b/tests/src/JIT/SIMD/VectorArray_ro.csproj new file mode 100644 index 0000000..645d784 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorArray_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorCopyToArray.csproj b/tests/src/JIT/SIMD/VectorCopyToArray_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorCopyToArray.csproj rename to tests/src/JIT/SIMD/VectorCopyToArray_r.csproj index 0912c36..b1aa977 100644 --- a/tests/src/JIT/SIMD/VectorCopyToArray.csproj +++ b/tests/src/JIT/SIMD/VectorCopyToArray_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorCopyToArray_ro.csproj b/tests/src/JIT/SIMD/VectorCopyToArray_ro.csproj new file mode 100644 index 0000000..b726cc8 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorCopyToArray_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorDiv.csproj b/tests/src/JIT/SIMD/VectorDiv_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorDiv.csproj rename to tests/src/JIT/SIMD/VectorDiv_r.csproj index 99e6d81..54e2bd0 100644 --- a/tests/src/JIT/SIMD/VectorDiv.csproj +++ b/tests/src/JIT/SIMD/VectorDiv_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorDiv_ro.csproj b/tests/src/JIT/SIMD/VectorDiv_ro.csproj new file mode 100644 index 0000000..358307c --- /dev/null +++ b/tests/src/JIT/SIMD/VectorDiv_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorDot.csproj b/tests/src/JIT/SIMD/VectorDot_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorDot.csproj rename to tests/src/JIT/SIMD/VectorDot_r.csproj index a58e4f9..5ecb5d1 100644 --- a/tests/src/JIT/SIMD/VectorDot.csproj +++ b/tests/src/JIT/SIMD/VectorDot_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorDot_ro.csproj b/tests/src/JIT/SIMD/VectorDot_ro.csproj new file mode 100644 index 0000000..88a2aee --- /dev/null +++ b/tests/src/JIT/SIMD/VectorDot_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorExp.csproj b/tests/src/JIT/SIMD/VectorExp_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorExp.csproj rename to tests/src/JIT/SIMD/VectorExp_r.csproj index cde12b6..0d4c305 100644 --- a/tests/src/JIT/SIMD/VectorExp.csproj +++ b/tests/src/JIT/SIMD/VectorExp_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorExp_ro.csproj b/tests/src/JIT/SIMD/VectorExp_ro.csproj new file mode 100644 index 0000000..12f1d01 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorExp_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorGet.csproj b/tests/src/JIT/SIMD/VectorGet_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorGet.csproj rename to tests/src/JIT/SIMD/VectorGet_r.csproj index ab5e5fe..7275f10 100644 --- a/tests/src/JIT/SIMD/VectorGet.csproj +++ b/tests/src/JIT/SIMD/VectorGet_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorGet_ro.csproj b/tests/src/JIT/SIMD/VectorGet_ro.csproj new file mode 100644 index 0000000..7a6fe22 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorGet_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorHWAccel2.csproj b/tests/src/JIT/SIMD/VectorHWAccel2_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorHWAccel2.csproj rename to tests/src/JIT/SIMD/VectorHWAccel2_r.csproj index 790ecfc..6d52336 100644 --- a/tests/src/JIT/SIMD/VectorHWAccel2.csproj +++ b/tests/src/JIT/SIMD/VectorHWAccel2_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorHWAccel2_ro.csproj b/tests/src/JIT/SIMD/VectorHWAccel2_ro.csproj new file mode 100644 index 0000000..242ebce --- /dev/null +++ b/tests/src/JIT/SIMD/VectorHWAccel2_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorHWAccel.csproj b/tests/src/JIT/SIMD/VectorHWAccel_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorHWAccel.csproj rename to tests/src/JIT/SIMD/VectorHWAccel_r.csproj index f2d7114..c5397b5 100644 --- a/tests/src/JIT/SIMD/VectorHWAccel.csproj +++ b/tests/src/JIT/SIMD/VectorHWAccel_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorHWAccel_ro.csproj b/tests/src/JIT/SIMD/VectorHWAccel_ro.csproj new file mode 100644 index 0000000..0a34cca --- /dev/null +++ b/tests/src/JIT/SIMD/VectorHWAccel_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorInitN.csproj b/tests/src/JIT/SIMD/VectorInitN_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorInitN.csproj rename to tests/src/JIT/SIMD/VectorInitN_r.csproj index 1afe58b..9083b85 100644 --- a/tests/src/JIT/SIMD/VectorInitN.csproj +++ b/tests/src/JIT/SIMD/VectorInitN_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorInitN_ro.csproj b/tests/src/JIT/SIMD/VectorInitN_ro.csproj new file mode 100644 index 0000000..8a9b3c2 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorInitN_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorInit.csproj b/tests/src/JIT/SIMD/VectorInit_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorInit.csproj rename to tests/src/JIT/SIMD/VectorInit_r.csproj index 262a4b3..7f292ed 100644 --- a/tests/src/JIT/SIMD/VectorInit.csproj +++ b/tests/src/JIT/SIMD/VectorInit_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorInit_ro.csproj b/tests/src/JIT/SIMD/VectorInit_ro.csproj new file mode 100644 index 0000000..b1a3272 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorInit_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorIntEquals.csproj b/tests/src/JIT/SIMD/VectorIntEquals_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorIntEquals.csproj rename to tests/src/JIT/SIMD/VectorIntEquals_r.csproj index b409c70..c97195e 100644 --- a/tests/src/JIT/SIMD/VectorIntEquals.csproj +++ b/tests/src/JIT/SIMD/VectorIntEquals_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorIntEquals_ro.csproj b/tests/src/JIT/SIMD/VectorIntEquals_ro.csproj new file mode 100644 index 0000000..35ee19a --- /dev/null +++ b/tests/src/JIT/SIMD/VectorIntEquals_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorMatrix.csproj b/tests/src/JIT/SIMD/VectorMatrix_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorMatrix.csproj rename to tests/src/JIT/SIMD/VectorMatrix_r.csproj index b4e1b9c..6e224f9 100644 --- a/tests/src/JIT/SIMD/VectorMatrix.csproj +++ b/tests/src/JIT/SIMD/VectorMatrix_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorMatrix_ro.csproj b/tests/src/JIT/SIMD/VectorMatrix_ro.csproj new file mode 100644 index 0000000..8e6ac7d --- /dev/null +++ b/tests/src/JIT/SIMD/VectorMatrix_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorMax.csproj b/tests/src/JIT/SIMD/VectorMax_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorMax.csproj rename to tests/src/JIT/SIMD/VectorMax_r.csproj index f1fe290..59e13f1 100644 --- a/tests/src/JIT/SIMD/VectorMax.csproj +++ b/tests/src/JIT/SIMD/VectorMax_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorMax_ro.csproj b/tests/src/JIT/SIMD/VectorMax_ro.csproj new file mode 100644 index 0000000..952e5e1 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorMax_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorMin.csproj b/tests/src/JIT/SIMD/VectorMin_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorMin.csproj rename to tests/src/JIT/SIMD/VectorMin_r.csproj index 31d0bd1..fdc3754 100644 --- a/tests/src/JIT/SIMD/VectorMin.csproj +++ b/tests/src/JIT/SIMD/VectorMin_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorMin_ro.csproj b/tests/src/JIT/SIMD/VectorMin_ro.csproj new file mode 100644 index 0000000..c1a4574 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorMin_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorMul.csproj b/tests/src/JIT/SIMD/VectorMul_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorMul.csproj rename to tests/src/JIT/SIMD/VectorMul_r.csproj index 02228aa..50f7e23 100644 --- a/tests/src/JIT/SIMD/VectorMul.csproj +++ b/tests/src/JIT/SIMD/VectorMul_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorMul_ro.csproj b/tests/src/JIT/SIMD/VectorMul_ro.csproj new file mode 100644 index 0000000..0f12043 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorMul_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorRelOp.csproj b/tests/src/JIT/SIMD/VectorRelOp_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorRelOp.csproj rename to tests/src/JIT/SIMD/VectorRelOp_r.csproj index dfa2717..a22e472 100644 --- a/tests/src/JIT/SIMD/VectorRelOp.csproj +++ b/tests/src/JIT/SIMD/VectorRelOp_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorRelOp_ro.csproj b/tests/src/JIT/SIMD/VectorRelOp_ro.csproj new file mode 100644 index 0000000..ddf1fba --- /dev/null +++ b/tests/src/JIT/SIMD/VectorRelOp_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorReturn.csproj b/tests/src/JIT/SIMD/VectorReturn_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorReturn.csproj rename to tests/src/JIT/SIMD/VectorReturn_r.csproj index 332449e..42f55c9 100644 --- a/tests/src/JIT/SIMD/VectorReturn.csproj +++ b/tests/src/JIT/SIMD/VectorReturn_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorReturn_ro.csproj b/tests/src/JIT/SIMD/VectorReturn_ro.csproj new file mode 100644 index 0000000..f0215b6 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorReturn_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorSet.csproj b/tests/src/JIT/SIMD/VectorSet_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorSet.csproj rename to tests/src/JIT/SIMD/VectorSet_r.csproj index fbb299c..a7289eb 100644 --- a/tests/src/JIT/SIMD/VectorSet.csproj +++ b/tests/src/JIT/SIMD/VectorSet_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorSet_ro.csproj b/tests/src/JIT/SIMD/VectorSet_ro.csproj new file mode 100644 index 0000000..51e7b3c --- /dev/null +++ b/tests/src/JIT/SIMD/VectorSet_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorSqrt.csproj b/tests/src/JIT/SIMD/VectorSqrt_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorSqrt.csproj rename to tests/src/JIT/SIMD/VectorSqrt_r.csproj index a6f9f56..4ec3265 100644 --- a/tests/src/JIT/SIMD/VectorSqrt.csproj +++ b/tests/src/JIT/SIMD/VectorSqrt_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorSqrt_ro.csproj b/tests/src/JIT/SIMD/VectorSqrt_ro.csproj new file mode 100644 index 0000000..a489f77 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorSqrt_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorSub.csproj b/tests/src/JIT/SIMD/VectorSub_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorSub.csproj rename to tests/src/JIT/SIMD/VectorSub_r.csproj index 604bfaf..c5af12c 100644 --- a/tests/src/JIT/SIMD/VectorSub.csproj +++ b/tests/src/JIT/SIMD/VectorSub_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorSub_ro.csproj b/tests/src/JIT/SIMD/VectorSub_ro.csproj new file mode 100644 index 0000000..0613cdc --- /dev/null +++ b/tests/src/JIT/SIMD/VectorSub_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + diff --git a/tests/src/JIT/SIMD/VectorUnused.csproj b/tests/src/JIT/SIMD/VectorUnused_r.csproj similarity index 93% rename from tests/src/JIT/SIMD/VectorUnused.csproj rename to tests/src/JIT/SIMD/VectorUnused_r.csproj index a5b12c5..abfa8c7 100644 --- a/tests/src/JIT/SIMD/VectorUnused.csproj +++ b/tests/src/JIT/SIMD/VectorUnused_r.csproj @@ -18,12 +18,18 @@ + pdbonly + true False + + None + + @@ -41,4 +47,4 @@ - \ No newline at end of file + diff --git a/tests/src/JIT/SIMD/VectorUnused_ro.csproj b/tests/src/JIT/SIMD/VectorUnused_ro.csproj new file mode 100644 index 0000000..67b3a85 --- /dev/null +++ b/tests/src/JIT/SIMD/VectorUnused_ro.csproj @@ -0,0 +1,50 @@ + + + + + Debug + AnyCPU + 2.0 + {95DFC527-4DC1-495E-97D7-E94EE1F7140D} + Exe + Properties + 512 + {786C830F-07A1-408B-BD7F-6EE04809D6DB};{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC} + $(ProgramFiles)\Common Files\microsoft shared\VSTT\11.0\UITestExtensionPackages + ..\..\ + 7a9bfb7d + + + + + + pdbonly + true + + + + False + + + + None + True + + + + + + + + + + + + + + + + -- 2.7.4