From 6b2777fff8a9942cdcee82ae3f17d7f483a1e18c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Mar 2023 19:33:17 +0100 Subject: [PATCH] arm64: dts: qcom: sm8450-hdk: align WCD9385 reset pin with downstream config Downstream DTS uses 16 mA drive strength for the WCD9385 audio codec RESET_N reset pin. It also pulls the pin down in shutdown mode, thus it is more like a shutdown pin, not a reset. Use the same settings here for HDK8450 and keep the WCD9385 by default in powered off (so pin as low). Align the name of pin configuration node with other pins in the DTS. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230308183317.559253-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index c97e775..e931545 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -810,9 +810,11 @@ output-low; }; - wcd_default: wcd-default-state { + wcd_default: wcd-reset-n-active-state { pins = "gpio43"; function = "gpio"; + drive-strength = <16>; bias-disable; + output-low; }; }; -- 2.7.4