From 6ae8aac19cdbdbd96d90f86e4d8505fe121bdf06 Mon Sep 17 00:00:00 2001
From: "H.J. Lu" <hjl.tools@gmail.com>
Date: Sat, 17 Jul 2021 14:38:39 -0700
Subject: [PATCH] x86: Enable the GPR only instructions for -mgeneral-regs-only

For -mgeneral-regs-only, enable the GPR only instructions which are
enabled implicitly by SSE ISAs unless they have been disabled explicitly.

gcc/

	PR target/101492
	* common/config/i386/i386-common.c (ix86_handle_option): For
	-mgeneral-regs-only, enable the GPR only instructions which are
	enabled implicitly by SSE ISAs unless they have been disabled
	explicitly.

gcc/testsuite/

	PR target/101492
	* gcc.target/i386/pr101492-1.c: New test.
	* gcc.target/i386/pr101492-2.c: Likewise.
	* gcc.target/i386/pr101492-3.c: Likewise.
	* gcc.target/i386/pr101492-4.c: Likewise.
---
 gcc/common/config/i386/i386-common.c       | 27 +++++++++++++++++++++++++--
 gcc/testsuite/gcc.target/i386/pr101492-1.c | 10 ++++++++++
 gcc/testsuite/gcc.target/i386/pr101492-2.c | 10 ++++++++++
 gcc/testsuite/gcc.target/i386/pr101492-3.c | 10 ++++++++++
 gcc/testsuite/gcc.target/i386/pr101492-4.c | 12 ++++++++++++
 5 files changed, 67 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr101492-1.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr101492-2.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr101492-3.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr101492-4.c

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index e156cc3..76ab1a1 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -354,16 +354,39 @@ ix86_handle_option (struct gcc_options *opts,
     case OPT_mgeneral_regs_only:
       if (value)
 	{
+	  HOST_WIDE_INT general_regs_only_flags = 0;
+	  HOST_WIDE_INT general_regs_only_flags2 = 0;
+
+	  /* NB: Enable the GPR only instructions which are enabled
+	     implicitly by SSE ISAs unless they have been disabled
+	     explicitly.  */
+	  if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags))
+	    {
+	      if (!TARGET_EXPLICIT_CRC32_P (opts))
+		general_regs_only_flags |= OPTION_MASK_ISA_CRC32;
+	      if (!TARGET_EXPLICIT_POPCNT_P (opts))
+		general_regs_only_flags |= OPTION_MASK_ISA_POPCNT;
+	    }
+	  if (TARGET_SSE3_P (opts->x_ix86_isa_flags))
+	    {
+	      if (!TARGET_EXPLICIT_MWAIT_P (opts))
+		general_regs_only_flags2 |= OPTION_MASK_ISA2_MWAIT;
+	    }
+
 	  /* Disable MMX, SSE and x87 instructions if only
 	     general registers are allowed.  */
 	  opts->x_ix86_isa_flags
 	    &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
 	  opts->x_ix86_isa_flags2
 	    &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
+	  opts->x_ix86_isa_flags |= general_regs_only_flags;
+	  opts->x_ix86_isa_flags2 |= general_regs_only_flags2;
 	  opts->x_ix86_isa_flags_explicit
-	    |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
+	    |= (OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
+		| general_regs_only_flags);
 	  opts->x_ix86_isa_flags2_explicit
-	    |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
+	    |= (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
+		| general_regs_only_flags2);
 
 	  opts->x_target_flags &= ~MASK_80387;
 	}
diff --git a/gcc/testsuite/gcc.target/i386/pr101492-1.c b/gcc/testsuite/gcc.target/i386/pr101492-1.c
new file mode 100644
index 0000000..4100257
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101492-1.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4.2 -mgeneral-regs-only" } */
+
+#include <x86intrin.h>
+
+unsigned int
+foo1 (unsigned int x, unsigned int y)
+{
+  return __crc32d (x, y);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr101492-2.c b/gcc/testsuite/gcc.target/i386/pr101492-2.c
new file mode 100644
index 0000000..c7d24f4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101492-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse4.2 -mgeneral-regs-only" } */
+
+#include <x86intrin.h>
+
+unsigned int
+foo1 (unsigned int x)
+{
+  return _mm_popcnt_u32 (x);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr101492-3.c b/gcc/testsuite/gcc.target/i386/pr101492-3.c
new file mode 100644
index 0000000..37e2071
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101492-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -msse3 -mgeneral-regs-only" } */
+
+#include <x86intrin.h>
+
+void
+foo1 (unsigned int x, unsigned int y)
+{
+  _mm_mwait (x, y);
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr101492-4.c b/gcc/testsuite/gcc.target/i386/pr101492-4.c
new file mode 100644
index 0000000..c5a4f0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr101492-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-mwait -msse3 -mgeneral-regs-only" } */
+
+#include <x86intrin.h>
+
+void
+foo1 (unsigned int x, unsigned int y)
+{
+  _mm_mwait (x, y);
+}
+
+/* { dg-error "target specific option mismatch" "" { target *-*-* } 0 } */
-- 
2.7.4