From 6ab4d6e44eb0bda03a57f43fbf3c88b9901210b9 Mon Sep 17 00:00:00 2001 From: Philipp Tomsich Date: Tue, 31 Jan 2023 21:34:06 +0100 Subject: [PATCH] [RISCV][NFC] Update RISCVUsage.rst to sort vendor extensions --- llvm/docs/RISCVUsage.rst | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 58a24ce..3b6b7b5 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -169,12 +169,11 @@ It is our intention to follow the naming conventions described in `riscv-non-isa The current vendor extensions supported are: -``XVentanaCondOps`` - LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. - ``XTHeadVdot`` LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `_ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above. +``XVentanaCondOps`` + LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. Specification Documents ======================= -- 2.7.4