From 69ec1e2065ac43eea44fdfa703cf027ce72a62da Mon Sep 17 00:00:00 2001 From: Tamar Christina Date: Tue, 13 Dec 2022 18:01:15 +0000 Subject: [PATCH] AArch64: Fix ILP32 tbranch the baremetal builds are currently broken because the shift ends up in the wrong representation if the mode is SImode and the shift amount if 31. To fix this create the rtx constant with an explicit mode so the backend passes know which representation it needs to take. gcc/ChangeLog: * config/aarch64/aarch64.md (tbranch_3): Use gen_int_mode. --- gcc/config/aarch64/aarch64.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d749c98..6c27fb8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -957,7 +957,7 @@ { rtx bitvalue = gen_reg_rtx (mode); rtx reg = gen_lowpart (mode, operands[0]); - rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), mode); emit_insn (gen_and3 (bitvalue, reg, val)); operands[1] = const0_rtx; operands[0] = aarch64_gen_compare_reg (, bitvalue, -- 2.7.4