From 69ce4b2288d22ad23b8ceeb8c238fcc58a7e5089 Mon Sep 17 00:00:00 2001 From: Paul Burton Date: Sun, 24 May 2015 16:11:22 +0100 Subject: [PATCH] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT Rather than hardcoding the IRQ number used to cascade interrupts from the SoC interrupt controller to the CPU interrupt controller, read that IRQ number from the DT describing the system. Signed-off-by: Paul Burton Cc: Lars-Peter Clausen Cc: Thomas Gleixner Cc: Jason Cooper Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Brian Norris Patchwork: https://patchwork.linux-mips.org/patch/10137/ Signed-off-by: Ralf Baechle --- arch/mips/jz4740/irq.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c index 43e000a..ed51915 100644 --- a/arch/mips/jz4740/irq.c +++ b/arch/mips/jz4740/irq.c @@ -85,6 +85,11 @@ static int __init jz4740_intc_of_init(struct device_node *node, { struct irq_chip_generic *gc; struct irq_chip_type *ct; + int parent_irq; + + parent_irq = irq_of_parse_and_map(node, 0); + if (!parent_irq) + return -EINVAL; jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14); @@ -108,7 +113,7 @@ static int __init jz4740_intc_of_init(struct device_node *node, irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL); - setup_irq(2, &jz4740_cascade_action); + setup_irq(parent_irq, &jz4740_cascade_action); return 0; } IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", jz4740_intc_of_init); -- 2.7.4