From 6979c6303a4abf263753cd9d577d79f05c6e8c47 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:11 +1000 Subject: [PATCH] drm/nouveau/clk: switch to new-style timer macros Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c | 16 +++++++++++++--- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c | 16 +++++++++++++--- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c | 8 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c | 24 +++++++++++++++++++----- drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c | 8 +++++--- 5 files changed, 54 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c index f7aac37..c90f7d6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c @@ -345,7 +345,10 @@ gf100_clk_prog_1(struct gf100_clk *clk, int idx) { struct nvkm_device *device = clk->base.subdev.device; nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); - nv_wait(clk, 0x137100, (1 << idx), 0x00000000); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) + break; + ); } static void @@ -360,7 +363,10 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000); + nvkm_msec(device, 2000, + if (nvkm_rd32(device, addr + 0x00) & 0x00020000) + break; + ); nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); } } @@ -373,7 +379,11 @@ gf100_clk_prog_3(struct gf100_clk *clk, int idx) struct nvkm_device *device = clk->base.subdev.device; if (info->ssel) { nvkm_mask(device, 0x137100, (1 << idx), info->ssel); - nv_wait(clk, 0x137100, (1 << idx), info->ssel); + nvkm_msec(device, 2000, + u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); + if (tmp == info->ssel) + break; + ); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c index d2b7d6e..ad166aa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c @@ -366,7 +366,10 @@ gk104_clk_prog_1_0(struct gk104_clk *clk, int idx) { struct nvkm_device *device = clk->base.subdev.device; nvkm_mask(device, 0x137100, (1 << idx), 0x00000000); - nv_wait(clk, 0x137100, (1 << idx), 0x00000000); + nvkm_msec(device, 2000, + if (!(nvkm_rd32(device, 0x137100) & (1 << idx))) + break; + ); } static void @@ -387,7 +390,10 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx) if (info->coef) { nvkm_wr32(device, addr + 0x04, info->coef); nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001); - nv_wait(clk, addr + 0x00, 0x00020000, 0x00020000); + nvkm_msec(device, 2000, + if (nvkm_rd32(device, addr + 0x00) & 0x00020000) + break; + ); nvkm_mask(device, addr + 0x00, 0x00020004, 0x00000004); } } @@ -410,7 +416,11 @@ gk104_clk_prog_4_0(struct gk104_clk *clk, int idx) struct nvkm_device *device = clk->base.subdev.device; if (info->ssel) { nvkm_mask(device, 0x137100, (1 << idx), info->ssel); - nv_wait(clk, 0x137100, (1 << idx), info->ssel); + nvkm_msec(device, 2000, + u32 tmp = nvkm_rd32(device, 0x137100) & (1 << idx); + if (tmp == info->ssel) + break; + ); } } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c index 6d36d09..49659bc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c @@ -405,11 +405,11 @@ _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) nvkm_wr32(device, GPCPLL_CFG, val); } - if (!nvkm_timer_wait_eq(clk, 300000, GPCPLL_CFG, GPCPLL_CFG_LOCK, - GPCPLL_CFG_LOCK)) { - nv_error(clk, "%s: timeout waiting for pllg lock\n", __func__); + if (nvkm_usec(device, 300, + if (nvkm_rd32(device, GPCPLL_CFG) & GPCPLL_CFG_LOCK) + break; + ) < 0) return -ETIMEDOUT; - } /* switch to VCO mode */ nvkm_mask(device, SEL_VCO, 0, BIT(SEL_VCO_GPC2CLK_OUT_SHIFT)); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c index 364c9b0..6992cbb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c @@ -302,21 +302,32 @@ int gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) { struct nvkm_device *device = clk->subdev.device; - struct nvkm_fifo *fifo = nvkm_fifo(clk); + struct nvkm_fifo *fifo = device->fifo; /* halt and idle execution engines */ nvkm_mask(device, 0x020060, 0x00070000, 0x00000000); nvkm_mask(device, 0x002504, 0x00000001, 0x00000001); /* Wait until the interrupt handler is finished */ - if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) + if (nvkm_msec(device, 2000, + if (!nvkm_rd32(device, 0x000100)) + break; + ) < 0) return -EBUSY; if (fifo) fifo->pause(fifo, flags); - if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, 0x002504) & 0x00000010) + break; + ) < 0) return -EIO; - if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) + + if (nvkm_msec(device, 2000, + u32 tmp = nvkm_rd32(device, 0x002504) & 0x0000003f; + if (tmp == 0x0000003f) + break; + ) < 0) return -EIO; return 0; @@ -367,7 +378,10 @@ prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) nvkm_wr32(device, coef, info->pll); nvkm_mask(device, ctrl, 0x00000015, 0x00000015); nvkm_mask(device, ctrl, 0x00000010, 0x00000000); - if (!nv_wait(clk, ctrl, 0x00020000, 0x00020000)) { + if (nvkm_msec(device, 2000, + if (nvkm_rd32(device, ctrl) & 0x00020000) + break; + ) < 0) { nvkm_mask(device, ctrl, 0x00000010, 0x00000010); nvkm_mask(device, src0, 0x00000101, 0x00000000); return; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c index 9d7c118..05d2a1b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c @@ -349,10 +349,12 @@ mcp77_clk_prog(struct nvkm_clk *obj) goto resume; } - if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { - nv_warn(clk,"Reclocking failed: unstable PLLs\n"); + if (nvkm_msec(device, 2000, + u32 tmp = nvkm_rd32(device, 0x004080) & pllmask; + if (tmp == pllmask) + break; + ) < 0) goto resume; - } switch (clk->vsrc) { case nv_clk_src_cclk: -- 2.7.4