From 6926129f65617d57b42fe10ad4d3fa870ce7597f Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Wed, 22 Mar 2017 16:28:36 +0900 Subject: [PATCH] s5j/spi: tidy up a bit Change-Id: I78b3b226b66cc6ed6855d4b390aee23e3205c5a4 Signed-off-by: Heesub Shin --- os/arch/arm/src/s5j/s5j_spi.c | 127 ++++++++++++++-------------- os/arch/arm/src/s5j/s5j_spi.h | 187 ++++++++++++++++++++++-------------------- 2 files changed, 159 insertions(+), 155 deletions(-) diff --git a/os/arch/arm/src/s5j/s5j_spi.c b/os/arch/arm/src/s5j/s5j_spi.c index 455fdd7..c3a9fd4 100644 --- a/os/arch/arm/src/s5j/s5j_spi.c +++ b/os/arch/arm/src/s5j/s5j_spi.c @@ -82,8 +82,6 @@ /***************************************************************************** * Definitions *****************************************************************************/ -#define SPI_FILE_OPT 1 - #define SPI0_BASE S5J_SPI0_BASE #define SPI1_BASE S5J_SPI1_BASE #define SPI2_BASE S5J_SPI2_BASE @@ -94,23 +92,17 @@ /***************************************************************************** * Private Types *****************************************************************************/ - struct s5jt200_spidev_s { struct spi_dev_s spidev; #ifndef CONFIG_SPI_POLLWAIT - sem_t xfrsem; /* Wait for transfer to complete */ + sem_t xfrsem; /* Wait for transfer to complete */ #endif - void *txbuffer; /* Source buffer */ - void *rxbuffer; /* Destination buffer */ - - /* Do we need it ??? - void (*txword)(struct s5jt200_spidev_s *priv); - void (*rxword)(struct s5jt200_spidev_s *priv); - */ + void *txbuffer; /* Source buffer */ + void *rxbuffer; /* Destination buffer */ uint32_t base; - uint8_t spiirq; /* SPI IRQ number */ + uint8_t spiirq; /* SPI IRQ number */ #ifdef CONFIG_SPI_DMA /* Put some here if we will decide to use DMA some day */ @@ -130,18 +122,22 @@ struct s5jt200_spidev_s { /***************************************************************************** * Private Function Prototypes *****************************************************************************/ - static int spi_lock(struct spi_dev_s *dev, bool lock); -static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, bool selected); +static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected); static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency); static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode); static void spi_setbits(struct spi_dev_s *dev, int nbits); static uint8_t spi_status(struct spi_dev_s *dev, enum spi_dev_e devid); static uint16_t spi_send(struct spi_dev_s *dev, uint16_t word); -static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords); +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords); + #ifndef CONFIG_SPI_EXCHANGE -static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, size_t nwords); -static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, size_t nwords); +static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, + size_t nwords); +static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, + size_t nwords); #endif /***************************************************************************** @@ -166,33 +162,35 @@ struct gsio_s5jt200_regs_s { static const struct gsio_s5jt200_regs_s gsio_regs[2] = { { - .interface = (volatile struct gsio_s5jt200_ctrl_regs_s *)GSIO_0_IF, + .interface = + (volatile struct gsio_s5jt200_ctrl_regs_s *)GSIO_0_IF, .clkdiv = (volatile uint32_t *)GSIO_0_CLKDIV, }, { - .interface = (volatile struct gsio_s5jt200_ctrl_regs_s *)GSIO_1_IF, + .interface = + (volatile struct gsio_s5jt200_ctrl_regs_s *)GSIO_1_IF, .clkdiv = (volatile uint32_t *)GSIO_1_CLKDIV, }, }; static const struct spi_ops_s g_spiops = { #ifndef CONFIG_SPI_OWNBUS - .lock = spi_lock, //done + .lock = spi_lock, #endif - .select = spi_select, //done - .setfrequency = spi_setfrequency, //more - .setmode = (void *)spi_setmode, //done - .setbits = (void *)spi_setbits, //done - .status = spi_status, //done + .select = spi_select, + .setfrequency = spi_setfrequency, + .setmode = (void *)spi_setmode, + .setbits = (void *)spi_setbits, + .status = spi_status, #ifdef CONFIG_SPI_CMDDATA .cmddata = MISSING FUNCTION; #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE - .exchange = spi_exchange, //more + .exchange = spi_exchange, #else - .sndblock = spi_sndblock, //more - .recvblock = spi_recvblock, //more + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, #endif .registercallback = 0, }; @@ -304,7 +302,7 @@ static void spi_set_gpio(SPI_PORT ePort, u32 DrvStrength) } } -/***************************************************************************** +/**************************************************************************** * Name: spi_lock * * Description: @@ -316,8 +314,7 @@ static void spi_set_gpio(SPI_PORT ePort, u32 DrvStrength) * configured for the device. If the SPI buss is being shared, then it * may have been left in an incompatible state. * - *****************************************************************************/ - + ****************************************************************************/ static int spi_lock(struct spi_dev_s *dev, bool lock) { struct s5jt200_spidev_s *priv = (struct s5jt200_spidev_s *)dev; @@ -337,14 +334,13 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) return 0; } -/***************************************************************************** +/**************************************************************************** * Name: spi_setfrequency * * Description: * Set the SPI frequency. * - *****************************************************************************/ - + ****************************************************************************/ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { struct s5jt200_spidev_s *priv = (struct s5jt200_spidev_s *)dev; @@ -376,8 +372,8 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) * all other attempts to select the device until the device is deselecte. * ****************************************************************************/ - -static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected) { struct s5jt200_spidev_s *priv = (struct s5jt200_spidev_s *)dev; SPI_SFR *pSPIRegs; @@ -400,10 +396,10 @@ void spi_set_initial(struct spi_dev_s *dev) SPI_SFR *pSPIRegs; pSPIRegs = (SPI_SFR *)priv->base; - Outp32(&pSPIRegs->CH_CFG, 0x03); // TX/RX enable. Master.CPHA 00. - Outp32(&pSPIRegs->MODE_CFG, 0); // No FIFO. N0 DMA. 8 bits - Outp32(&pSPIRegs->CS_REG, 1); // CS Manual Passive - Outp32(&pSPIRegs->SPI_INT_EN, 0); // Disable Interrupts + Outp32(&pSPIRegs->CH_CFG, 0x03); /* TX/RX enable. Master.CPHA 00. */ + Outp32(&pSPIRegs->MODE_CFG, 0); /* No FIFO. N0 DMA. 8 bits */ + Outp32(&pSPIRegs->CS_REG, 1); /* CS Manual Passive */ + Outp32(&pSPIRegs->SPI_INT_EN, 0); /* Disable Interrupts */ } /***************************************************************************** @@ -413,7 +409,6 @@ void spi_set_initial(struct spi_dev_s *dev) * Set the SPI mode. see enum spi_mode_e for mode definitions * *****************************************************************************/ - static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { struct s5jt200_spidev_s *priv = (struct s5jt200_spidev_s *)dev; @@ -435,14 +430,13 @@ inline void spi_fifo_flush(SPI_SFR *pSPIRegs) Outp32(&pSPIRegs->CH_CFG, ch_cfg); } -/***************************************************************************** +/**************************************************************************** * Name: spi_setbits * * Description: * Set the number of bits per word. * - *****************************************************************************/ - + ****************************************************************************/ static void spi_setbits(struct spi_dev_s *dev, int nbits) { struct s5jt200_spidev_s *priv = (struct s5jt200_spidev_s *)dev; @@ -477,29 +471,27 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) Outp32(&pSPIRegs->MODE_CFG, mode_cfg); } -/***************************************************************************** +/**************************************************************************** * Name: spi_status * * Description: * Get SPI status * ****************************************************************************/ - static uint8_t spi_status(struct spi_dev_s *dev, enum spi_dev_e devid) { - while (1) ; /*STATUS? What status? */ + while (1) ; /* STATUS? What status? */ return SPI_STATUS_PRESENT; } -/***************************************************************************** +/**************************************************************************** * Name: spi_send * * Description: * Exchange one word on SPI * - *****************************************************************************/ - + ****************************************************************************/ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t word) { uint8_t txbyte; @@ -512,14 +504,15 @@ static uint16_t spi_send(struct spi_dev_s *dev, uint16_t word) return (uint16_t)rxbyte; } -/***************************************************************************** +/**************************************************************************** * Name: spi_exchange * * Description: * Exchange a block data with the SPI device * ****************************************************************************/ -static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) { size_t sent = 0; size_t received = 0; @@ -591,44 +584,43 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbu } } -/***************************************************************************** +/**************************************************************************** * Name: spi_sndblock * * Description: * Send a block of data on SPI * - *****************************************************************************/ - -static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, size_t nwords) + ****************************************************************************/ +static void spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, + size_t nwords) { spi_exchange(dev, txbuffer, NULL, nwords); } -/***************************************************************************** +/**************************************************************************** * Name: spi_recvblock * * Description: * Revice a block of data from SPI * - *****************************************************************************/ - -static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) + ****************************************************************************/ +static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, + size_t nwords) { spi_exchange(dev, NULL, rxbuffer, nwords); } -/***************************************************************************** +/**************************************************************************** * Public Functions - *****************************************************************************/ + ****************************************************************************/ -/***************************************************************************** +/**************************************************************************** * Name: up_spiinitialize * * Description: * Initialize the selected SPI port * - *****************************************************************************/ - + ****************************************************************************/ struct spi_dev_s *up_spiinitialize(int port) { struct s5jt200_spidev_s *priv = NULL; @@ -639,8 +631,8 @@ struct spi_dev_s *up_spiinitialize(int port) priv = &g_spidev[port]; lldbg("Prepare SPI0 for Master operation\n"); - //spi_init(&gpCtrlInfo); - /*SET GPIO for the port */ + + /* SET GPIO for the port */ spi_set_gpio(port, 0xFFFF); priv->port = port; @@ -648,6 +640,7 @@ struct spi_dev_s *up_spiinitialize(int port) #ifndef CONFIG_SPI_POLLWAIT sem_init(&priv->xfrsem, 0, 0); #endif + #ifndef CONFIG_SPI_OWNBUS sem_init(&priv->exclsem, 0, 1); #endif diff --git a/os/arch/arm/src/s5j/s5j_spi.h b/os/arch/arm/src/s5j/s5j_spi.h index 33e3eb7..1f5855e 100644 --- a/os/arch/arm/src/s5j/s5j_spi.h +++ b/os/arch/arm/src/s5j/s5j_spi.h @@ -68,11 +68,11 @@ extern "C" { /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define SPI_CLOCK_TEST 0 -#define SPI_TRANS_SIZE 8 -#define SPI_BUFFER_SIZE 32 -#define SPI_NO_ERROR 0 -#define SPI_ERROR (-1) +#define SPI_CLOCK_TEST 0 +#define SPI_TRANS_SIZE 8 +#define SPI_BUFFER_SIZE 32 +#define SPI_NO_ERROR 0 +#define SPI_ERROR (-1) #define TEMP_TEST @@ -84,18 +84,18 @@ typedef enum { } eSPI_IOCTL_CMD; typedef struct _SPI_SFR { - u32 CH_CFG; /* 0x00 spi configuration register */ - u32 CLK_CFG; /* 0x04 deleted */ - u32 MODE_CFG; /* 0x08 spi fifo control register */ - u32 CS_REG; /* 0x0C slave selection signal */ - u32 SPI_INT_EN; /* 0x10 spi interrupt enable register */ - u32 SPI_STATUS; /* 0x14 spi status register */ - u32 SPI_TX_DATA; /* 0x18 spi tx data register */ - u32 SPI_RX_DATA; /* 0x1C spi rx data register */ - u32 PACKET_CNT_REG; /* 0x20 count how many data master gets. */ + u32 CH_CFG; /* 0x00 spi configuration register */ + u32 CLK_CFG; /* 0x04 deleted */ + u32 MODE_CFG; /* 0x08 spi fifo control register */ + u32 CS_REG; /* 0x0C slave selection signal */ + u32 SPI_INT_EN; /* 0x10 spi interrupt enable register */ + u32 SPI_STATUS; /* 0x14 spi status register */ + u32 SPI_TX_DATA; /* 0x18 spi tx data register */ + u32 SPI_RX_DATA; /* 0x1C spi rx data register */ + u32 PACKET_CNT_REG; /* 0x20 count how many data master gets. */ u32 PENDING_CLR_REG; /* 0x24 pending clear register */ - u32 SWAP_CFG; /* 0x28 swap config register */ - u32 FB_CLK_SEL; /* 0x2C feedback clock config register */ + u32 SWAP_CFG; /* 0x28 swap config register */ + u32 FB_CLK_SEL; /* 0x2C feedback clock config register */ } SPI_SFR; typedef enum { @@ -132,79 +132,81 @@ typedef enum { } SPI_DMA_type; typedef enum { - SPI_INT_TRAILING = (1 << 6), - SPI_INT_RX_OVERRUN = (1 << 5), - SPI_INT_RX_UNDERRUN = (1 << 4), - SPI_INT_TX_OVERRUN = (1 << 3), - SPI_INT_TX_UNDERRUN = (1 << 2), - SPI_INT_RX_FIFORDY = (1 << 1), - SPI_INT_TX_FIFORDY = (1 << 0), - SPI_INT_ALL = 0x7F, + SPI_INT_TRAILING = (1 << 6), + SPI_INT_RX_OVERRUN = (1 << 5), + SPI_INT_RX_UNDERRUN = (1 << 4), + SPI_INT_TX_OVERRUN = (1 << 3), + SPI_INT_TX_UNDERRUN = (1 << 2), + SPI_INT_RX_FIFORDY = (1 << 1), + SPI_INT_TX_FIFORDY = (1 << 0), + SPI_INT_ALL = 0x7F, } SPI_IntrModeBit_et; typedef enum { - SPI_CLR_PND_TX_UNDERRUN = (1 << 4), - SPI_CLR_PND_TX_OVERRUN = (1 << 3), - SPI_CLR_PND_RX_UNDERRUN = (1 << 2), - SPI_CLR_PND_RX_OVERRUN = (1 << 1), - SPI_CLR_PND_TRAILING = (1 << 0), - SPI_CLR_PND_ALL = 0x1F, + SPI_CLR_PND_TX_UNDERRUN = (1 << 4), + SPI_CLR_PND_TX_OVERRUN = (1 << 3), + SPI_CLR_PND_RX_UNDERRUN = (1 << 2), + SPI_CLR_PND_RX_OVERRUN = (1 << 1), + SPI_CLR_PND_TRAILING = (1 << 0), + SPI_CLR_PND_ALL = 0x1F, } SPI_IntClrModeBit_et; typedef enum { - SPI_STATUS_TX_DONE = (1 << 25), - SPI_STATUS_TRAILING_BYTE = (1 << 24), - SPI_STATUS_RX_OVERRUN = (1 << 5), - SPI_STATUS_RX_UNDERRUN = (1 << 4), - SPI_STATUS_TX_OVERRUN = (1 << 3), - SPI_STATUS_TX_UNDERRUN = (1 << 2), - SPI_STATUS_RX_FIFORDY = (1 << 1), - SPI_STATUS_TX_FIFORDY = (1 << 0), + SPI_STATUS_TX_DONE = (1 << 25), + SPI_STATUS_TRAILING_BYTE = (1 << 24), + SPI_STATUS_RX_OVERRUN = (1 << 5), + SPI_STATUS_RX_UNDERRUN = (1 << 4), + SPI_STATUS_TX_OVERRUN = (1 << 3), + SPI_STATUS_TX_UNDERRUN = (1 << 2), + SPI_STATUS_RX_FIFORDY = (1 << 1), + SPI_STATUS_TX_FIFORDY = (1 << 0), } SPI_StatusBit_et; typedef enum { - SPI_BYTE = 0, - SPI_HWORD = 1, - SPI_WORD = 2, + SPI_BYTE = 0, + SPI_HWORD = 1, + SPI_WORD = 2, } SPI_transfer_data_type; typedef enum { - SPI_PHASE_DELAY0 = 0x00, - SPI_PHASE_DELAY90 = 0x01, - SPI_PHASE_DELAY180 = 0x02, - SPI_PHASE_DELAY270 = 0x03, - SPI_PHASE_DELAY = 0x04, + SPI_PHASE_DELAY0 = 0x00, + SPI_PHASE_DELAY90 = 0x01, + SPI_PHASE_DELAY180 = 0x02, + SPI_PHASE_DELAY270 = 0x03, + SPI_PHASE_DELAY = 0x04, } SPI_feedbackClock; typedef enum { - SPI_INTERRUPT_MODE = 0x0, - SPI_DMA_MODE = 0x1, - SPI_POLLING_MODE = 0x4, + SPI_INTERRUPT_MODE = 0x0, + SPI_DMA_MODE = 0x1, + SPI_POLLING_MODE = 0x4, } SPI_transfer_mode; typedef enum { - SPI_CLKSRC_XXTI = 0, - SPI_CLKSRC_BUS_PLL = 1, + SPI_CLKSRC_XXTI = 0, + SPI_CLKSRC_BUS_PLL = 1, } SPI_CLKSRC_et; typedef enum { - SPI_NSSOUT_ACTIVE = 0, - SPI_NSSOUT_INACTIVE = 1, - SPI_NSSOUT_USER_MODE = 2, + SPI_NSSOUT_ACTIVE = 0, + SPI_NSSOUT_INACTIVE = 1, + SPI_NSSOUT_USER_MODE = 2, } SPI_NSSOUT_et; typedef enum { - SPI_NO_SWAP = 0, - SPI_BIT_SWAP = (1 << 1), /* Bit swap. */ - SPI_BYTE_SWAP = (1 << 2), /* Byte swap. */ - SPI_HWORD_SWAP = (1 << 3), /* Half Word swap. */ + SPI_NO_SWAP = 0, + SPI_BIT_SWAP = (1 << 1), /* Bit swap. */ + SPI_BYTE_SWAP = (1 << 2), /* Byte swap. */ + SPI_HWORD_SWAP = (1 << 3), /* Half Word swap. */ } SPI_SwapMode; typedef struct { u32 m_StartMemAddr; u32 m_TotalSize; - u32 m_CurMemAddr; /* I'll use the Non Cacheable Memory Area as Ring-Buffer. */ + + /* I'll use the Non Cacheable Memory Area as Ring-Buffer. */ + u32 m_CurMemAddr; } SPI_NCBufCtrlInfo_st; typedef struct { @@ -212,19 +214,19 @@ typedef struct { u8 *m_pCurPtr; /* Current buffer pointer */ u32 m_BufSize; /* Buffer size */ u32 m_ReqDataSize; /* Requested data size */ - u32 m_RemainDataSize; /* not treated, Remain data size */ + u32 m_RemainDataSize; /* not treated, Remain data size */ } SPI_BufAllocInfo_st; typedef void (*SPI_IntHandler_t)(void); typedef void (*SPI_Callback_t)(u32 Value2); typedef struct { - SPI_PORT m_SPIPortIdx; /* SPI0, SPI1, SPI2 */ - SPI_SFR *m_SPISFRBase; /* SFR Base Register */ + SPI_PORT m_SPIPortIdx; /* SPI0, SPI1, SPI2 */ + SPI_SFR *m_SPISFRBase; /* SFR Base Register */ /* CH_CFG */ bool m_EnHighSpeed; /* Enable High Speed in Salve Tx */ - SPI_OpMode m_OpMode; /* Master or Slave Mode */ + SPI_OpMode m_OpMode; /* Master or Slave Mode */ SPI_CPOL m_CPOL; /* CPOL */ SPI_CPHA m_CPHA; /* CPHA */ bool m_EnRxChannel; /* Enable Tx Channel */ @@ -232,31 +234,31 @@ typedef struct { bool m_EnClk; /* Clock Enable/Disable */ bool m_ClkDivPre; /* 1~256 */ - SPI_CLKSRC_et m_ClkSrc; /* XTI, USBXTI */ + SPI_CLKSRC_et m_ClkSrc; /* XTI, USBXTI */ u32 m_ClkDiv; /* 1 ~ 16 */ u32 m_OpClock; /* Opeation clock */ u32 m_TargetSPICLK; /* Target Clock */ /* MODE_CFG */ SPI_transfer_data_type m_ChWidth; /* BYTE, HWORD, WORD */ - u32 m_TraillingCnt; /* Trailing Bytes threshold value in Rx FIFO */ + u32 m_TraillingCnt; /* Trailing Bytes threshold value in Rx FIFO */ SPI_transfer_data_type m_BusWidth; /* BYTE, HWORD, WORD */ - u32 m_RxReadyLevel; /* Rx FIFO trigger level */ - u32 m_TxReadyLevel; /* Tx FIFO trigger level */ - bool m_Self_loopbackMode; /* self loopback test mode */ + u32 m_RxReadyLevel; /* Rx FIFO trigger level */ + u32 m_TxReadyLevel; /* Tx FIFO trigger level */ + bool m_Self_loopbackMode; /* self loopback test mode */ SPI_transfer_mode m_RxTransferMode; /* Interrupt mode, DMA mode */ SPI_transfer_mode m_TxTransferMode; /* Interrupt mode, DMA mode */ - u32 m_MaxFIFOSize; /* Port0 : 256 bytes, Port1/2 : 64 bytes */ - u32 m_FifoLevelGrid; /* Port0 : 4 bytes, Port1/2 : 1 byte */ + u32 m_MaxFIFOSize; /* Port0 : 256 bytes, Port1/2 : 64 bytes */ + u32 m_FifoLevelGrid; /* Port0 : 4 bytes, Port1/2 : 1 byte */ u32 m_TxTransferSize; u32 m_RxTransferSize; - SPI_DMA_type m_DMAType; /* Single or 4Burst */ + SPI_DMA_type m_DMAType; /* Single or 4Burst */ /* CS_REG */ u32 m_NCSTimeCnt; /* NCS Time Count */ bool m_EnAutoCS; /* Manual or Auto Chip Selection */ - SPI_NSSOUT_et m_NSSOut; /* Active or Inactive in Manual mode Chip Selection */ + SPI_NSSOUT_et m_NSSOut; /* Active or Inactive in Manual mode Chip Selection */ /* INT_EN */ bool m_EnTrailingInt; /* Enable Trailing Interrupt */ @@ -278,18 +280,18 @@ typedef struct { /* FB_CLK_SEL */ SPI_feedbackClock m_FBClkSel; /* Select Feedback Clock */ - /* Drive Strength */ - u32 m_DrvStrength; /* Drive Strength */ - bool m_EnSWReset; /* Reset in InitializeREG() */ + /* Drive Strength */ + u32 m_DrvStrength; /* Drive Strength */ + bool m_EnSWReset; /* Reset in InitializeREG() */ - bool m_EnPrintInISR; /* interrupt massage */ - u32 m_SPIIntNum; /* store interrupt Number */ + bool m_EnPrintInISR; /* interrupt massage */ + u32 m_SPIIntNum; /* store interrupt Number */ SPI_IntHandler_t m_fnISR_SPI; /* SPI interrupt handler */ SPI_BufAllocInfo_st m_RxBufNode; SPI_BufAllocInfo_st m_TxBufNode; - /* ISR */ + /* ISR */ SPI_Callback_t m_RxDMACompleteCallback; u32 m_RxDMACompleteCallback_Value; @@ -348,7 +350,8 @@ u8 spi_rd_rx_data08(SPI_PortInfo_st *pPortInfo); u16 spi_rd_rx_data16(SPI_PortInfo_st *pPortInfo); u32 spi_rd_rx_data32(SPI_PortInfo_st *pPortInfo); -void spi_set_isr_func(SPI_PortInfo_st *pPortInfo, u32 uIntrMode, void (*fnIsrFunc)(u32), u32 uIsrVar); +void spi_set_isr_func(SPI_PortInfo_st *pPortInfo, u32 uIntrMode, + void (*fnIsrFunc)(u32), u32 uIsrVar); /**************************************************************************** * Private Functions Prototypes @@ -358,7 +361,8 @@ static void spi_chip_select(SPI_PortInfo_st *pPortInfo, SPI_NSSOUT_et NSSOut); static void spi_enable_channel(SPI_PortInfo_st *pPortInfo); static u8 spi_is_tx_done(SPI_PortInfo_st *pPortInfo); static void spi_sw_reset(SPI_PortInfo_st *pPortInfo); -static void spi_enable_packet_count(SPI_PortInfo_st *pPortInfo, bool En, u32 CntVal); +static void spi_enable_packet_count(SPI_PortInfo_st *pPortInfo, bool En, + u32 CntVal); static u8 spi_is_tx_fifo_rdy(SPI_PortInfo_st *pPortInfo); static u16 spi_is_tx_fifo_lvl(SPI_PortInfo_st *pPortInfo); static u16 spi_is_rx_fifo_lvl(SPI_PortInfo_st *pPortInfo); @@ -366,11 +370,11 @@ static u16 spi_is_rx_fifo_lvl(SPI_PortInfo_st *pPortInfo); /**************************************************************************** * Private Functions Prototypes; Used for only Test ****************************************************************************/ - static void spi_create_ncbuf_ctrl(u32 StartAddr, u32 TotalSize); static u8 *spi_get_ncbuf(SPI_BufAllocInfo_st *pBufAllocInfo, u32 BufSize); static int spi_init_ncbuf_zero(SPI_BufAllocInfo_st *pBufAllocInfo); -static void spi_display_ncbuf_hex(SPI_BufAllocInfo_st *pBufAllocInfo, SPI_transfer_data_type EnDisplay); +static void spi_display_ncbuf_hex(SPI_BufAllocInfo_st *pBufAllocInfo, + SPI_transfer_data_type EnDisplay); static int spi_init_ncbuf_fix(SPI_BufAllocInfo_st *pBufAllocInfo, u32 BufSize); static int spi_init_buf_zero(void *pBuf, u32 BufSize); static s32 spi_polling_master_tx(SPI_PortInfo_st *pPortInfo); @@ -379,15 +383,22 @@ static s32 spi_polling_master_rx(SPI_PortInfo_st *pPortInfo); static s32 spi_polling_slave_tx(SPI_PortInfo_st *pPortInfo); static s32 spi_polling_master_txrx(SPI_PortInfo_st *pPortInfo); static int spi_compare_data(u8 *data1, u8 *data2, u32 bytes); -static s32 spi_check_loopback_master_and_channel(SPI_PortInfo_st *pPortAInfo, SPI_PortInfo_st *pPortBInfo, SPI_PortInfo_st **pMasterPort, SPI_PortInfo_st **pSlavePort, SPI_PortInfo_st **pTxPort, SPI_PortInfo_st **pRxPort); -static s32 spi_loopback_polling_masterTxRx_slaveTxRx_test(SPI_PortInfo_st *pMaster, SPI_PortInfo_st *pSlave); -static s32 spi_loopback_polling_masterTx_slaveRx_test(SPI_PortInfo_st *pMaster, SPI_PortInfo_st *pSlave); -static s32 spi_loopback_polling_masterRx_slaveTx_test(SPI_PortInfo_st *pMaster, SPI_PortInfo_st *pSlave); -static s32 spi_loopback_portA_portB_polling_test(SPI_PortInfo_st *pPortAInfo, SPI_PortInfo_st *pPortBInfo); +static s32 spi_check_loopback_master_and_channel(SPI_PortInfo_st *pPortAInfo, + SPI_PortInfo_st *pPortBInfo, SPI_PortInfo_st **pMasterPort, + SPI_PortInfo_st **pSlavePort, SPI_PortInfo_st **pTxPort, + SPI_PortInfo_st **pRxPort); +static s32 spi_loopback_polling_masterTxRx_slaveTxRx_test( + SPI_PortInfo_st *pMaster, SPI_PortInfo_st *pSlave); +static s32 spi_loopback_polling_masterTx_slaveRx_test( + SPI_PortInfo_st *pMaster, SPI_PortInfo_st *pSlave); +static s32 spi_loopback_polling_masterRx_slaveTx_test( + SPI_PortInfo_st *pMaster, SPI_PortInfo_st *pSlave); +static s32 spi_loopback_portA_portB_polling_test( + SPI_PortInfo_st *pPortAInfo, SPI_PortInfo_st *pPortBInfo); static s32 spi_loopback_polling_test(SPI_CtrlInfo_st *pCtrlInfo); static s32 spi_loopback_test(void); #ifdef __cplusplus } #endif -#endif /* __ARCH_ARM_SRC_S5J_S5J_SPIDRV_H */ +#endif /* __ARCH_ARM_SRC_S5J_S5J_SPIDRV_H */ -- 2.7.4