From 6901aab8e35183115ae65362f3af0ea095b6c1b8 Mon Sep 17 00:00:00 2001
From: Jagan Teki <jagan@amarulasolutions.com>
Date: Fri, 11 Jan 2019 15:41:46 +0530
Subject: [PATCH] clk: sunxi: Add Allwinner A80 CLK driver

Add initial clock driver for Allwinner A80.

- Implement UART bus clocks via ccu_clk_gate table for
  A80, so it can accessed in common clk enable and disable
  functions from clk_sunxi.c
- Implement UART bus resets via ccu_reset table for A80,
  so it can accessed in common reset deassert and assert
  functions from reset-sunxi.c

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/clk/sunxi/Kconfig   |  7 +++++
 drivers/clk/sunxi/Makefile  |  1 +
 drivers/clk/sunxi/clk_a80.c | 57 +++++++++++++++++++++++++++++++++++++
 3 files changed, 65 insertions(+)
 create mode 100644 drivers/clk/sunxi/clk_a80.c

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index cb11c7c21e..5ff101b993 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -58,6 +58,13 @@ config CLK_SUN8I_V3S
 	  This enables common clock driver support for platforms based
 	  on Allwinner V3S SoC.
 
+config CLK_SUN9I_A80
+	bool "Clock driver for Allwinner A80"
+	default MACH_SUN9I
+	help
+	  This enables common clock driver support for platforms based
+	  on Allwinner A80 SoC.
+
 config CLK_SUN8I_H3
 	bool "Clock driver for Allwinner H3/H5"
 	default MACH_SUNXI_H3_H5
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 794aa2461c..36fb2aeb56 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
+obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
new file mode 100644
index 0000000000..d6dd6a1fa1
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Amarula Solutions.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/arch/ccu.h>
+#include <dt-bindings/clock/sun9i-a80-ccu.h>
+#include <dt-bindings/reset/sun9i-a80-ccu.h>
+
+static const struct ccu_clk_gate a80_gates[] = {
+	[CLK_BUS_UART0]		= GATE(0x594, BIT(16)),
+	[CLK_BUS_UART1]		= GATE(0x594, BIT(17)),
+	[CLK_BUS_UART2]		= GATE(0x594, BIT(18)),
+	[CLK_BUS_UART3]		= GATE(0x594, BIT(19)),
+	[CLK_BUS_UART4]		= GATE(0x594, BIT(20)),
+	[CLK_BUS_UART5]		= GATE(0x594, BIT(21)),
+};
+
+static const struct ccu_reset a80_resets[] = {
+	[RST_BUS_UART0]		= RESET(0x5b4, BIT(16)),
+	[RST_BUS_UART1]		= RESET(0x5b4, BIT(17)),
+	[RST_BUS_UART2]		= RESET(0x5b4, BIT(18)),
+	[RST_BUS_UART3]		= RESET(0x5b4, BIT(19)),
+	[RST_BUS_UART4]		= RESET(0x5b4, BIT(20)),
+	[RST_BUS_UART5]		= RESET(0x5b4, BIT(21)),
+};
+
+static const struct ccu_desc a80_ccu_desc = {
+	.gates = a80_gates,
+	.resets = a80_resets,
+};
+
+static int a80_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a80_resets));
+}
+
+static const struct udevice_id a80_ccu_ids[] = {
+	{ .compatible = "allwinner,sun9i-a80-ccu",
+	  .data = (ulong)&a80_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun9i_a80) = {
+	.name		= "sun9i_a80_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a80_ccu_ids,
+	.priv_auto_alloc_size	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a80_clk_bind,
+};
-- 
2.34.1