From 68bf6fe91b86fcdbdcda003b7b84764cf67db69d Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Mon, 31 Aug 2015 13:52:43 +0200 Subject: [PATCH] clk: samsung: exynos5422: fix MFC clock hierarchy parent Proper source for MFC block is mout_user_aclk333 (in datasheet named USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX. Signed-off-by: Marek Szyprowski --- drivers/clk/samsung/clk-exynos5420.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 5e70e4d12dbb..03cdea4f3789 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -930,7 +930,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = { GATE_BUS_TOP, 13, 0, 0), GATE(0, "aclk166", "mout_user_aclk166", GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0), - GATE(0, "aclk333", "mout_aclk333", + GATE(0, "aclk333", "mout_user_aclk333", GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0), GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), -- 2.34.1