From 68b49f7ef49eec068b7ddcf86c868e2a193e64e1 Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Mon, 17 Feb 2020 17:05:39 +0000 Subject: [PATCH] [ARM,MVE] Add intrinsics vclzq and vclsq. Summary: vclzq maps nicely to the existing target-independent @llvm.ctlz IR intrinsic. But vclsq ('count leading sign bits') has no corresponding target-independent intrinsic, so I've made up @llvm.arm.mve.vcls. This commit adds the unpredicated forms only. Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard Reviewed By: miyuki Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74335 --- clang/include/clang/Basic/arm_mve.td | 3 + clang/include/clang/Basic/arm_mve_defs.td | 6 ++ clang/test/CodeGen/arm-mve-intrinsics/vclz.c | 132 ++++++++++++++++++++++++ llvm/include/llvm/IR/IntrinsicsARM.td | 2 + llvm/lib/Target/ARM/ARMInstrMVE.td | 7 ++ llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll | 36 +++++++ 6 files changed, 186 insertions(+) create mode 100644 clang/test/CodeGen/arm-mve-intrinsics/vclz.c create mode 100644 llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll diff --git a/clang/include/clang/Basic/arm_mve.td b/clang/include/clang/Basic/arm_mve.td index 126c2e2..21801b4 100644 --- a/clang/include/clang/Basic/arm_mve.td +++ b/clang/include/clang/Basic/arm_mve.td @@ -237,8 +237,11 @@ let params = T.Unsigned in { let params = T.Int in { def vmvnq: Intrinsic; + def vclzq: Intrinsic $a, (i1 0))>; } let params = T.Signed in { + def vclsq: Intrinsic $a)>; def vnegq: Intrinsic; def vabsq: Intrinsic { let special_params = [IRBuilderIntParam<1, "unsigned">]; } +// Helper for making boolean flags in IR +def i1: IRBuilderBase { + let prefix = "llvm::ConstantInt::get(Builder.getInt1Ty(), "; + let special_params = [IRBuilderIntParam<0, "bool">]; +} + // A node that makes an Address out of a pointer-typed Value, by // providing an alignment as the second argument. def address; diff --git a/clang/test/CodeGen/arm-mve-intrinsics/vclz.c b/clang/test/CodeGen/arm-mve-intrinsics/vclz.c new file mode 100644 index 0000000..7a2ebe0 --- /dev/null +++ b/clang/test/CodeGen/arm-mve-intrinsics/vclz.c @@ -0,0 +1,132 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s + +#include + +// CHECK-LABEL: @test_vclzq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vclzq_s8(int8x16_t a) +{ +#ifdef POLYMORPHIC + return vclzq(a); +#else /* POLYMORPHIC */ + return vclzq_s8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclzq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vclzq_s16(int16x8_t a) +{ +#ifdef POLYMORPHIC + return vclzq(a); +#else /* POLYMORPHIC */ + return vclzq_s16(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclzq_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vclzq_s32(int32x4_t a) +{ +#ifdef POLYMORPHIC + return vclzq(a); +#else /* POLYMORPHIC */ + return vclzq_s32(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclzq_u8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +uint8x16_t test_vclzq_u8(uint8x16_t a) +{ +#ifdef POLYMORPHIC + return vclzq(a); +#else /* POLYMORPHIC */ + return vclzq_u8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclzq_u16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +uint16x8_t test_vclzq_u16(uint16x8_t a) +{ +#ifdef POLYMORPHIC + return vclzq(a); +#else /* POLYMORPHIC */ + return vclzq_u16(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclzq_u32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[A:%.*]], i1 false) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +uint32x4_t test_vclzq_u32(uint32x4_t a) +{ +#ifdef POLYMORPHIC + return vclzq(a); +#else /* POLYMORPHIC */ + return vclzq_u32(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclsq_s8( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> [[A:%.*]]) +// CHECK-NEXT: ret <16 x i8> [[TMP0]] +// +int8x16_t test_vclsq_s8(int8x16_t a) +{ +#ifdef POLYMORPHIC + return vclsq(a); +#else /* POLYMORPHIC */ + return vclsq_s8(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclsq_s16( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> [[A:%.*]]) +// CHECK-NEXT: ret <8 x i16> [[TMP0]] +// +int16x8_t test_vclsq_s16(int16x8_t a) +{ +#ifdef POLYMORPHIC + return vclsq(a); +#else /* POLYMORPHIC */ + return vclsq_s16(a); +#endif /* POLYMORPHIC */ +} + +// CHECK-LABEL: @test_vclsq_s32( +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> [[A:%.*]]) +// CHECK-NEXT: ret <4 x i32> [[TMP0]] +// +int32x4_t test_vclsq_s32(int32x4_t a) +{ +#ifdef POLYMORPHIC + return vclsq(a); +#else /* POLYMORPHIC */ + return vclsq_s32(a); +#endif /* POLYMORPHIC */ +} + diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td index 80ab3a7..0e8a523 100644 --- a/llvm/include/llvm/IR/IntrinsicsARM.td +++ b/llvm/include/llvm/IR/IntrinsicsARM.td @@ -1161,5 +1161,7 @@ defm int_arm_mve_vcvt_fix: MVEMXPredicated< def int_arm_mve_vrintn: Intrinsic< [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; +def int_arm_mve_vcls: Intrinsic< + [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; } // end TargetPrefix diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index b0ec2049..0583a26 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -2076,6 +2076,13 @@ let Predicates = [HasMVEInt] in { (v4i32 ( MVE_VCLZs32 (v4i32 MQPR:$val1)))>; def : Pat<(v8i16 ( ctlz (v8i16 MQPR:$val1))), (v8i16 ( MVE_VCLZs16 (v8i16 MQPR:$val1)))>; + + def : Pat<(v16i8 ( int_arm_mve_vcls (v16i8 MQPR:$val1))), + (v16i8 ( MVE_VCLSs8 (v16i8 MQPR:$val1)))>; + def : Pat<(v4i32 ( int_arm_mve_vcls (v4i32 MQPR:$val1))), + (v4i32 ( MVE_VCLSs32 (v4i32 MQPR:$val1)))>; + def : Pat<(v8i16 ( int_arm_mve_vcls (v8i16 MQPR:$val1))), + (v8i16 ( MVE_VCLSs16 (v8i16 MQPR:$val1)))>; } class MVE_VABSNEG_int size, bit negate, diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll new file mode 100644 index 0000000..788bf32 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vcls.ll @@ -0,0 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s + +define arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> %a) { +; CHECK-LABEL: test_vclsq_s8: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcls.s8 q0, q0 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %a) + ret <16 x i8> %0 +} + +define arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> %a) { +; CHECK-LABEL: test_vclsq_s16: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcls.s16 q0, q0 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %a) + ret <8 x i16> %0 +} + +define arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> %a) { +; CHECK-LABEL: test_vclsq_s32: +; CHECK: @ %bb.0: @ %entry +; CHECK-NEXT: vcls.s32 q0, q0 +; CHECK-NEXT: bx lr +entry: + %0 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %a) + ret <4 x i32> %0 +} + +declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>) +declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>) +declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>) -- 2.7.4