From 682e15f371db9b515d95fe9571983f1070bbc805 Mon Sep 17 00:00:00 2001 From: Quinn Pham Date: Thu, 16 Sep 2021 14:00:01 -0500 Subject: [PATCH] [PowerPC] Fix td pattern for P10 VSLDBI and VSRDBI This patch fixes the pattern for the P10 instructions Vector Shift Left Double by Bit Immediate VN-form and Vector Shift Right Double by Bit Immediate VN-form. The third argument should be a target constant (`timm`) instead of an `i32` because an immediate is expected. Reviewed By: lei Differential Revision: https://reviews.llvm.org/D109920 --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index c067946..de194b7 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -1927,7 +1927,7 @@ let Predicates = [IsISA3_1] in { [(set v16i8:$VRT, (int_ppc_altivec_vsldbi v16i8:$VRA, v16i8:$VRB, - i32:$SH))]>; + timm:$SH))]>; def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH), "vsrdbi $VRT, $VRA, $VRB, $SH", @@ -1935,7 +1935,7 @@ let Predicates = [IsISA3_1] in { [(set v16i8:$VRT, (int_ppc_altivec_vsrdbi v16i8:$VRA, v16i8:$VRB, - i32:$SH))]>; + timm:$SH))]>; defm VSTRIBR : VXForm_VTB5_RCr<13, 1, (outs vrrc:$vT), (ins vrrc:$vB), "vstribr", "$vT, $vB", IIC_VecGeneral, [(set v16i8:$vT, -- 2.7.4