From 6826d3c513b3366edb6b8fde769b4c5d90c4be19 Mon Sep 17 00:00:00 2001 From: Dmitry Makogon Date: Mon, 19 Jun 2023 15:49:47 +0700 Subject: [PATCH] [Test] Add test for PR62430 showing bug in SCEV mul expression creation (NFC) --- llvm/test/Analysis/ScalarEvolution/pr62430.ll | 75 +++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 llvm/test/Analysis/ScalarEvolution/pr62430.ll diff --git a/llvm/test/Analysis/ScalarEvolution/pr62430.ll b/llvm/test/Analysis/ScalarEvolution/pr62430.ll new file mode 100644 index 0000000..7aea144 --- /dev/null +++ b/llvm/test/Analysis/ScalarEvolution/pr62430.ll @@ -0,0 +1,75 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; RUN: opt -loop-reduce -S < %s | FileCheck %s + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2" +target triple = "x86_64-unknown-linux-gnu" + +define void @test() { +; CHECK-LABEL: define void @test() { +; CHECK-NEXT: bb: +; CHECK-NEXT: br label [[BB3:%.*]] +; CHECK: bb3: +; CHECK-NEXT: [[LSR_IV13:%.*]] = phi i32 [ [[LSR_IV_NEXT14:%.*]], [[BB7:%.*]] ], [ 0, [[BB:%.*]] ] +; CHECK-NEXT: [[LSR_IV11:%.*]] = phi i32 [ [[LSR_IV_NEXT12:%.*]], [[BB7]] ], [ 98304, [[BB]] ] +; CHECK-NEXT: [[LSR_IV9:%.*]] = phi i32 [ [[LSR_IV_NEXT10:%.*]], [[BB7]] ], [ 0, [[BB]] ] +; CHECK-NEXT: [[LSR_IV7:%.*]] = phi i32 [ [[LSR_IV_NEXT8:%.*]], [[BB7]] ], [ 147456, [[BB]] ] +; CHECK-NEXT: [[LSR_IV5:%.*]] = phi i32 [ [[LSR_IV_NEXT6:%.*]], [[BB7]] ], [ 0, [[BB]] ] +; CHECK-NEXT: [[LSR_IV3:%.*]] = phi i32 [ [[LSR_IV_NEXT4:%.*]], [[BB7]] ], [ 57344, [[BB]] ] +; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB7]] ], [ 0, [[BB]] ] +; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], [[BB7]] ], [ 4096, [[BB]] ] +; CHECK-NEXT: br label [[BB4:%.*]] +; CHECK: bb4: +; CHECK-NEXT: [[LSR_IV21:%.*]] = phi i32 [ [[LSR_IV_NEXT22:%.*]], [[BB6:%.*]] ], [ 0, [[BB3]] ] +; CHECK-NEXT: [[LSR_IV19:%.*]] = phi i32 [ [[LSR_IV_NEXT20:%.*]], [[BB6]] ], [ [[LSR_IV1]], [[BB3]] ] +; CHECK-NEXT: [[LSR_IV17:%.*]] = phi i32 [ [[LSR_IV_NEXT18:%.*]], [[BB6]] ], [ [[LSR_IV5]], [[BB3]] ] +; CHECK-NEXT: [[LSR_IV15:%.*]] = phi i32 [ [[LSR_IV_NEXT16:%.*]], [[BB6]] ], [ [[LSR_IV9]], [[BB3]] ] +; CHECK-NEXT: br i1 true, label [[BB7]], label [[BB6]] +; CHECK: bb6: +; CHECK-NEXT: [[LSR_IV_NEXT16]] = add i32 [[LSR_IV15]], [[LSR_IV13]] +; CHECK-NEXT: [[LSR_IV_NEXT18]] = add i32 [[LSR_IV17]], [[LSR_IV15]] +; CHECK-NEXT: [[LSR_IV_NEXT20]] = add i32 [[LSR_IV19]], [[LSR_IV17]] +; CHECK-NEXT: [[LSR_IV_NEXT22]] = add i32 [[LSR_IV21]], [[LSR_IV19]] +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb7: +; CHECK-NEXT: call void @foo(i32 [[LSR_IV21]]) +; CHECK-NEXT: [[SEXT:%.*]] = sext i32 [[LSR_IV21]] to i64 +; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 8192 +; CHECK-NEXT: [[LSR_IV_NEXT2]] = add i32 [[LSR_IV1]], [[LSR_IV]] +; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i32 [[LSR_IV3]], 114688 +; CHECK-NEXT: [[LSR_IV_NEXT6]] = add i32 [[LSR_IV5]], [[LSR_IV3]] +; CHECK-NEXT: [[LSR_IV_NEXT8]] = add i32 [[LSR_IV7]], 294912 +; CHECK-NEXT: [[LSR_IV_NEXT10]] = add i32 [[LSR_IV9]], [[LSR_IV7]] +; CHECK-NEXT: [[LSR_IV_NEXT12]] = add i32 [[LSR_IV11]], 196608 +; CHECK-NEXT: [[LSR_IV_NEXT14]] = add i32 [[LSR_IV13]], [[LSR_IV11]] +; CHECK-NEXT: br label [[BB3]] +; +bb: + br label %bb3 + +bb3: ; preds = %bb7, %bb + %phi = phi i64 [ 0, %bb ], [ %add11, %bb7 ] + br label %bb4 + +bb4: ; preds = %bb6, %bb3 + %phi5 = phi i32 [ 0, %bb3 ], [ %add, %bb6 ] + br i1 true, label %bb7, label %bb6 + +bb6: ; preds = %bb4 + %add = add i32 %phi5, 8 + br label %bb4 + +bb7: ; preds = %bb4 + %shl = shl i32 %phi5, 25 + %mul = mul i64 %phi, %phi + %trunc = trunc i64 %mul to i32 + %add8 = add i32 %shl, %trunc + %mul9 = mul i32 %add8, %add8 + %mul10 = mul i32 %mul9, %add8 + call void @foo(i32 %mul10) + %sext = sext i32 %mul10 to i64 + %add11 = add i64 %phi, 4 + br label %bb3 +} + +declare void @foo(i32) + -- 2.7.4