From 681b9466c9209ee6c7209761a309fb78c6fa1ef6 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 26 Mar 2022 17:25:34 -0400
Subject: [PATCH] RegAllocGreedy: Remove redundant check for virtual registers

The set of interfering virtual registers obviously only includes
virtual registers.
---
 llvm/lib/CodeGen/RegAllocGreedy.cpp | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 80d796d1ad92..029f05d0b507 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -460,9 +460,6 @@ bool RAGreedy::canEvictInterferenceInRange(const LiveInterval &VirtReg,
       if (!Intf->overlaps(Start, End))
         continue;
 
-      // Cannot evict non virtual reg interference.
-      if (!Register::isVirtualRegister(Intf->reg()))
-        return false;
       // Never evict spill products. They cannot split or spill.
       if (ExtraInfo->getStage(*Intf) == RS_Done)
         return false;
-- 
2.34.1