From 6812d74803740100a0c422b9bc1fda947af4da6a Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Mon, 8 May 2023 16:08:37 -0400 Subject: [PATCH] drm/amd/display: Update SR watermarks for DCN314 [Why & How] Update parameters for SR watermarks for DCN314 Reviewed-by: Charlene Liu Acked-by: Tom Chung Signed-off-by: Nicholas Kazlauskas Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c index 4d5cd59..2a0c696 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c @@ -403,32 +403,32 @@ static struct wm_table lpddr5_wm_table = { .wm_inst = WM_A, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 16.5, - .sr_enter_plus_exit_time_us = 18.5, + .sr_exit_time_us = 30.0, + .sr_enter_plus_exit_time_us = 32.0, .valid = true, }, { .wm_inst = WM_B, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 16.5, - .sr_enter_plus_exit_time_us = 18.5, + .sr_exit_time_us = 30.0, + .sr_enter_plus_exit_time_us = 32.0, .valid = true, }, { .wm_inst = WM_C, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 16.5, - .sr_enter_plus_exit_time_us = 18.5, + .sr_exit_time_us = 30.0, + .sr_enter_plus_exit_time_us = 32.0, .valid = true, }, { .wm_inst = WM_D, .wm_type = WM_TYPE_PSTATE_CHG, .pstate_latency_us = 11.65333, - .sr_exit_time_us = 16.5, - .sr_enter_plus_exit_time_us = 18.5, + .sr_exit_time_us = 30.0, + .sr_enter_plus_exit_time_us = 32.0, .valid = true, }, } -- 2.7.4