From 67ddcd6dd08f31c74b4c6662aeb9574651d0c7c7 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 11 Jul 2013 08:37:13 +0000 Subject: [PATCH] [SystemZ] Allow 8-bit operands to RISBG RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. llvm-svn: 186070 --- llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 3 +-- llvm/test/MC/Disassembler/SystemZ/insns.txt | 8 ++++---- llvm/test/MC/SystemZ/insn-bad.s | 8 ++++---- llvm/test/MC/SystemZ/insn-good.s | 8 ++++---- 4 files changed, 13 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index fb530cc..7300b90 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -1020,8 +1020,7 @@ multiclass CmpSwapRSPair rsOpcode, bits<16> rsyOpcode, class RotateSelectRIEf opcode, RegisterOperand cls1, RegisterOperand cls2> : InstRIEf { let Constraints = "$R1 = $R1src"; let DisableEncoding = "$R1src"; diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt index 56236f7..664ae807 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt @@ -4642,11 +4642,11 @@ # CHECK: risbg %r0, %r0, 0, 0, 63 0xec 0x00 0x00 0x00 0x3f 0x55 -# CHECK: risbg %r0, %r0, 0, 63, 0 -0xec 0x00 0x00 0x3f 0x00 0x55 +# CHECK: risbg %r0, %r0, 0, 255, 0 +0xec 0x00 0x00 0xff 0x00 0x55 -# CHECK: risbg %r0, %r0, 63, 0, 0 -0xec 0x00 0x3f 0x00 0x00 0x55 +# CHECK: risbg %r0, %r0, 255, 0, 0 +0xec 0x00 0xff 0x00 0x00 0x55 # CHECK: risbg %r0, %r15, 0, 0, 0 0xec 0x0f 0x00 0x00 0x00 0x55 diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s index 24c7747..ea9a7ed 100644 --- a/llvm/test/MC/SystemZ/insn-bad.s +++ b/llvm/test/MC/SystemZ/insn-bad.s @@ -2102,18 +2102,18 @@ #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,-1,0 #CHECK: error: invalid operand -#CHECK: risbg %r0,%r0,0,64,0 +#CHECK: risbg %r0,%r0,0,256,0 #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,-1,0,0 #CHECK: error: invalid operand -#CHECK: risbg %r0,%r0,64,0,0 +#CHECK: risbg %r0,%r0,256,0,0 risbg %r0,%r0,0,0,-1 risbg %r0,%r0,0,0,64 risbg %r0,%r0,0,-1,0 - risbg %r0,%r0,0,64,0 + risbg %r0,%r0,0,256,0 risbg %r0,%r0,-1,0,0 - risbg %r0,%r0,64,0,0 + risbg %r0,%r0,256,0,0 #CHECK: error: invalid operand #CHECK: rll %r0,%r0,-524289 diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s index 2309dfb..3adfa98 100644 --- a/llvm/test/MC/SystemZ/insn-good.s +++ b/llvm/test/MC/SystemZ/insn-good.s @@ -5835,16 +5835,16 @@ #CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55] #CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] -#CHECK: risbg %r0, %r0, 0, 63, 0 # encoding: [0xec,0x00,0x00,0x3f,0x00,0x55] -#CHECK: risbg %r0, %r0, 63, 0, 0 # encoding: [0xec,0x00,0x3f,0x00,0x00,0x55] +#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] +#CHECK: risbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x55] #CHECK: risbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55] #CHECK: risbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55] #CHECK: risbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x55] risbg %r0,%r0,0,0,0 risbg %r0,%r0,0,0,63 - risbg %r0,%r0,0,63,0 - risbg %r0,%r0,63,0,0 + risbg %r0,%r0,0,255,0 + risbg %r0,%r0,255,0,0 risbg %r0,%r15,0,0,0 risbg %r15,%r0,0,0,0 risbg %r4,%r5,6,7,8 -- 2.7.4