From 67bf1da27269bd54bd9fb61fa4293e8e758ba82a Mon Sep 17 00:00:00 2001 From: Zhigang Gong Date: Thu, 29 Aug 2013 14:27:05 +0800 Subject: [PATCH] GBE: don't use flag register as src 1 for xor instruction. Gen doesn't support to use ARF as src1. This bug is reported by Edward Ching . v2: add an assert at setSrc1 to check whether we encode an instruction which is using ARF as SRC1. Signed-off-by: Zhigang Gong Tested-by: Edward Ching --- backend/src/backend/gen_encoder.cpp | 1 + backend/src/backend/gen_reg_allocation.cpp | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/backend/src/backend/gen_encoder.cpp b/backend/src/backend/gen_encoder.cpp index 1a459e1..cde7b48 100644 --- a/backend/src/backend/gen_encoder.cpp +++ b/backend/src/backend/gen_encoder.cpp @@ -315,6 +315,7 @@ namespace gbe void GenEncoder::setSrc1(GenInstruction *insn, GenRegister reg) { assert(reg.nr < 128); + assert(reg.file != GEN_ARCHITECTURE_REGISTER_FILE); insn->bits1.da1.src1_reg_file = reg.file; insn->bits1.da1.src1_reg_type = reg.type; diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp index a765917..0bb75a2 100644 --- a/backend/src/backend/gen_reg_allocation.cpp +++ b/backend/src/backend/gen_reg_allocation.cpp @@ -645,7 +645,8 @@ namespace gbe // Flag registers can only go to src[0] const SelectionOpcode opcode = SelectionOpcode(insn.opcode); - if (opcode == SEL_OP_AND || opcode == SEL_OP_OR) { + if (opcode == SEL_OP_AND || opcode == SEL_OP_OR || opcode == SEL_OP_XOR + || opcode == SEL_OP_I64AND || opcode == SEL_OP_I64OR || opcode == SEL_OP_I64XOR) { if (insn.src(1).physical == 0) { const ir::Register reg = insn.src(1).reg(); if (ctx.sel->getRegisterFamily(reg) == ir::FAMILY_BOOL) -- 2.7.4