From 67826a5883da8c45464c52fa86f36c684b5f8cf6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 1 Feb 2015 07:35:40 +0000 Subject: [PATCH] [X86] Rename _mm512_valign_epi64/32 intrinsics to _mm512_alignr_epi64/32 to match Intel docs. Make immediate argument to them an ICE. Fix mask size for the alignd version. llvm-svn: 227713 --- clang/include/clang/Basic/BuiltinsX86.def | 4 ++-- clang/lib/Headers/avx512fintrin.h | 28 ++++++++++------------------ clang/test/CodeGen/avx512f-builtins.c | 13 ++++++++++--- 3 files changed, 22 insertions(+), 23 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsX86.def b/clang/include/clang/Basic/BuiltinsX86.def index 8cd7d53..6cf30a0 100644 --- a/clang/include/clang/Basic/BuiltinsX86.def +++ b/clang/include/clang/Basic/BuiltinsX86.def @@ -922,8 +922,8 @@ BUILTIN(__builtin_ia32_vpermt2vard512_mask, "V16iV16iV16iV16iUs", "") BUILTIN(__builtin_ia32_vpermt2varq512_mask, "V8LLiV8LLiV8LLiV8LLiUc", "") BUILTIN(__builtin_ia32_vpermt2varps512_mask, "V16fV16iV16fV16fUs", "") BUILTIN(__builtin_ia32_vpermt2varpd512_mask, "V8dV8LLiV8dV8dUc", "") -BUILTIN(__builtin_ia32_alignq512_mask, "V8LLiV8LLiV8LLiUcV8LLiUc", "") -BUILTIN(__builtin_ia32_alignd512_mask, "V16iV16iV16iUcV16iUc", "") +BUILTIN(__builtin_ia32_alignq512_mask, "V8LLiV8LLiV8LLiIcV8LLiUc", "") +BUILTIN(__builtin_ia32_alignd512_mask, "V16iV16iV16iIcV16iUs", "") BUILTIN(__builtin_ia32_extractf64x4_mask, "V4dV8dIcV4dUc", "") BUILTIN(__builtin_ia32_extractf32x4_mask, "V4fV16fIcV4fUc", "") BUILTIN(__builtin_ia32_gathersiv8df, "V8dV8dvC*V8iUcIi", "") diff --git a/clang/lib/Headers/avx512fintrin.h b/clang/lib/Headers/avx512fintrin.h index 8aa6cec..09b29fa 100644 --- a/clang/lib/Headers/avx512fintrin.h +++ b/clang/lib/Headers/avx512fintrin.h @@ -606,25 +606,17 @@ _mm512_permutex2var_ps(__m512 __A, __m512i __I, __m512 __B) (__mmask16) -1); } -static __inline __m512i __attribute__ ((__always_inline__, __nodebug__)) -_mm512_valign_epi64(__m512i __A, __m512i __B, const int __I) -{ - return (__m512i) __builtin_ia32_alignq512_mask((__v8di)__A, - (__v8di)__B, - __I, - (__v8di)_mm512_setzero_si512(), - (__mmask8) -1); -} +#define _mm512_alignr_epi64(A, B, I) __extension__ ({ \ + (__m512i)__builtin_ia32_alignq512_mask((__v8di)(__m512i)(A), \ + (__v8di)(__m512i)(B), \ + (I), (__v8di)_mm512_setzero_si512(), \ + (__mmask8)-1); }) -static __inline __m512i __attribute__ ((__always_inline__, __nodebug__)) -_mm512_valign_epi32(__m512i __A, __m512i __B, const int __I) -{ - return (__m512i)__builtin_ia32_alignd512_mask((__v16si)__A, - (__v16si)__B, - __I, - (__v16si)_mm512_setzero_si512(), - (__mmask16) -1); -} +#define _mm512_alignr_epi32(A, B, I) __extension__ ({ \ + (__m512i)__builtin_ia32_alignd512_mask((__v16si)(__m512i)(A), \ + (__v16si)(__m512i)(B), \ + (I), (__v16si)_mm512_setzero_si512(), \ + (__mmask16)-1); }) /* Vector Extract */ diff --git a/clang/test/CodeGen/avx512f-builtins.c b/clang/test/CodeGen/avx512f-builtins.c index 4f11b52..1e22da8 100644 --- a/clang/test/CodeGen/avx512f-builtins.c +++ b/clang/test/CodeGen/avx512f-builtins.c @@ -173,11 +173,18 @@ __mmask16 test_mm512_knot(__mmask16 a) return _mm512_knot(a); } -__m512i test_mm512_valign_epi64(__m512i a, __m512i b) +__m512i test_mm512_alignr_epi32(__m512i a, __m512i b) { - // CHECK-LABEL: @test_mm512_valign_epi64 + // CHECK-LABEL: @test_mm512_alignr_epi32 + // CHECK: @llvm.x86.avx512.mask.valign.d.512 + return _mm512_alignr_epi32(a, b, 2); +} + +__m512i test_mm512_alignr_epi64(__m512i a, __m512i b) +{ + // CHECK-LABEL: @test_mm512_alignr_epi64 // CHECK: @llvm.x86.avx512.mask.valign.q.512 - return _mm512_valign_epi64(a, b, 2); + return _mm512_alignr_epi64(a, b, 2); } __m512d test_mm512_broadcastsd_pd(__m128d a) -- 2.7.4