From 676b4087fcb44f9816eaeb21261ed25dd3f3c822 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 10 May 2017 16:18:34 +0800 Subject: [PATCH] drm/amd/powerplay: convert from number of lanes to lane bits on vega10 We need a mask. Signed-off-by: Rex Zhu Reviewws-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c index 48803eb..c16c37e 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c @@ -1170,12 +1170,12 @@ static int vega10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) bios_pcie_table->entries[i].gen_speed; if (data->registry_data.pcieLaneOverride) - pcie_table->pcie_lane[i] = - data->registry_data.pcieLaneOverride; + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + data->registry_data.pcieLaneOverride); else - pcie_table->pcie_lane[i] = - bios_pcie_table->entries[i].lane_width; - + pcie_table->pcie_lane[i] = (uint8_t)encode_pcie_lane_width( + bios_pcie_table->entries[i].lane_width); + printk("pcie_table->pcie_lane[%d] is %d %d\n", i, pcie_table->pcie_lane[i], bios_pcie_table->entries[i].lane_width); if (data->registry_data.pcieClockOverride) pcie_table->lclk[i] = data->registry_data.pcieClockOverride; -- 2.7.4