From 6753bb2c41264aed432ffb90d2b0291d0cdb9289 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 26 Apr 2022 17:01:02 +0100 Subject: [PATCH] [AMDGPU] Precommit a test case for D124450 --- llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll | 49 ++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll diff --git a/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll b/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll new file mode 100644 index 0000000..894833e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/setcc-multiple-use.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -march=amdgcn -mcpu=gfx1030 < %s | FileCheck %s + +; SelectionDAG generates a setcc node with multiple uses: +; +; t23: i1 = setcc t3, Constant:i32<0>, setne:ch +; t17: i32,i1 = subcarry Constant:i32<1>, Constant:i32<0>, t23 +; t25: i32 = select t23, t17, Constant:i32<0> + +define amdgpu_cs void @main() { +; CHECK-LABEL: main: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: v_mov_b32_e32 v0, 0 +; CHECK-NEXT: ds_read_b32 v1, v0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 +; CHECK-NEXT: s_cmpk_lg_u32 vcc_lo, 0x0 +; CHECK-NEXT: s_subb_u32 s0, 1, 0 +; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, s0, vcc_lo +; CHECK-NEXT: .LBB0_1: ; %bb1 +; CHECK-NEXT: ; =>This Loop Header: Depth=1 +; CHECK-NEXT: ; Child Loop BB0_2 Depth 2 +; CHECK-NEXT: v_cmp_eq_u32_e64 s0, 0, v0 +; CHECK-NEXT: .LBB0_2: ; %bb3 +; CHECK-NEXT: ; Parent Loop BB0_1 Depth=1 +; CHECK-NEXT: ; => This Inner Loop Header: Depth=2 +; CHECK-NEXT: v_mov_b32_e32 v0, v1 +; CHECK-NEXT: s_and_b32 vcc_lo, exec_lo, s0 +; CHECK-NEXT: s_cbranch_vccz .LBB0_2 +; CHECK-NEXT: s_branch .LBB0_1 +bb: + %i = load i32, i32 addrspace(3)* null, align 16 + br label %bb1 + +bb1: + %i2 = phi i32 [ 0, %bb ], [ %i9, %bb5 ] + br label %bb3 + +bb3: + %i4 = icmp eq i32 %i2, 0 + br i1 %i4, label %bb5, label %bb3 + +bb5: + %i6 = icmp ult i32 0, %i + %i7 = sext i1 %i6 to i32 + %i8 = add i32 %i7, 1 + %i9 = and i32 %i8, %i7 + br label %bb1 +} -- 2.7.4