From 66ea30c7bc926806dcfedd54ac9a17f7baeccbeb Mon Sep 17 00:00:00 2001 From: Thomas Lively Date: Thu, 29 Nov 2018 22:01:01 +0000 Subject: [PATCH] [WebAssembly] Expand unavailable integer operations for vectors Summary: Expands for vector types all of the integer operations that are expanded for scalars because they are not supported at all by WebAssembly. This CL has no tests because such tests would really be testing the target-independent expansion, but I'm happy to add tests if reviewers think it would be helpful. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55010 llvm-svn: 347923 --- .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index 418ceca..a038215 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -123,14 +123,22 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering( for (auto Op : {ISD::SADDSAT, ISD::UADDSAT}) setOperationAction(Op, T, Legal); - for (auto T : {MVT::i32, MVT::i64}) { - // Expand unavailable integer operations. - for (auto Op : - {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, - ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, - ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { + // Expand unavailable integer operations. + for (auto Op : + {ISD::BSWAP, ISD::SMUL_LOHI, ISD::UMUL_LOHI, ISD::MULHS, ISD::MULHU, + ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, ISD::SRA_PARTS, + ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { + for (auto T : {MVT::i32, MVT::i64}) { setOperationAction(Op, T, Expand); } + if (Subtarget->hasSIMD128()) { + for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) { + setOperationAction(Op, T, Expand); + } + if (EnableUnimplementedWasmSIMDInstrs) { + setOperationAction(Op, MVT::v2i64, Expand); + } + } } // There is no i64x2.mul instruction -- 2.7.4