From 66d60e06cbc51b453f9e38ad69795f9487213fe5 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 23 Jul 2020 21:11:46 -0400 Subject: [PATCH] AMDGPU: Serialize MFI spill fields These should probably be inferred from the function on parse, but the target specific infrastructure currently does not give you a way to do this. SILowerSGPRSpills early exits without this reporting spills, which makes it difficult to write a MIR test for. --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 4 ++++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++++ .../MIR/AMDGPU/machine-function-info-no-ir.mir | 26 ++++++++++++++++++++++ .../CodeGen/MIR/AMDGPU/machine-function-info.ll | 8 +++++++ 4 files changed, 42 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 788e987..441bad0 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -546,6 +546,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()), MemoryBound(MFI.isMemoryBound()), WaveLimiter(MFI.needsWaveLimiter()), + HasSpilledSGPRs(MFI.hasSpilledSGPRs()), + HasSpilledVGPRs(MFI.hasSpilledVGPRs()), HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()), ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), @@ -567,6 +569,8 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields( NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath; MemoryBound = YamlMFI.MemoryBound; WaveLimiter = YamlMFI.WaveLimiter; + HasSpilledSGPRs = YamlMFI.HasSpilledSGPRs; + HasSpilledVGPRs = YamlMFI.HasSpilledVGPRs; return false; } diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 57a89d9..d9a2d3a 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -281,6 +281,8 @@ struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo { bool NoSignedZerosFPMath = false; bool MemoryBound = false; bool WaveLimiter = false; + bool HasSpilledSGPRs = false; + bool HasSpilledVGPRs = false; uint32_t HighBitsOf32BitAddress = 0; StringValue ScratchRSrcReg = "$private_rsrc_reg"; @@ -308,6 +310,8 @@ template <> struct MappingTraits { YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false); YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false); YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false); + YamlIO.mapOptional("hasSpilledSGPRs", MFI.HasSpilledSGPRs, false); + YamlIO.mapOptional("hasSpilledVGPRs", MFI.HasSpilledVGPRs, false); YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg, StringValue("$private_rsrc_reg")); YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg, diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir index e39ff3b..5d4eae6 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir @@ -12,6 +12,8 @@ # FULL-NEXT: noSignedZerosFPMath: false # FULL-NEXT: memoryBound: true # FULL-NEXT: waveLimiter: true +# FULL-NEXT: hasSpilledSGPRs: false +# FULL-NEXT: hasSpilledVGPRs: false # FULL-NEXT: scratchRSrcReg: '$sgpr8_sgpr9_sgpr10_sgpr11' # FULL-NEXT: frameOffsetReg: '$sgpr12' # FULL-NEXT: stackPtrOffsetReg: '$sgpr13' @@ -83,6 +85,8 @@ body: | # FULL-NEXT: noSignedZerosFPMath: false # FULL-NEXT: memoryBound: false # FULL-NEXT: waveLimiter: false +# FULL-NEXT: hasSpilledSGPRs: false +# FULL-NEXT: hasSpilledVGPRs: false # FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' @@ -121,6 +125,8 @@ body: | # FULL-NEXT: noSignedZerosFPMath: false # FULL-NEXT: memoryBound: false # FULL-NEXT: waveLimiter: false +# FULL-NEXT: hasSpilledSGPRs: false +# FULL-NEXT: hasSpilledVGPRs: false # FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' @@ -160,6 +166,8 @@ body: | # FULL-NEXT: noSignedZerosFPMath: false # FULL-NEXT: memoryBound: false # FULL-NEXT: waveLimiter: false +# FULL-NEXT: hasSpilledSGPRs: false +# FULL-NEXT: hasSpilledVGPRs: false # FULL-NEXT: scratchRSrcReg: '$private_rsrc_reg' # FULL-NEXT: frameOffsetReg: '$fp_reg' # FULL-NEXT: stackPtrOffsetReg: '$sp_reg' @@ -259,3 +267,21 @@ body: | S_ENDPGM 0 ... + + +--- +# ALL-LABEL: name: parse_spilled_regs +# ALL: machineFunctionInfo: +# ALL: hasSpilledSGPRs: true +# ALL-NEXT: hasSpilledVGPRs: true + +name: parse_spilled_regs +machineFunctionInfo: + hasSpilledSGPRs: true + hasSpilledVGPRs: true + +body: | + bb.0: + S_ENDPGM 0 + +... diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll index 94f926e..b6a0476 100644 --- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll +++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll @@ -15,6 +15,8 @@ ; CHECK-NEXT: noSignedZerosFPMath: false ; CHECK-NEXT: memoryBound: false ; CHECK-NEXT: waveLimiter: false +; CHECK-NEXT: hasSpilledSGPRs: false +; CHECK-NEXT: hasSpilledVGPRs: false ; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' ; CHECK-NEXT: frameOffsetReg: '$fp_reg' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' @@ -48,6 +50,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) { ; CHECK-NEXT: noSignedZerosFPMath: false ; CHECK-NEXT: memoryBound: false ; CHECK-NEXT: waveLimiter: false +; CHECK-NEXT: hasSpilledSGPRs: false +; CHECK-NEXT: hasSpilledVGPRs: false ; CHECK-NEXT: scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99' ; CHECK-NEXT: frameOffsetReg: '$fp_reg' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' @@ -76,6 +80,8 @@ define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) { ; CHECK-NEXT: noSignedZerosFPMath: false ; CHECK-NEXT: memoryBound: false ; CHECK-NEXT: waveLimiter: false +; CHECK-NEXT: hasSpilledSGPRs: false +; CHECK-NEXT: hasSpilledVGPRs: false ; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' ; CHECK-NEXT: frameOffsetReg: '$sgpr33' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' @@ -103,6 +109,8 @@ define void @function() { ; CHECK-NEXT: noSignedZerosFPMath: true ; CHECK-NEXT: memoryBound: false ; CHECK-NEXT: waveLimiter: false +; CHECK-NEXT: hasSpilledSGPRs: false +; CHECK-NEXT: hasSpilledVGPRs: false ; CHECK-NEXT: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' ; CHECK-NEXT: frameOffsetReg: '$sgpr33' ; CHECK-NEXT: stackPtrOffsetReg: '$sgpr32' -- 2.7.4