From 66d141a15c19f89e7e259e57a007550a253e03d2 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 19 May 2023 19:08:43 +0530 Subject: [PATCH] arm64: dts: qcom: ipq5332: define UART1 Add the definition for the UART1 found on IPQ5332 SoC. Reviewed-by: Bhupesh Sharma Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230519133844.23512-3-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 4798403..e7d3ec7 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -225,6 +225,18 @@ status = "disabled"; }; + blsp1_uart1: serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078b0000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + blsp1_spi0: spi@78b5000 { compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; -- 2.7.4