From 66bdbe7cca55d6810b3fb07f976406c1e9d96be5 Mon Sep 17 00:00:00 2001 From: Yong Qin Date: Mon, 1 Apr 2019 14:56:44 +0800 Subject: [PATCH] di: bringup for tm2 [1/1] PD#SWPL-6575 Problem: chip bring up Solution: 1.add tm2 chip id for tm2 2.add h scaling down function for tm2 Verify: tm2 Change-Id: I364d7c07be331d81ef546357445225c6071f8e3c Signed-off-by: Yong Qin --- drivers/amlogic/media/deinterlace/deinterlace.c | 47 ++++++++++++---- drivers/amlogic/media/deinterlace/deinterlace.h | 1 + .../amlogic/media/deinterlace/deinterlace_dbg.c | 2 +- drivers/amlogic/media/deinterlace/deinterlace_hw.c | 19 +++---- .../amlogic/media/deinterlace/deinterlace_mtn.c | 2 +- drivers/amlogic/media/deinterlace/di_pps.c | 62 +++++++++++++++++++++- drivers/amlogic/media/deinterlace/di_pps.h | 9 ++++ drivers/amlogic/media/deinterlace/nr_drv.c | 34 +++++------- drivers/amlogic/media/deinterlace/register.h | 9 ++++ 9 files changed, 143 insertions(+), 42 deletions(-) diff --git a/drivers/amlogic/media/deinterlace/deinterlace.c b/drivers/amlogic/media/deinterlace/deinterlace.c index 8da4595..8da7afd 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.c +++ b/drivers/amlogic/media/deinterlace/deinterlace.c @@ -129,7 +129,7 @@ static di_dev_t *de_devp; static dev_t di_devno; static struct class *di_clsp; -static const char version_s[] = "2019-02-26a sm1 buring up test"; +static const char version_s[] = "2019-0401:TM2 bring up"; static int bypass_state = 1; static int bypass_all; @@ -3482,6 +3482,11 @@ module_param_named(pps_position, pps_position, uint, 0644); static unsigned int pre_enable_mask = 3;/*bit0:ma bit1:mc*/ module_param_named(pre_enable_mask, pre_enable_mask, uint, 0644); +static bool pre_hsc_down_en; +module_param_named(pre_hsc_down_en, pre_hsc_down_en, bool, 0644); +static int pre_hsc_down_width = 480; +module_param_named(pre_hsc_down_width, pre_hsc_down_width, int, 0644); + static unsigned char pre_de_buf_config(void) { struct di_buf_s *di_buf = NULL; @@ -4026,7 +4031,15 @@ jiffies_to_msecs(jiffies_64 - vframe->ready_jiffies64)); } if (pps_dsth != di_buf->vframe->height) di_buf->vframe->height = pps_dsth; + } else if (de_devp->h_sc_down_en) { + if (pre_hsc_down_width != di_buf->vframe->width) { + pr_info("di: hscd %d to %d\n", di_buf->vframe->width, + pre_hsc_down_width); + di_buf->vframe->width = pre_hsc_down_width; + di_pre_stru.width_bk = pre_hsc_down_width; + } } + if (di_force_bit_mode == 10) { di_buf->vframe->bitdepth |= (BITDEPTH_Y10); if (full_422_pack) @@ -5249,6 +5262,7 @@ de_post_process(void *arg, unsigned int zoom_start_x_lines, is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu() || + is_meson_tm2_cpu() || is_meson_sm1_cpu()) { di_post_read_reverse_irq(overturn, mc_pre_flag, post_blend_en ? mcpre_en : false); @@ -6040,7 +6054,8 @@ static void di_unreg_process_irq(void) di_hw_uninit(); if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() - || is_meson_tl1_cpu() || is_meson_sm1_cpu()) { + || is_meson_tl1_cpu() || is_meson_sm1_cpu() || + is_meson_tm2_cpu()) { di_pre_gate_control(false, mcpre_en); nr_gate_control(false); } else if (cpu_after_eq(MESON_CPU_MAJOR_ID_GXTVBB)) { @@ -6053,7 +6068,8 @@ static void di_unreg_process_irq(void) di_hw_disable(mcpre_en); if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() - || is_meson_tl1_cpu() || is_meson_sm1_cpu()) { + || is_meson_tl1_cpu() || is_meson_sm1_cpu() || + is_meson_tm2_cpu()) { enable_di_post_mif(GATE_OFF); di_post_gate_control(false); di_top_gate_control(false, false); @@ -6166,7 +6182,7 @@ static void di_pre_size_change(unsigned short width, is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || - is_meson_tl1_cpu() || + is_meson_tl1_cpu() || is_meson_tm2_cpu() || is_meson_sm1_cpu()) film_mode_win_config(width, height); } @@ -6199,6 +6215,15 @@ static void di_pre_size_change(unsigned short width, pps_h = di_pre_stru.cur_height>>1; di_pps_config(1, pps_w, pps_h, pps_dstw, (pps_dsth>>1)); } + + if (de_devp->h_sc_down_en) { + pps_w = di_pre_stru.cur_width; + di_inp_hsc_setting(pps_w, pre_hsc_down_width); + } else { + di_inp_hsc_setting(di_pre_stru.cur_width, + di_pre_stru.cur_width); + } + di_interrupt_ctrl(di_pre_stru.madi_enable, det3d_en?1:0, de_devp->nrds_enable, @@ -6297,6 +6322,8 @@ static void di_reg_process_irq(void) } de_devp->nrds_enable = nrds_en; de_devp->pps_enable = pps_en; + /*di pre h scaling down: sm1 tm2*/ + de_devp->h_sc_down_en = pre_hsc_down_en; switch_vpu_clk_gate_vmod(VPU_VPU_CLKB, VPU_CLK_GATE_ON); if (post_wr_en && post_wr_support) diwr_set_power_control(1); @@ -6615,7 +6642,7 @@ static int di_task_handle(void *data) } } if (is_meson_g12a_cpu() || is_meson_g12b_cpu() - || is_meson_tl1_cpu() || + || is_meson_tl1_cpu() || is_meson_tm2_cpu() || is_meson_sm1_cpu()) { #ifdef CLK_TREE_SUPPORT clk_set_rate(de_devp->vpu_clkb, @@ -7576,7 +7603,7 @@ static void set_di_flag(void) is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || - is_meson_tl1_cpu() || + is_meson_tl1_cpu() || is_meson_tm2_cpu() || is_meson_sm1_cpu()) { mcpre_en = true; mc_mem_alloc = true; @@ -7595,7 +7622,7 @@ static void set_di_flag(void) is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || - is_meson_tl1_cpu() || + is_meson_tl1_cpu() || is_meson_tm2_cpu() || is_meson_sm1_cpu()) { full_422_pack = true; } @@ -7608,7 +7635,7 @@ static void set_di_flag(void) } post_hold_line = (is_meson_g12a_cpu() || is_meson_g12b_cpu() - || is_meson_tl1_cpu() || + || is_meson_tl1_cpu() || is_meson_tm2_cpu() || is_meson_sm1_cpu())?10:17; } else { post_hold_line = 8; /*2019-01-10: from VLSI feijun*/ @@ -7619,7 +7646,7 @@ static void set_di_flag(void) use_2_interlace_buff = 0; di_force_bit_mode = 8; } - if (is_meson_tl1_cpu()) + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) pulldown_enable = true; if (cpu_after_eq(MESON_CPU_MAJOR_ID_G12A)) intr_mode = 3; @@ -7737,6 +7764,8 @@ static int di_probe(struct platform_device *pdev) "nrds-enable", &(di_devp->nrds_enable)); ret = of_property_read_u32(pdev->dev.of_node, "pps-enable", &(di_devp->pps_enable)); + /*di pre h scaling down :sm1 tm2*/ + di_devp->h_sc_down_en = pre_hsc_down_en; if (di_devp->flag_cma >= 1) { #ifdef CONFIG_CMA diff --git a/drivers/amlogic/media/deinterlace/deinterlace.h b/drivers/amlogic/media/deinterlace/deinterlace.h index 333a7ca..9b9ad1f 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace.h +++ b/drivers/amlogic/media/deinterlace/deinterlace.h @@ -247,6 +247,7 @@ struct di_dev_s { unsigned int post_wr_support; unsigned int nrds_enable; unsigned int pps_enable; + u32 h_sc_down_en;/*sm1, tm2 ...*/ /*struct mutex cma_mutex;*/ unsigned int flag_cma; struct page *total_pages; diff --git a/drivers/amlogic/media/deinterlace/deinterlace_dbg.c b/drivers/amlogic/media/deinterlace/deinterlace_dbg.c index 2cec435..2a844dc 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_dbg.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_dbg.c @@ -255,7 +255,7 @@ void dump_di_reg_g12(void) is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || - is_meson_tl1_cpu() || + is_meson_tl1_cpu() || is_meson_tm2_cpu() || is_meson_sm1_cpu()) base_addr = 0xff900000; else diff --git a/drivers/amlogic/media/deinterlace/deinterlace_hw.c b/drivers/amlogic/media/deinterlace/deinterlace_hw.c index 95d9a8c..51baaa9 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_hw.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_hw.c @@ -472,7 +472,8 @@ void di_hw_init(bool pd_enable, bool mc_enable) switch_vpu_clk_gate_vmod(VPU_VPU_CLKB, VPU_CLK_GATE_ON); if (is_meson_txlx_cpu() || is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() - || is_meson_tl1_cpu() || is_meson_sm1_cpu()) + || is_meson_tl1_cpu() || is_meson_sm1_cpu() || + is_meson_tm2_cpu()) di_top_gate_control(true, true); else if (is_meson_gxl_cpu() || is_meson_gxm_cpu() || is_meson_gxlx_cpu()) @@ -486,7 +487,7 @@ void di_hw_init(bool pd_enable, bool mc_enable) is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_sm1_cpu() || - is_meson_tl1_cpu()) { + is_meson_tl1_cpu() || is_meson_tm2_cpu()) { /* vpp fifo max size on txl :128*3=384[0x180] */ /* di fifo max size on txl :96*3=288[0x120] */ fifo_size_vpp = 0x180; @@ -522,7 +523,7 @@ void di_hw_init(bool pd_enable, bool mc_enable) is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_sm1_cpu() || - is_meson_tl1_cpu()) { + is_meson_tl1_cpu() || is_meson_tm2_cpu()) { di_pre_gate_control(true, true); di_post_gate_control(true); } @@ -541,7 +542,7 @@ void di_hw_init(bool pd_enable, bool mc_enable) is_meson_txhd_cpu() || is_meson_g12a_cpu() || is_meson_sm1_cpu() || is_meson_g12b_cpu() || - is_meson_tl1_cpu()) { + is_meson_tl1_cpu() || is_meson_tm2_cpu()) { di_pre_gate_control(false, true); di_post_gate_control(false); di_top_gate_control(false, false); @@ -883,7 +884,7 @@ static enum eAFBC_DEC afbc_get_decnub(void) sel_dec = eAFBC_DEC1; else if (is_meson_g12a_cpu()) sel_dec = eAFBC_DEC1; - else if (is_meson_tl1_cpu()) + else if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) sel_dec = eAFBC_DEC0; return sel_dec; } @@ -905,7 +906,7 @@ bool afbc_is_supported(void) ret = false; else if (is_meson_g12a_cpu()) ret = false; - else if (is_meson_tl1_cpu()) + else if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) ret = true; return ret; @@ -1071,7 +1072,7 @@ u32 enable_afbc_input(struct vframe_s *vf) /* TL1 add bit[13:12]: fmt_mode; 0:yuv444; 1:yuv422; 2:yuv420 * di does not support yuv444, so for fmt yuv444 di will bypass+ */ - if (is_meson_tl1_cpu()) { + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) { if (vf->type & VIDTYPE_VIU_444) r |= (0 << 12); else if (vf->type & VIDTYPE_VIU_422) @@ -1191,13 +1192,13 @@ static void afbcx_sw(bool on) /*g12a*/ /*RDMA_WR(reg_en, 0x1600);*/ RDMA_WR_BITS(VIUB_MISC_CTRL0, 1, 16, 1); /*TL1 add mem control bit */ - if (is_meson_tl1_cpu()) + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 1, 22, 1); } else { RDMA_WR(reg_ctrl, tmp); RDMA_WR(reg_en, 0x1600); RDMA_WR_BITS(VIUB_MISC_CTRL0, 0, 16, 1); - if (is_meson_tl1_cpu()) + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) RDMA_WR_BITS(VD1_AFBCD0_MISC_CTRL, 0, 22, 1); } } diff --git a/drivers/amlogic/media/deinterlace/deinterlace_mtn.c b/drivers/amlogic/media/deinterlace/deinterlace_mtn.c index 6ff0bb6..9f33569 100644 --- a/drivers/amlogic/media/deinterlace/deinterlace_mtn.c +++ b/drivers/amlogic/media/deinterlace/deinterlace_mtn.c @@ -293,7 +293,7 @@ struct combing_status_s *adpative_combing_config(unsigned int width, } void mtn_int_combing_glbmot(void) { - if (is_meson_tl1_cpu()) {/*from VLSI yanling.liu*/ + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) {/*from VLSI yanling.liu*/ combing_glbmot_radprat[0] = 30; } } diff --git a/drivers/amlogic/media/deinterlace/di_pps.c b/drivers/amlogic/media/deinterlace/di_pps.c index 750be01..3025554 100644 --- a/drivers/amlogic/media/deinterlace/di_pps.c +++ b/drivers/amlogic/media/deinterlace/di_pps.c @@ -388,10 +388,12 @@ static void f2v_get_vertical_phase(unsigned int zoom_ratio, vphase->phase = (offset_out - offset_in) >> 2; } } + /* * patch 1: inp scaler 0: di wr scaler + * support: TM2 + * not support: SM1 */ - void di_pps_config(unsigned char path, int src_w, int src_h, int dst_w, int dst_h) { @@ -1325,3 +1327,61 @@ RESTART: } #endif +/* + * di pre h scaling down function + * only have h scaling down + * support: sm1 tm2 ... + * 0x37b0 ~ 0x37b5 + */ +void di_inp_hsc_setting(uint32_t src_w, uint32_t dst_w) +{ + uint32_t i; + uint32_t hsc_en; + uint32_t horz_phase_step; + int *filt_coef0 = di_filt_coef0; + /*int *filt_coef1 = di_filt_coef1;*/ + /*int *filt_coef2 = di_filt_coef2;*/ + + if (src_w == dst_w) { + hsc_en = 0; + } else { + hsc_en = 1; + /*write horz filter coefs*/ + RDMA_WR(DI_VIU_HSC_COEF_IDX, 0x0100); + for (i = 0; i < 33; i++) + RDMA_WR(DI_VIU_HSC_COEF, filt_coef0[i]); /*bicubic*/ + + horz_phase_step = (src_w << 20) / dst_w; + horz_phase_step = (horz_phase_step << 4); + RDMA_WR(DI_VIU_HSC_WIDTHM1, (src_w-1)<<16 | (dst_w-1)); + RDMA_WR(DI_VIU_HSC_PHASE_STEP, horz_phase_step); + RDMA_WR(DI_VIU_HSC_PHASE_CTRL, 0); + } + RDMA_WR(DI_VIU_HSC_CTRL, + (4 << 20) | /* initial receive number*/ + (0 << 12) | /* initial pixel ptr*/ + (1 << 10) | /* repeat first pixel number*/ + (0 << 8) | /* sp422 mode*/ + (4 << 4) | /* horz scaler bank length*/ + (0 << 2) | /* phase0 always en*/ + (0 << 1) | /* nearest_en*/ + (hsc_en<<0)); /* hsc_en*/ +} + +/* + * 0x37b0 ~ 0x37b5 + */ +void dump_hdownscler_reg(unsigned int base_addr) +{ + unsigned int i = 0x374e; + + pr_info("-----dump hdownscler start-----\n"); + for (i = 0x37b0; i < 0x37b5; i++) { + pr_info("[0x%x][0x%x]=0x%x\n", + base_addr + (i << 2), + i, RDMA_RD(i)); + } + pr_info("-----dump hdownscler end-----\n"); +} + + diff --git a/drivers/amlogic/media/deinterlace/di_pps.h b/drivers/amlogic/media/deinterlace/di_pps.h index 9ec789e..a607364 100644 --- a/drivers/amlogic/media/deinterlace/di_pps.h +++ b/drivers/amlogic/media/deinterlace/di_pps.h @@ -54,6 +54,12 @@ enum f2v_vphase_type_e { F2V_TYPE_MAX }; /* frame to video conversion type */ #endif + +enum hdr2_scaler_e { + hdr2_scaler_postdi = 0, + hdr2_scaler_predi = 1, +}; + struct pps_f2v_vphase_s { unsigned char rcv_num; unsigned char rpt_num; @@ -99,4 +105,7 @@ struct pps_frame_par_s { void di_pps_config(unsigned char path, int src_w, int src_h, int dst_w, int dst_h); void dump_pps_reg(unsigned int base_addr); +void di_inp_hsc_setting(uint32_t src_w, uint32_t dst_w); +void dump_hdownscler_reg(unsigned int base_addr); + #endif diff --git a/drivers/amlogic/media/deinterlace/nr_drv.c b/drivers/amlogic/media/deinterlace/nr_drv.c index 61f2ffd..76a1ba2 100644 --- a/drivers/amlogic/media/deinterlace/nr_drv.c +++ b/drivers/amlogic/media/deinterlace/nr_drv.c @@ -280,7 +280,7 @@ static void dnr_config(struct DNR_PARM_s *dnr_parm_p, DI_Wr(DNR_DM_CTRL, Rd(DNR_DM_CTRL)|(1 << 11)); DI_Wr_reg_bits(DNR_CTRL, dnr_en?1:0, 16, 1); /* dm for sd, hd will slower */ - if (is_meson_tl1_cpu()) + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) DI_Wr(DNR_CTRL, 0x1df00 | (0x03 << 18)); //5 line else DI_Wr(DNR_CTRL, 0x1df00); @@ -357,7 +357,7 @@ static void nr2_config(unsigned short width, unsigned short height) { if (is_meson_txlx_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu() || - is_meson_sm1_cpu()) { + is_meson_sm1_cpu() || is_meson_tm2_cpu()) { DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 2, 1); DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 15, 1); DI_Wr_reg_bits(NR4_TOP_CTRL, nr2_en, 17, 1); @@ -407,7 +407,7 @@ void nr_all_config(unsigned short width, unsigned short height, cue_config(nr_param.pcue_parm, field_type); if (is_meson_txlx_cpu() || is_meson_g12a_cpu() || is_meson_g12b_cpu() || is_meson_tl1_cpu() || - is_meson_sm1_cpu()) { + is_meson_sm1_cpu() || is_meson_tm2_cpu()) { linebuffer_config(width); nr4_config(nr_param.pnr4_parm, width, height); } @@ -599,7 +599,7 @@ static void dnr_process(struct DNR_PARM_s *pDnrPrm) #endif int ll, lr; - if (is_meson_tl1_cpu()) { + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) { ll = Rd(DNR_RO_GBS_STAT_LR); lr = Rd(DNR_RO_GBS_STAT_LL); } else { @@ -747,7 +747,7 @@ void adaptive_cue_adjust(unsigned int frame_diff, unsigned int field_diff) struct CUE_PARM_s *pcue_parm = nr_param.pcue_parm; unsigned int mask1, mask2; - if (is_meson_tl1_cpu()) { + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) { /*value from VLSI(yanling.liu) 2018-12-07: */ mask1 = 0x50332; mask2 = 0x00054357; @@ -840,7 +840,7 @@ void nr_process_in_irq(void) dnr_process(&dnr_param); if (is_meson_txlx_cpu() || is_meson_g12a_cpu() || is_meson_g12a_cpu() || is_meson_tl1_cpu() || - is_meson_sm1_cpu()) { + is_meson_sm1_cpu() || is_meson_tm2_cpu()) { noise_meter_process(nr_param.pnr4_parm, nr_param.frame_count); luma_enhancement_process(nr_param.pnr4_parm, nr_param.frame_count); @@ -1077,19 +1077,11 @@ static void nr4_param_init(struct NR4_PARM_s *nr4_parm_p) nr4_parm_p->sw_nr4_sad2gain_lut[14] = 14; nr4_parm_p->sw_nr4_sad2gain_lut[15] = 9; - if (is_meson_tl1_cpu()) { - nr4_parm_p->sw_nr4_noise_thd = 32; - nr4_parm_p->sw_nr4_noise_sel = 0; - nr4_parm_p->sw_nr4_noise_ctrl_dm_en = 0; - nr4_parm_p->sw_nr4_scene_change_thd2 = 80; - nr4_parm_p->sw_dm_scene_change_en = 0; - } else { - nr4_parm_p->sw_nr4_noise_thd = 32; - nr4_parm_p->sw_nr4_noise_sel = 0; - nr4_parm_p->sw_nr4_noise_ctrl_dm_en = 0; - nr4_parm_p->sw_nr4_scene_change_thd2 = 80; - nr4_parm_p->sw_dm_scene_change_en = 0; - } + nr4_parm_p->sw_nr4_noise_thd = 32; + nr4_parm_p->sw_nr4_noise_sel = 0; + nr4_parm_p->sw_nr4_noise_ctrl_dm_en = 0; + nr4_parm_p->sw_nr4_scene_change_thd2 = 80; + nr4_parm_p->sw_dm_scene_change_en = 0; } static void cue_param_init(struct CUE_PARM_s *cue_parm_p) @@ -1200,7 +1192,7 @@ void nr_hw_init(void) { nr_gate_control(true); - if (is_meson_tl1_cpu()) + if (is_meson_tl1_cpu() || is_meson_tm2_cpu()) DI_Wr(DNR_CTRL, 0x1df00|(0x03<<18));//5 line else DI_Wr(DNR_CTRL, 0x1df00); @@ -1217,7 +1209,7 @@ void nr_gate_control(bool gate) { if (!is_meson_txlx_cpu() && !is_meson_g12a_cpu() && !is_meson_g12b_cpu() && !is_meson_sm1_cpu() - && !is_meson_tl1_cpu()) + && !is_meson_tl1_cpu() && !is_meson_tm2_cpu()) return; if (gate) { /* enable nr auto gate */ diff --git a/drivers/amlogic/media/deinterlace/register.h b/drivers/amlogic/media/deinterlace/register.h index 5ce602d..5d8a36a 100644 --- a/drivers/amlogic/media/deinterlace/register.h +++ b/drivers/amlogic/media/deinterlace/register.h @@ -212,6 +212,15 @@ void DI_VSYNC_WR_MPEG_REG_BITS(unsigned int addr, #define DI_HSC_INI_PAT_CTRL 0x376b #define DI_SC_GCLK_CTRL 0x376c #define DI_SC_HOLD_LINE 0x376d + +/* DI H DOWN SCALER */ +#define DI_VIU_HSC_WIDTHM1 0x37b0 +#define DI_VIU_HSC_PHASE_STEP 0x37b1 +#define DI_VIU_HSC_CTRL 0x37b2 +#define DI_VIU_HSC_PHASE_CTRL 0x37b3 +#define DI_VIU_HSC_COEF 0x37b4 +#define DI_VIU_HSC_COEF_IDX 0x37b5 + /* NR DOWNSAMPLE */ #define NRDSWR_X 0x37f9 #define NRDSWR_Y 0x37fa -- 2.7.4