From 6652cc0cf7c0373b8af12f9e5b1a7065577a78da Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 7 Jan 2020 16:24:42 -0500 Subject: [PATCH] AMDGPU/GlobalISel: Fix scalar G_SELECT for arbitrary pointers 4e85ca9562a588eba491e44bcbf73cb2f419780f missed updating the legal condition type set for pointers with any unrecognized address space. --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +- .../AMDGPU/GlobalISel/inst-select-select.mir | 30 +++++++++- .../AMDGPU/GlobalISel/regbankselect-select.mir | 68 ++++++++++++++++++++++ 3 files changed, 98 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index e9ecc8d..0e02170 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -915,7 +915,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_, .clampMaxNumElements(0, PrivatePtr, 2) .scalarize(0) .widenScalarToNextPow2(0) - .legalIf(all(isPointer(0), typeIs(1, S1))); + .legalIf(all(isPointer(0), typeInSet(1, {S1, S32}))); // TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can // be more flexible with the shift amount type. diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir index 0e3e5ba..c162d38 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir @@ -88,7 +88,6 @@ body: | ... -# FIXME: Handle arbitrary address spaces --- name: select_p1_scc legalized: true @@ -119,6 +118,35 @@ body: | ... --- +name: select_p999_scc +legalized: true +regBankSelected: true + +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 + + ; GCN-LABEL: name: select_p999_scc + ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GCN: [[COPY2:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3 + ; GCN: [[COPY3:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5 + ; GCN: S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc + ; GCN: [[COPY4:%[0-9]+]]:sreg_32 = COPY $scc + ; GCN: $scc = COPY [[COPY4]] + ; GCN: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64 = S_CSELECT_B64 [[COPY2]], [[COPY3]], implicit $scc + ; GCN: S_ENDPGM 0, implicit [[S_CSELECT_B64_]] + %0:sgpr(s32) = COPY $sgpr0 + %1:sgpr(s32) = COPY $sgpr1 + %2:sgpr(p999) = COPY $sgpr2_sgpr3 + %3:sgpr(p999) = COPY $sgpr4_sgpr5 + %4:sgpr(s32) = G_ICMP intpred(eq), %0, %1 + %5:sgpr(p999) = G_SELECT %4, %2, %3 + S_ENDPGM 0, implicit %5 + +... + +--- name: select_v4s16_scc legalized: true regBankSelected: true diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir index a613e5c8..de2253d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir @@ -1180,6 +1180,38 @@ body: | ... --- +name: select_p999_scc_ss +legalized: true +body: | + bb.0: + liveins: $sgpr0, $sgpr1, $sgpr2_sgpr3, $sgpr4_sgpr5 + ; FAST-LABEL: name: select_p999_scc_ss + ; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; FAST: [[COPY2:%[0-9]+]]:sgpr(p999) = COPY $sgpr2_sgpr3 + ; FAST: [[COPY3:%[0-9]+]]:sgpr(p999) = COPY $sgpr4_sgpr5 + ; FAST: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) + ; FAST: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) + ; FAST: [[SELECT:%[0-9]+]]:sgpr(p999) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]] + ; GREEDY-LABEL: name: select_p999_scc_ss + ; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 + ; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 + ; GREEDY: [[COPY2:%[0-9]+]]:sgpr(p999) = COPY $sgpr2_sgpr3 + ; GREEDY: [[COPY3:%[0-9]+]]:sgpr(p999) = COPY $sgpr4_sgpr5 + ; GREEDY: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[ICMP]](s32) + ; GREEDY: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1) + ; GREEDY: [[SELECT:%[0-9]+]]:sgpr(p999) = G_SELECT [[ZEXT]](s32), [[COPY2]], [[COPY3]] + %0:_(s32) = COPY $sgpr0 + %1:_(s32) = COPY $sgpr1 + %2:_(p999) = COPY $sgpr2_sgpr3 + %3:_(p999) = COPY $sgpr4_sgpr5 + %4:_(s1) = G_ICMP intpred(ne), %0, %1 + %5:_(p999) = G_SELECT %4, %2, %3 +... + +--- name: select_p1_scc_sv legalized: true body: | @@ -1445,6 +1477,42 @@ body: | ... --- +name: select_p999_vcc_vv +legalized: true +body: | + bb.0: + liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5 + ; FAST-LABEL: name: select_p999_vcc_vv + ; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; FAST: [[COPY2:%[0-9]+]]:vgpr(p999) = COPY $vgpr2_vgpr3 + ; FAST: [[COPY3:%[0-9]+]]:vgpr(p999) = COPY $vgpr4_vgpr5 + ; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; FAST: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p999) + ; FAST: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p999) + ; FAST: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]] + ; FAST: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]] + ; FAST: [[MV:%[0-9]+]]:vgpr(p999) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32) + ; GREEDY-LABEL: name: select_p999_vcc_vv + ; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 + ; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1 + ; GREEDY: [[COPY2:%[0-9]+]]:vgpr(p999) = COPY $vgpr2_vgpr3 + ; GREEDY: [[COPY3:%[0-9]+]]:vgpr(p999) = COPY $vgpr4_vgpr5 + ; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]] + ; GREEDY: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY2]](p999) + ; GREEDY: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY3]](p999) + ; GREEDY: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV]], [[UV2]] + ; GREEDY: [[SELECT1:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[UV1]], [[UV3]] + ; GREEDY: [[MV:%[0-9]+]]:vgpr(p999) = G_MERGE_VALUES [[SELECT]](s32), [[SELECT1]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(p999) = COPY $vgpr2_vgpr3 + %3:_(p999) = COPY $vgpr4_vgpr5 + %4:_(s1) = G_ICMP intpred(ne), %0, %1 + %5:_(p999) = G_SELECT %4, %2, %3 +... + +--- name: select_s32_vgpr_vv legalized: true body: | -- 2.7.4