From 660ca3c276d0a1df7102e0be0af92e5c3455af1a Mon Sep 17 00:00:00 2001 From: "HeungJun, Kim" Date: Mon, 1 Jun 2009 23:00:53 +0900 Subject: [PATCH] [S5PC100] remove s5pc1xx.h & move the definitions to include/asm/arch/cpu.h use include/asm-arm/arch-s5pc100/cpu.h, next time. Signed-off-by: HeungJun, Kim --- board/samsung/tickertape/lowlevel_init.S | 3 +- board/samsung/tickertape/onenand.c | 1 - board/samsung/tickertape/tickertape.c | 1 - cpu/arm_cortexa8/s5pc100/cpu_init.S | 1 - cpu/arm_cortexa8/s5pc100/interrupts.c | 5 +- cpu/arm_cortexa8/s5pc100/speed.c | 1 - drivers/mtd/onenand/s3c-onenand.c | 1 - drivers/serial/serial_s5pc100.c | 2 - include/asm-arm/arch-s5pc100/clock-others.h | 33 ++ include/asm-arm/arch-s5pc100/cpu.h | 372 +++++++++++++++--- include/asm-arm/arch-s5pc100/gpio.h | 580 ++++++++++++++++++++++++++++ include/asm-arm/arch-s5pc100/uart.h | 68 ++++ include/asm-arm/arch-s5pc100/watchdog.h | 16 + include/s5pc1xx.h | 532 ++++++++++++------------- 14 files changed, 1294 insertions(+), 322 deletions(-) create mode 100644 include/asm-arm/arch-s5pc100/clock-others.h create mode 100644 include/asm-arm/arch-s5pc100/gpio.h create mode 100644 include/asm-arm/arch-s5pc100/uart.h create mode 100644 include/asm-arm/arch-s5pc100/watchdog.h diff --git a/board/samsung/tickertape/lowlevel_init.S b/board/samsung/tickertape/lowlevel_init.S index e9635fb..e3c6180 100644 --- a/board/samsung/tickertape/lowlevel_init.S +++ b/board/samsung/tickertape/lowlevel_init.S @@ -33,8 +33,7 @@ #include #include - -#include +#include #ifdef CONFIG_SERIAL0 #define UART_CONSOLE_BASE UARTx_OFFSET(0) diff --git a/board/samsung/tickertape/onenand.c b/board/samsung/tickertape/onenand.c index 70040e4..4d34265 100644 --- a/board/samsung/tickertape/onenand.c +++ b/board/samsung/tickertape/onenand.c @@ -9,7 +9,6 @@ #include -#include #include #include diff --git a/board/samsung/tickertape/tickertape.c b/board/samsung/tickertape/tickertape.c index b0d75cc..8a90c0a 100644 --- a/board/samsung/tickertape/tickertape.c +++ b/board/samsung/tickertape/tickertape.c @@ -29,7 +29,6 @@ */ #include -#include static inline void delay(unsigned long loops) { diff --git a/cpu/arm_cortexa8/s5pc100/cpu_init.S b/cpu/arm_cortexa8/s5pc100/cpu_init.S index 7f7877b..3d1b3b5 100644 --- a/cpu/arm_cortexa8/s5pc100/cpu_init.S +++ b/cpu/arm_cortexa8/s5pc100/cpu_init.S @@ -29,7 +29,6 @@ */ #include -#include .globl mem_ctrl_asm_init mem_ctrl_asm_init: diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c b/cpu/arm_cortexa8/s5pc100/interrupts.c index 445965d..cdd4cd0 100644 --- a/cpu/arm_cortexa8/s5pc100/interrupts.c +++ b/cpu/arm_cortexa8/s5pc100/interrupts.c @@ -44,7 +44,6 @@ */ #include -#include #define PRESCALER_0 (16 - 1) /* prescaler of PWM timer 4 */ #define MUX4_DIV_12 (2 - 1) /* MUX 4, 1/2 period */ @@ -58,14 +57,14 @@ static unsigned long lastdec; /* Last decremneter snapshot */ /* macro to read the 16 bit timer */ static inline ulong READ_TIMER(void) { - s5pc1xx_timers *const timers = (s5pc1xx_timers *)S5P_TIMER_BASE; + s5pc1xx_timers_t *const timers = (s5pc1xx_timers_t *)S5P_TIMER_BASE; return timers->TCNTO4; } int interrupt_init(void) { - s5pc1xx_timers *const timers = (s5pc1xx_timers *)S5P_TIMER_BASE; + s5pc1xx_timers_t *const timers = (s5pc1xx_timers_t *)S5P_TIMER_BASE; /* * @ PWM Timer 4 diff --git a/cpu/arm_cortexa8/s5pc100/speed.c b/cpu/arm_cortexa8/s5pc100/speed.c index 4cac4a1..76b3922 100644 --- a/cpu/arm_cortexa8/s5pc100/speed.c +++ b/cpu/arm_cortexa8/s5pc100/speed.c @@ -36,7 +36,6 @@ */ #include -#include #define APLL 0 #define MPLL 1 diff --git a/drivers/mtd/onenand/s3c-onenand.c b/drivers/mtd/onenand/s3c-onenand.c index e69c0b2..6fdf885 100644 --- a/drivers/mtd/onenand/s3c-onenand.c +++ b/drivers/mtd/onenand/s3c-onenand.c @@ -11,7 +11,6 @@ #include #include #elif defined(CONFIG_S5PC1XX) -#include #include #endif diff --git a/drivers/serial/serial_s5pc100.c b/drivers/serial/serial_s5pc100.c index ee702cf..3b90c5b 100644 --- a/drivers/serial/serial_s5pc100.c +++ b/drivers/serial/serial_s5pc100.c @@ -23,8 +23,6 @@ #include -#include - #ifdef CONFIG_SERIAL0 #define UART_NR S5PC1XX_UART0 #elif defined(CONFIG_SERIAL1) diff --git a/include/asm-arm/arch-s5pc100/clock-others.h b/include/asm-arm/arch-s5pc100/clock-others.h new file mode 100644 index 0000000..35f1686 --- /dev/null +++ b/include/asm-arm/arch-s5pc100/clock-others.h @@ -0,0 +1,33 @@ + +/* + * Clock control - Others + */ +#define S5P_OTHERS_REG_BASE(x) (S5P_PA_CLK_OTHERS + (x)) +#define S5P_OTHERS_BASE S5P_OTHERS_REG_BASE(0x0) +#define S5P_SW_RST S5P_OTHERS_REG_BASE(0x0) +#define S5P_ONENAND_RST S5P_OTHERS_REG_BASE(0x8) +#define S5P_GENERAL_CTRL S5P_OTHERS_REG_BASE(0x100) +#define S5P_GENERAL_STATUS S5P_OTHERS_REG_BASE(0x104) +#define S5P_MEM_SYS_CFG S5P_OTHERS_REG_BASE(0x200) +#define S5P_CAM_MUX_SEL S5P_OTHERS_REG_BASE(0x300) +#define S5P_MIXER_OUT_SEL S5P_OTHERS_REG_BASE(0x304) +#define S5P_LPMP3_MODE_SEL S5P_OTHERS_REG_BASE(0x308) +#define S5P_MIPI_PHY_CON0 S5P_OTHERS_REG_BASE(0x400) +#define S5P_MIPI_PHY_CON1 S5P_OTHERS_REG_BASE(0x414) +#define S5P_HDMI_PHY_CON0 S5P_OTHERS_REG_BASE(0x420) + +#ifndef __ASSEMBLY__ +#define S5P_OTHERS_BASE_REG __REG(S5P_OTHERS_BASE) +#define S5P_SW_RST_REG __REG(S5P_SW_RST) +#define S5P_ONENAND_RST_REG __REG(S5P_ONENAND_RST) +#define S5P_GENERAL_CTRL_REG __REG(S5P_GENERAL_CTRL) +#define S5P_GENERAL_STATUS_REG __REG(S5P_GENERAL_STATUS) +#define S5P_MEM_SYS_CFG_REG __REG(S5P_MEM_SYS_CFG) +#define S5P_CAM_MUX_SEL_REG __REG(S5P_CAM_MUX_SEL) +#define S5P_MIXER_OUT_SEL_REG __REG(S5P_MIXER_OUT_SEL) +#define S5P_LPMP3_MODE_SEL_REG __REG(S5P_LPMP3_MODE_SEL) +#define S5P_MIPI_PHY_CON0_REG __REG(S5P_MIPI_PHY_CON0) +#define S5P_MIPI_PHY_CON1_REG __REG(S5P_MIPI_PHY_CON1) +#define S5P_HDMI_PHY_CON0_REG __REG(S5P_HDMI_PHY_CON0) +#endif /* __ASSENBLY__ */ + diff --git a/include/asm-arm/arch-s5pc100/cpu.h b/include/asm-arm/arch-s5pc100/cpu.h index 91db718..9d3e9a7 100644 --- a/include/asm-arm/arch-s5pc100/cpu.h +++ b/include/asm-arm/arch-s5pc100/cpu.h @@ -24,50 +24,329 @@ #ifndef _CPU_H #define _CPU_H +#include + +#ifndef __S5PC100_H__ +#define __S5PC100_H__ + +#define S5P_ADDR_BASE (0xe0000000) +#define S5P_ADDR(x) (S5P_ADDR_BASE + (x)) + +#define S5P_PA_CLK S5P_ADDR(0x00100000) /* Clock Base */ +#define S5P_PA_PWR S5P_ADDR(0x00108000) /* Power Base */ +#define S5P_PA_CLK_OTHERS S5P_ADDR(0x00200000) /* Clock Others Base */ +#define S5P_PA_GPIO S5P_ADDR(0x00300000) /* GPIO Base */ +#define S5P_PA_VIC0 S5P_ADDR(0x04000000) /* Vector Interrupt Controller 0 */ +#define S5P_PA_VIC1 S5P_ADDR(0x04100000) /* Vector Interrupt Controller 1 */ +#define S5P_PA_VIC2 S5P_ADDR(0x04200000) /* Vector Interrupt Controller 2 */ +#define S5P_PA_DMC S5P_ADDR(0x06000000) /* Dram Memory Controller */ +#define S5P_PA_SROMC S5P_ADDR(0x07000000) /* SROM Controller */ +#define S5P_PA_WATCHDOG S5P_ADDR(0x0a200000) /* Watchdog Timer */ +#define S5P_PA_PWMTIMER S5P_ADDR(0x0a000000) /* PWM Timer */ + +/* + * Chip ID + */ +#define S5P_ID(x) (S5P_PA_ID + (x)) + +#define S5P_PRO_ID S5P_ID(0) +#define S5P_OMR S5P_ID(4) + +/* + * Clock control + */ +#define S5P_CLKREG(x) (S5P_PA_CLK + (x)) + +/* Clock Register */ +#define S5P_APLL_LOCK S5P_CLKREG(0x0) +#define S5P_MPLL_LOCK S5P_CLKREG(0x4) +#define S5P_EPLL_LOCK S5P_CLKREG(0x8) +#define S5P_HPLL_LOCK S5P_CLKREG(0xc) + +#define S5P_APLL_CON S5P_CLKREG(0x100) +#define S5P_MPLL_CON S5P_CLKREG(0x104) +#define S5P_EPLL_CON S5P_CLKREG(0x108) +#define S5P_HPLL_CON S5P_CLKREG(0x10c) + +#define S5P_CLK_SRC0 S5P_CLKREG(0x200) +#define S5P_CLK_SRC1 S5P_CLKREG(0x204) +#define S5P_CLK_SRC2 S5P_CLKREG(0x208) +#define S5P_CLK_SRC3 S5P_CLKREG(0x20c) + +#define S5P_CLK_DIV0 S5P_CLKREG(0x300) +#define S5P_CLK_DIV1 S5P_CLKREG(0x304) +#define S5P_CLK_DIV2 S5P_CLKREG(0x308) +#define S5P_CLK_DIV3 S5P_CLKREG(0x30c) +#define S5P_CLK_DIV4 S5P_CLKREG(0x310) + +#define S5P_CLK_OUT S5P_CLKREG(0x400) + +#define S5P_CLK_GATE_D00 S5P_CLKREG(0x500) +#define S5P_CLK_GATE_D01 S5P_CLKREG(0x504) +#define S5P_CLK_GATE_D02 S5P_CLKREG(0x508) + +#define S5P_CLK_GATE_D10 S5P_CLKREG(0x520) +#define S5P_CLK_GATE_D11 S5P_CLKREG(0x524) +#define S5P_CLK_GATE_D12 S5P_CLKREG(0x528) +#define S5P_CLK_GATE_D13 S5P_CLKREG(0x530) +#define S5P_CLK_GATE_D14 S5P_CLKREG(0x534) + +#define S5P_CLK_GATE_D20 S5P_CLKREG(0x540) + +#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x560) +#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x564) -/* UART (see manual chapter 11) */ #ifndef __ASSEMBLY__ -typedef struct s5pc1xx_uart { - volatile unsigned long ULCON; - volatile unsigned long UCON; - volatile unsigned long UFCON; - volatile unsigned long UMCON; - volatile unsigned long UTRSTAT; - volatile unsigned long UERSTAT; - volatile unsigned long UFSTAT; - volatile unsigned long UMSTAT; -#ifdef __BIG_ENDIAN - volatile unsigned char res1[3]; - volatile unsigned char UTXH; - volatile unsigned char res2[3]; - volatile unsigned char URXH; -#else /* Little Endian */ - volatile unsigned char UTXH; - volatile unsigned char res1[3]; - volatile unsigned char URXH; - volatile unsigned char res2[3]; -#endif - volatile unsigned long UBRDIV; -#ifdef __BIG_ENDIAN - volatile unsigned char res3[2]; - volatile unsigned short UDIVSLOT; -#else - volatile unsigned short UDIVSLOT; - volatile unsigned char res3[2]; -#endif -} s5pc1xx_uart_t; - -enum s5pc1xx_uarts_nr { - S5PC1XX_UART0, - S5PC1XX_UART1, - S5PC1XX_UART2, - S5PC1XX_UART3, -}; -#else -#endif +/* Clock Address */ +#define S5P_APLL_LOCK_REG __REG(S5P_APLL_LOCK) +#define S5P_MPLL_LOCK_REG __REG(S5P_MPLL_LOCK) +#define S5P_EPLL_LOCK_REG __REG(S5P_EPLL_LOCK) +#define S5P_HPLL_LOCK_REG __REG(S5P_HPLL_LOCK) + +#define S5P_APLL_CON_REG __REG(S5P_APLL_CON) +#define S5P_MPLL_CON_REG __REG(S5P_MPLL_CON) +#define S5P_EPLL_CON_REG __REG(S5P_EPLL_CON) +#define S5P_HPLL_CON_REG __REG(S5P_HPLL_CON) + +#define S5P_CLK_SRC0_REG __REG(S5P_CLK_SRC0) +#define S5P_CLK_SRC1_REG __REG(S5P_CLK_SRC1) +#define S5P_CLK_SRC2_REG __REG(S5P_CLK_SRC2) +#define S5P_CLK_SRC3_REG __REG(S5P_CLK_SRC3) + +#define S5P_CLK_DIV0_REG __REG(S5P_CLK_DIV0) +#define S5P_CLK_DIV1_REG __REG(S5P_CLK_DIV1) +#define S5P_CLK_DIV2_REG __REG(S5P_CLK_DIV2) +#define S5P_CLK_DIV3_REG __REG(S5P_CLK_DIV3) +#define S5P_CLK_DIV4_REG __REG(S5P_CLK_DIV4) + +#define S5P_CLK_OUT_REG __REG(S5P_CLK_OUT) + +#define S5P_CLK_GATE_D00_REG __REG(S5P_CLK_GATE_D00) +#define S5P_CLK_GATE_D01_REG __REG(S5P_CLK_GATE_D01) +#define S5P_CLK_GATE_D02_REG __REG(S5P_CLK_GATE_D02) + +#define S5P_CLK_GATE_D10_REG __REG(S5P_CLK_GATE_D10) +#define S5P_CLK_GATE_D11_REG __REG(S5P_CLK_GATE_D11) +#define S5P_CLK_GATE_D12_REG __REG(S5P_CLK_GATE_D12) +#define S5P_CLK_GATE_D13_REG __REG(S5P_CLK_GATE_D13) +#define S5P_CLK_GATE_D14_REG __REG(S5P_CLK_GATE_D14) + +#define S5P_CLK_GATE_D20_REG __REG(S5P_CLK_GATE_D20) + +#define S5P_CLK_GATE_SCLK0_REG __REG(S5P_CLK_GATE_SCLK0) +#define S5P_CLK_GATE_SCLK1_REG __REG(S5P_CLK_GATE_SCLK1) +#endif /* __ASSENBLY__ */ + + +/* + * Power control + */ +#define S5P_PWRREG(x) (S5P_PA_PWR + (x)) + +#define S5P_PWR_CFG S5P_PWRREG(0x0) +#define S5P_EINT_WAKEUP_MASK S5P_PWRREG(0x04) +#define S5P_NORMAL_CFG S5P_PWRREG(0x10) +#define S5P_STOP_CFG S5P_PWRREG(0x14) +#define S5P_SLEEP_CFG S5P_PWRREG(0x18) +#define S5P_STOP_MEM_CFG S5P_PWRREG(0x1c) +#define S5P_OSC_FREQ S5P_PWRREG(0x100) +#define S5P_OSC_STABLE S5P_PWRREG(0x104) +#define S5P_PWR_STABLE S5P_PWRREG(0x108) +#define S5P_INTERNAL_PWR_STABLE S5P_PWRREG(0x110) +#define S5P_CLAMP_STABLE S5P_PWRREG(0x114) +#define S5P_OTHERS S5P_PWRREG(0x200) +#define S5P_RST_STAT S5P_PWRREG(0x300) +#define S5P_WAKEUP_STAT S5P_PWRREG(0x304) +#define S5P_BLK_PWR_STAT S5P_PWRREG(0x308) +#define S5P_INFORM0 S5P_PWRREG(0x400) +#define S5P_INFORM1 S5P_PWRREG(0x404) +#define S5P_INFORM2 S5P_PWRREG(0x408) +#define S5P_INFORM3 S5P_PWRREG(0x40c) +#define S5P_INFORM4 S5P_PWRREG(0x410) +#define S5P_INFORM5 S5P_PWRREG(0x414) +#define S5P_INFORM6 S5P_PWRREG(0x418) +#define S5P_INFORM7 S5P_PWRREG(0x41c) +#define S5P_DCGIDX_MAP0 S5P_PWRREG(0x500) +#define S5P_DCGIDX_MAP1 S5P_PWRREG(0x504) +#define S5P_DCGIDX_MAP2 S5P_PWRREG(0x508) +#define S5P_DCGPERF_MAP0 S5P_PWRREG(0x50c) +#define S5P_DCGPERF_MAP1 S5P_PWRREG(0x510) +#define S5P_DVCIDX_MAP S5P_PWRREG(0x514) +#define S5P_FREQ_CPU S5P_PWRREG(0x518) +#define S5P_FREQ_DPM S5P_PWRREG(0x51c) +#define S5P_DVSEMCLK_EN S5P_PWRREG(0x520) +#define S5P_APLL_CON_L8 S5P_PWRREG(0x600) +#define S5P_APLL_CON_L7 S5P_PWRREG(0x604) +#define S5P_APLL_CON_L6 S5P_PWRREG(0x608) +#define S5P_APLL_CON_L5 S5P_PWRREG(0x60c) +#define S5P_APLL_CON_L4 S5P_PWRREG(0x610) +#define S5P_APLL_CON_L3 S5P_PWRREG(0x614) +#define S5P_APLL_CON_L2 S5P_PWRREG(0x618) +#define S5P_APLL_CON_L1 S5P_PWRREG(0x61c) +#define S5P_EM_CONTROL S5P_PWRREG(0x620) + +#define S5P_CLKDIV_IEM_L8 S5P_PWRREG(0x700) +#define S5P_CLKDIV_IEM_L7 S5P_PWRREG(0x704) +#define S5P_CLKDIV_IEM_L6 S5P_PWRREG(0x708) +#define S5P_CLKDIV_IEM_L5 S5P_PWRREG(0x70c) +#define S5P_CLKDIV_IEM_L4 S5P_PWRREG(0x710) +#define S5P_CLKDIV_IEM_L3 S5P_PWRREG(0x714) +#define S5P_CLKDIV_IEM_L2 S5P_PWRREG(0x718) +#define S5P_CLKDIV_IEM_L1 S5P_PWRREG(0x71c) + +#define S5P_IEM_HPMCLK_DIV S5P_PWRREG(0x724) + + +/* + * Vector Interrupt Controller + * : VIC0, VIC1, VIC2 + */ +/* VIC0 */ +#define S5P_VIC0_BASE(x) (S5P_PA_VIC0 + (x)) +#define S5P_VIC1_BASE(x) (S5P_PA_VIC1 + (x)) +#define S5P_VIC2_BASE(x) (S5P_PA_VIC2 + (x)) + +/* Vector Interrupt Offset */ +#define VIC_IRQSTATUS_OFFSET 0x0 /* IRQ Status Register */ +#define VIC_FIQSTATUS_OFFSET 0x4 /* FIQ Status Register */ +#define VIC_RAWINTR_OFFSET 0x8 /* Raw Interrupt Status Register */ +#define VIC_INTSELECT_OFFSET 0xc /* Interrupt Select Register */ +#define VIC_INTENABLE_OFFSET 0x10 /* Interrupt Enable Register */ +#define VIC_INTENCLEAR_OFFSET 0x14 /* Interrupt Enable Clear Register */ +#define VIC_SOFTINT_OFFSET 0x18 /* Software Interrupt Register */ +#define VIC_SOFTINTCLEAR_OFFSET 0x1c /* Software Interrupt Clear Register */ +#define VIC_PROTECTION_OFFSET 0x20 /* Protection Enable Register */ +#define VIC_SWPRIORITYMASK_OFFSET 0x24 /* Software Priority Mask Register */ +#define VIC_PRIORITYDAISY_OFFSET 0x28 /* Vector Priority Register for Daisy Chain */ +#define VIC_INTADDRESS_OFFSET 0xf00 /* Vector Priority Register for Daisy Chain */ + + +/* + * SROMC Controller + */ +/* DRAM Memory Controller */ +#define S5P_DMC_BASE(x) (S5P_PA_DMC + (x)) +/* SROMC Base */ +#define S5P_SROMC_BASE(x) (S5P_PA_SROMC + (x)) +/* SROMC offset */ +#define CONCONTROL_OFFSET 0x0 /* Controller Control Register */ +#define MEMCONTROL_OFFSET 0x04 /* Memory Control Register */ +#define MEMCONFIG0_OFFSET 0x08 /* Memory Chip0 Configuration Register */ +#define MEMCONFIG1_OFFSET 0x0c /* Memory Chip1 Configuration Register */ +#define DIRECTCMD_OFFSET 0x10 /* Memory Direct Command Register */ +#define PRECHCONFIG_OFFSET 0x14 /* Precharge Policy Configuration Register */ +#define PHYCONTROL0_OFFSET 0x18 /* PHY Control0 Register */ +#define PHYCONTROL1_OFFSET 0x1c /* PHY Control1 Register */ +#define PHYCONTROL2_OFFSET 0x20 /* PHY Control2 Register */ +#define PWRDNCONFIG_OFFSET 0x28 /* Dynamic Power Down Configuration Register */ +#define TIMINGAREF_OFFSET 0x30 /* AC Timing Register for SDRAM Auto Refresh */ +#define TIMINGROW_OFFSET 0x34 /* AC Timing Register for SDRAM Row */ +#define TIMINGDATA_OFFSET 0x38 /* AC Timing Register for SDRAM Data */ +#define TIMINGPOWER_OFFSET 0x3c /* AC Timing Register for Power Mode of SDRAM */ +#define PHYSTATUS0_OFFSET 0x40 /* PHY Status Register 0 */ +#define PHYSTATUS1_OFFSET 0x44 /* PHY Status Register 1 */ +#define CHIP0STATUS_OFFSET 0x48 /* Memory Chip0 Status Register */ +#define CHIP1STATUS_OFFSET 0x4c /* Memory Chip1 Status Register */ +#define AREFSTATUS_OFFSET 0x50 /* Counter status Register for Auto Refresh */ +#define MRSTATUS_OFFSET 0x54 /* Memory Mode Registers Status Register */ +#define PHYTEST0_OFFSET 0x58 /* PHY Test Register 0 */ +#define PHYTEST1_OFFSET 0x5c /* PHY Test Register 1 */ + +#define S5P_CONCONTROL S5P_DMC_BASE(CONCONTROL_OFFSET) +#define S5P_MEMCONTROL S5P_DMC_BASE(MEMCONTROL_OFFSET) +#define S5P_MEMCONFIG0 S5P_DMC_BASE(MEMCONFIG0_OFFSET) +#define S5P_MEMCONFIG1 S5P_DMC_BASE(MEMCONFIG1_OFFSET) +#define S5P_DIRECTCMD S5P_DMC_BASE(DIRECTCMD_OFFSET) +#define S5P_PRECHCONFIG S5P_DMC_BASE(PRECHCONFIG_OFFSET) +#define S5P_PHYCONTROL0 S5P_DMC_BASE(PHYCONTROL0_OFFSET) +#define S5P_PHYCONTROL1 S5P_DMC_BASE(PHYCONTROL1_OFFSET) +#define S5P_PHYCONTROL2 S5P_DMC_BASE(PHYCONTROL2_OFFSET) +#define S5P_PWRDNCONFIG S5P_DMC_BASE(PWRDNCONFIG_OFFSET) +#define S5P_TIMINGAREF S5P_DMC_BASE(TIMINGAREF_OFFSET) +#define S5P_TIMINGROW S5P_DMC_BASE(TIMINGROW_OFFSET) +#define S5P_TIMINGDATA S5P_DMC_BASE(TIMINGDATA_OFFSET) +#define S5P_TIMINGPOWER S5P_DMC_BASE(TIMINGPOWER_OFFSET) +#define S5P_PHYSTATUS0 S5P_DMC_BASE(PHYSTATUS0_OFFSET) +#define S5P_PHYSTATUS1 S5P_DMC_BASE(PHYSTATUS1_OFFSET) +#define S5P_CHIP0STATUS S5P_DMC_BASE(CHIP0STATUS_OFFSET) +#define S5P_CHIP1STATUS S5P_DMC_BASE(CHIP1STATUS_OFFSET) +#define S5P_AREFSTATUS S5P_DMC_BASE(AREFSTATUS_OFFSET) +#define S5P_MRSTATUS S5P_DMC_BASE(MRSTATUS_OFFSET) +#define S5P_PHYTEST0 S5P_DMC_BASE(PHYTEST0_OFFSET) +#define S5P_PHYTEST1 S5P_DMC_BASE(PHYTEST1_OFFSET) + + +/* + * PWM Timer + */ +#define S5P_PWMTIMER_BASE(x) (S5P_PA_PWMTIMER + (x)) + +/* PWM timer offset */ +#define PWM_TCFG0_OFFSET 0x0 +#define PWM_TCFG1_OFFSET 0x04 +#define PWM_TCON_OFFSET 0x08 +#define PWM_TCNTB0_OFFSET 0x0c +#define PWM_TCMPB0_OFFSET 0x10 +#define PWM_TCNTO0_OFFSET 0x14 +#define PWM_TCNTB1_OFFSET 0x18 +#define PWM_TCMPB1_OFFSET 0x1c +#define PWM_TCNTO1_OFFSET 0x20 +#define PWM_TCNTB2_OFFSET 0x24 +#define PWM_TCMPB2_OFFSET 0x28 +#define PWM_TCNTO2_OFFSET 0x2c +#define PWM_TCNTB3_OFFSET 0x30 +#define PWM_TCNTO3_OFFSET 0x38 +#define PWM_TCNTB4_OFFSET 0x3c +#define PWM_TCNTO4_OFFSET 0x40 +#define PWM_TINT_CSTAT_OFFSET 0x44 + +/* PWM timer register */ +#define S5P_PWM_TCFG0 S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET) +#define S5P_PWM_TCFG1 S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET) +#define S5P_PWM_TCON S5P_PWMTIMER_BASE(PWM_TCON_OFFSET) +#define S5P_PWM_TCNTB0 S5P_PWMTIMER_BASE(PWM_TCNTB0_OFFSET) +#define S5P_PWM_TCMPB0 S5P_PWMTIMER_BASE(PWM_TCMPB0_OFFSET) +#define S5P_PWM_TCNTO0 S5P_PWMTIMER_BASE(PWM_TCNTO0_OFFSET) +#define S5P_PWM_TCNTB1 S5P_PWMTIMER_BASE(PWM_TCNTB1_OFFSET) +#define S5P_PWM_TCMPB1 S5P_PWMTIMER_BASE(PWM_TCMPB1_OFFSET) +#define S5P_PWM_TCNTO1 S5P_PWMTIMER_BASE(PWM_TCNTO1_OFFSET) +#define S5P_PWM_TCNTB2 S5P_PWMTIMER_BASE(PWM_TCNTB2_OFFSET) +#define S5P_PWM_TCMPB2 S5P_PWMTIMER_BASE(PWM_TCMPB2_OFFSET) +#define S5P_PWM_TCNTO2 S5P_PWMTIMER_BASE(PWM_TCNTO2_OFFSET) +#define S5P_PWM_TCNTB3 S5P_PWMTIMER_BASE(PWM_TCNTB3_OFFSET) +#define S5P_PWM_TCNTO3 S5P_PWMTIMER_BASE(PWM_TCNTO3_OFFSET) +#define S5P_PWM_TCNTB4 S5P_PWMTIMER_BASE(PWM_TCNTB4_OFFSET) +#define S5P_PWM_TCNTO4 S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET) +#define S5P_PWM_TINT_CSTAT S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET) + +/* PWM timer addressing */ +#define S5P_TIMER_BASE S5P_PWMTIMER_BASE(0x0) +#define S5P_PWMTIMER_BASE_REG __REG(S5P_PWMTIMER_BASE(0x0)) +#define S5P_PWM_TCFG0_REG __REG(S5P_PWM_TCFG0) +#define S5P_PWM_TCFG1_REG __REG(S5P_PWM_TCFG1) +#define S5P_PWM_TCON_REG __REG(S5P_PWM_TCON) +#define S5P_PWM_TCNTB0_REG __REG(S5P_PWM_TCNTB0) +#define S5P_PWM_TCMPB0_REG __REG(S5P_PWM_TCMPB0) +#define S5P_PWM_TCNTO0_REG __REG(S5P_PWM_TCNTO0) +#define S5P_PWM_TCNTB1_REG __REG(S5P_PWM_TCNTB1) +#define S5P_PWM_TCMPB1_REG __REG(S5P_PWM_TCMPB1) +#define S5P_PWM_TCNTO1_REG __REG(S5P_PWM_TCNTO1) +#define S5P_PWM_TCNTB2_REG __REG(S5P_PWM_TCNTB2) +#define S5P_PWM_TCMPB2_REG __REG(S5P_PWM_TCMPB2) +#define S5P_PWM_TCNTO2_REG __REG(S5P_PWM_TCNTO2) +#define S5P_PWM_TCNTB3_REG __REG(S5P_PWM_TCNTB3) +#define S5P_PWM_TCNTO3_REG __REG(S5P_PWM_TCNTO3) +#define S5P_PWM_TCNTB4_REG __REG(S5P_PWM_TCNTB4) +#define S5P_PWM_TCNTO4_REG __REG(S5P_PWM_TCNTO4) +#define S5P_PWM_TINT_CSTAT_REG __REG(S5P_PWM_TINT_CSTAT) + +/* PWM timer value */ +#define S5P_TCON4_AUTO_RELOAD (1 << 22) /* Interval mode(Auto Reload) of PWM Timer 4 */ +#define S5P_TCON4_UPDATE (1 << 21) /* Update TCNTB4 */ +#define S5P_TCON4_ON (1 << 20) /* start bit of PWM Timer 4 */ #ifndef __ASSEMBLY__ -typedef struct s5pc1x0_timer { +typedef struct s5pc1xx_timer { volatile unsigned long TCFG0; volatile unsigned long TCFG1; volatile unsigned long TCON; @@ -87,9 +366,14 @@ typedef struct s5pc1x0_timer { volatile unsigned long TCNTO4; volatile unsigned long TINTCSTAT; -} s5pc1xx_timers; -#else -#endif +} s5pc1xx_timers_t; +#endif /* __ASSEMBLY__ */ + +#include +#include +#include +#include +#endif /* __S5PC100_H__ */ -#endif /* _CPU_H */ +#endif /* _CPU_H */ diff --git a/include/asm-arm/arch-s5pc100/gpio.h b/include/asm-arm/arch-s5pc100/gpio.h new file mode 100644 index 0000000..a8f032a --- /dev/null +++ b/include/asm-arm/arch-s5pc100/gpio.h @@ -0,0 +1,580 @@ +/* + * (C) Copyright 2009 SAMSUNG Electronics + * Heungjun Kim + * Minkyu Kang + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * GPIO + */ + +/* GPIO Bank Base */ +#define S5P_GPIO_BASE(x) (S5P_PA_GPIO + (x)) + +#define S5P_GPIO_A_REG(x) (S5P_GPIO_BASE(0x0) + (x)) +#define S5P_GPIO_B_REG(x) (S5P_GPIO_BASE(0x40) + (x)) +#define S5P_GPIO_C_REG(x) (S5P_GPIO_BASE(0x60) + (x)) +#define S5P_GPIO_D_REG(x) (S5P_GPIO_BASE(0x80) + (x)) +#define S5P_GPIO_E_REG(x) (S5P_GPIO_BASE(0xa0) + (x)) +#define S5P_GPIO_F_REG(x) (S5P_GPIO_BASE(0xe0) + (x)) +#define S5P_GPIO_G_REG(x) (S5P_GPIO_BASE(0x160) + (x)) +#define S5P_GPIO_I_REG(x) (S5P_GPIO_BASE(0x1e0) + (x)) +#define S5P_GPIO_J_REG(x) (S5P_GPIO_BASE(0x200) + (x)) +#define S5P_GPIO_K_REG(x) (S5P_GPIO_BASE(0x2a0) + (x)) +#define S5P_GPIO_L_REG(x) (S5P_GPIO_BASE(0x320) + (x)) + +#define S5P_MP_REG(x) (S5P_GPIO_BASE(0x3c0) + (x)) +#define S5P_ETC_REG(x) (S5P_GPIO_BASE(0x4e0) + (x)) + +#define S5P_GPIO_INT_CON_REG(x) (S5P_GPIO_BASE(0x700) + (x)) +#define S5P_GPIO_INT_FLTCON_REG(x) (S5P_GPIO_BASE(0x800) + (x)) +#define S5P_GPIO_INT_MASK_REG(x) (S5P_GPIO_BASE(0x900) + (x)) +#define S5P_GPIO_INT_PEND_REG(x) (S5P_GPIO_BASE(0xa00) + (x)) +#define S5P_GPIO_INT_PRIO_REG(x) (S5P_GPIO_BASE(0xb00) + (x)) + +#define S5P_GPIO_H_REG(x) (S5P_GPIO_BASE(0xc00) + (x)) + +#define S5P_WAKEUP_INT_CON(x) (S5P_GPIO_BASE(0xe00) + (x)) +#define S5P_WAKEUP_FLTINT_CON(x) (S5P_GPIO_BASE(0xe80) + (x)) +#define S5P_WAKEUP_INT_MASK(x) (S5P_GPIO_BASE(0xf00) + (x)) +#define S5P_WAKEUP_INT_PEND(x) (S5P_GPIO_BASE(0xf40) + (x)) + + +/* GPIO Offset */ +#define CON_OFFSET 0x0 +#define DAT_OFFSET 0x4 +#define PULL_OFFSET 0x8 +#define DRV_OFFSET 0xc +#define PDNCON_OFFSET 0x10 +#define PDNPULL_OFFSET 0x14 + + +/* GPIO A Bank Base */ +#define S5P_GPIO_A0_BASE(x) (S5P_GPIO_A_REG(0x0) + (x)) +#define S5P_GPIO_A1_BASE(x) (S5P_GPIO_A_REG(0x20) + (x)) + +#define S5P_GPIO_A0_CON S5P_GPIO_A0_BASE(CON_OFFSET) +#define S5P_GPIO_A0_DAT S5P_GPIO_A0_BASE(DAT_OFFSET) +#define S5P_GPIO_A0_PULL S5P_GPIO_A0_BASE(PULL_OFFSET) +#define S5P_GPIO_A0_DRV S5P_GPIO_A0_BASE(DRV_OFFSET) +#define S5P_GPIO_A0_PDNCON S5P_GPIO_A0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_A0_PDNPUL S5P_GPIO_A0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_A1_CON S5P_GPIO_A1_BASE(CON_OFFSET) +#define S5P_GPIO_A1_DAT S5P_GPIO_A1_BASE(DAT_OFFSET) +#define S5P_GPIO_A1_PULL S5P_GPIO_A1_BASE(PULL_OFFSET) +#define S5P_GPIO_A1_DRV S5P_GPIO_A1_BASE(DRV_OFFSET) +#define S5P_GPIO_A1_PDNCON S5P_GPIO_A1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_A1_PDNPUL S5P_GPIO_A1_BASE(PDNPULL_OFFSET) + +/* GPIO B Bank Base */ +#define S5P_GPIO_B_BASE(x) (S5P_GPIO_B_REG(0x0) + (x)) + +#define S5P_GPIO_B_CON S5P_GPIO_B_BASE(CON_OFFSET) +#define S5P_GPIO_B_DAT S5P_GPIO_B_BASE(DAT_OFFSET) +#define S5P_GPIO_B_PULL S5P_GPIO_B_BASE(PULL_OFFSET) +#define S5P_GPIO_B_DRV S5P_GPIO_B_BASE(DRV_OFFSET) +#define S5P_GPIO_B_PDNCON S5P_GPIO_B_BASE(PDNCON_OFFSET) +#define S5P_GPIO_B_PDNPUL S5P_GPIO_B_BASE(PDNPULL_OFFSET) + +/* GPIO C Bank Base */ +#define S5P_GPIO_C_BASE(x) (S5P_GPIO_C_REG(0x0) + (x)) + +#define S5P_GPIO_C_CON S5P_GPIO_C_BASE(CON_OFFSET) +#define S5P_GPIO_C_DAT S5P_GPIO_C_BASE(DAT_OFFSET) +#define S5P_GPIO_C_PULL S5P_GPIO_C_BASE(PULL_OFFSET) +#define S5P_GPIO_C_DRV S5P_GPIO_C_BASE(DRV_OFFSET) +#define S5P_GPIO_C_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET) +#define S5P_GPIO_C_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET) + +/* GPIO D Bank Base */ +#define S5P_GPIO_D_BASE(x) (S5P_GPIO_C_REG(0x0) + (x)) + +#define S5P_GPIO_D_CON S5P_GPIO_C_BASE(CON_OFFSET) +#define S5P_GPIO_D_DAT S5P_GPIO_C_BASE(DAT_OFFSET) +#define S5P_GPIO_D_PULL S5P_GPIO_C_BASE(PULL_OFFSET) +#define S5P_GPIO_D_DRV S5P_GPIO_C_BASE(DRV_OFFSET) +#define S5P_GPIO_D_PDNCON S5P_GPIO_C_BASE(PDNCON_OFFSET) +#define S5P_GPIO_D_PDNPUL S5P_GPIO_C_BASE(PDNPULL_OFFSET) + +/* GPIO E Bank Base */ +#define S5P_GPIO_E0_BASE(x) (S5P_GPIO_E_REG(0x0) + (x)) +#define S5P_GPIO_E1_BASE(x) (S5P_GPIO_E_REG(0x20) + (x)) + +#define S5P_GPIO_E0_CON S5P_GPIO_E0_BASE(CON_OFFSET) +#define S5P_GPIO_E0_DAT S5P_GPIO_E0_BASE(DAT_OFFSET) +#define S5P_GPIO_E0_PULL S5P_GPIO_E0_BASE(PULL_OFFSET) +#define S5P_GPIO_E0_DRV S5P_GPIO_E0_BASE(DRV_OFFSET) +#define S5P_GPIO_E0_PDNCON S5P_GPIO_E0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_E0_PDNPUL S5P_GPIO_E0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_E1_CON S5P_GPIO_E1_BASE(CON_OFFSET) +#define S5P_GPIO_E1_DAT S5P_GPIO_E1_BASE(DAT_OFFSET) +#define S5P_GPIO_E1_PULL S5P_GPIO_E1_BASE(PULL_OFFSET) +#define S5P_GPIO_E1_DRV S5P_GPIO_E1_BASE(DRV_OFFSET) +#define S5P_GPIO_E1_PDNCON S5P_GPIO_E1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_E1_PDNPUL S5P_GPIO_E1_BASE(PDNPULL_OFFSET) + +/* GPIO F Bank Base */ +#define S5P_GPIO_F0_BASE(x) (S5P_GPIO_F_REG(0x0) + (x)) +#define S5P_GPIO_F1_BASE(x) (S5P_GPIO_F_REG(0x20) + (x)) +#define S5P_GPIO_F2_BASE(x) (S5P_GPIO_F_REG(0x40) + (x)) +#define S5P_GPIO_F3_BASE(x) (S5P_GPIO_F_REG(0x60) + (x)) + +#define S5P_GPIO_F0_CON S5P_GPIO_F0_BASE(CON_OFFSET) +#define S5P_GPIO_F0_DAT S5P_GPIO_F0_BASE(DAT_OFFSET) +#define S5P_GPIO_F0_PULL S5P_GPIO_F0_BASE(PULL_OFFSET) +#define S5P_GPIO_F0_DRV S5P_GPIO_F0_BASE(DRV_OFFSET) +#define S5P_GPIO_F0_PDNCON S5P_GPIO_F0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F0_PDNPUL S5P_GPIO_F0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_F1_CON S5P_GPIO_F1_BASE(CON_OFFSET) +#define S5P_GPIO_F1_DAT S5P_GPIO_F1_BASE(DAT_OFFSET) +#define S5P_GPIO_F1_PULL S5P_GPIO_F1_BASE(PULL_OFFSET) +#define S5P_GPIO_F1_DRV S5P_GPIO_F1_BASE(DRV_OFFSET) +#define S5P_GPIO_F1_PDNCON S5P_GPIO_F1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F1_PDNPUL S5P_GPIO_F1_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_F2_CON S5P_GPIO_F2_BASE(CON_OFFSET) +#define S5P_GPIO_F2_DAT S5P_GPIO_F2_BASE(DAT_OFFSET) +#define S5P_GPIO_F2_PULL S5P_GPIO_F2_BASE(PULL_OFFSET) +#define S5P_GPIO_F2_DRV S5P_GPIO_F2_BASE(DRV_OFFSET) +#define S5P_GPIO_F2_PDNCON S5P_GPIO_F2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F2_PDNPUL S5P_GPIO_F2_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_F3_CON S5P_GPIO_F3_BASE(CON_OFFSET) +#define S5P_GPIO_F3_DAT S5P_GPIO_F3_BASE(DAT_OFFSET) +#define S5P_GPIO_F3_PULL S5P_GPIO_F3_BASE(PULL_OFFSET) +#define S5P_GPIO_F3_DRV S5P_GPIO_F3_BASE(DRV_OFFSET) +#define S5P_GPIO_F3_PDNCON S5P_GPIO_F3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_F3_PDNPUL S5P_GPIO_F3_BASE(PDNPULL_OFFSET) + +/* GPIO G Bank Base */ +#define S5P_GPIO_G0_BASE(x) (S5P_GPIO_G_REG(0x0) + (x)) +#define S5P_GPIO_G1_BASE(x) (S5P_GPIO_G_REG(0x20) + (x)) +#define S5P_GPIO_G2_BASE(x) (S5P_GPIO_G_REG(0x40) + (x)) +#define S5P_GPIO_G3_BASE(x) (S5P_GPIO_G_REG(0x60) + (x)) + +#define S5P_GPIO_G0_CON S5P_GPIO_G0_BASE(CON_OFFSET) +#define S5P_GPIO_G0_DAT S5P_GPIO_G0_BASE(DAT_OFFSET) +#define S5P_GPIO_G0_PULL S5P_GPIO_G0_BASE(PULL_OFFSET) +#define S5P_GPIO_G0_DRV S5P_GPIO_G0_BASE(DRV_OFFSET) +#define S5P_GPIO_G0_PDNCON S5P_GPIO_G0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G0_PDNPUL S5P_GPIO_G0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_G1_CON S5P_GPIO_G1_BASE(CON_OFFSET) +#define S5P_GPIO_G1_DAT S5P_GPIO_G1_BASE(DAT_OFFSET) +#define S5P_GPIO_G1_PULL S5P_GPIO_G1_BASE(PULL_OFFSET) +#define S5P_GPIO_G1_DRV S5P_GPIO_G1_BASE(DRV_OFFSET) +#define S5P_GPIO_G1_PDNCON S5P_GPIO_G1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G1_PDNPUL S5P_GPIO_G1_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_G2_CON S5P_GPIO_G2_BASE(CON_OFFSET) +#define S5P_GPIO_G2_DAT S5P_GPIO_G2_BASE(DAT_OFFSET) +#define S5P_GPIO_G2_PULL S5P_GPIO_G2_BASE(PULL_OFFSET) +#define S5P_GPIO_G2_DRV S5P_GPIO_G2_BASE(DRV_OFFSET) +#define S5P_GPIO_G2_PDNCON S5P_GPIO_G2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G2_PDNPUL S5P_GPIO_G2_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_G3_CON S5P_GPIO_G3_BASE(CON_OFFSET) +#define S5P_GPIO_G3_DAT S5P_GPIO_G3_BASE(DAT_OFFSET) +#define S5P_GPIO_G3_PULL S5P_GPIO_G3_BASE(PULL_OFFSET) +#define S5P_GPIO_G3_DRV S5P_GPIO_G3_BASE(DRV_OFFSET) +#define S5P_GPIO_G3_PDNCON S5P_GPIO_G3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_G3_PDNPUL S5P_GPIO_G3_BASE(PDNPULL_OFFSET) + +/* GPIO I Bank Base */ +#define S5P_GPIO_I_BASE(x) (S5P_GPIO_I_REG(0x0) + (x)) + +#define S5P_GPIO_I_CON S5P_GPIO_I_BASE(CON_OFFSET) +#define S5P_GPIO_I_DAT S5P_GPIO_I_BASE(DAT_OFFSET) +#define S5P_GPIO_I_PULL S5P_GPIO_I_BASE(PULL_OFFSET) +#define S5P_GPIO_I_DRV S5P_GPIO_I_BASE(DRV_OFFSET) +#define S5P_GPIO_I_PDNCON S5P_GPIO_I_BASE(PDNCON_OFFSET) +#define S5P_GPIO_I_PDNPUL S5P_GPIO_I_BASE(PDNPULL_OFFSET) + +/* GPIO J Bank Base */ +#define S5P_GPIO_J0_BASE(x) (S5P_GPIO_J_REG(0x0) + (x)) +#define S5P_GPIO_J1_BASE(x) (S5P_GPIO_J_REG(0x20) + (x)) +#define S5P_GPIO_J2_BASE(x) (S5P_GPIO_J_REG(0x40) + (x)) +#define S5P_GPIO_J3_BASE(x) (S5P_GPIO_J_REG(0x60) + (x)) +#define S5P_GPIO_J4_BASE(x) (S5P_GPIO_J_REG(0x80) + (x)) + +#define S5P_GPIO_J0_CON S5P_GPIO_J0_BASE(CON_OFFSET) +#define S5P_GPIO_J0_DAT S5P_GPIO_J0_BASE(DAT_OFFSET) +#define S5P_GPIO_J0_PULL S5P_GPIO_J0_BASE(PULL_OFFSET) +#define S5P_GPIO_J0_DRV S5P_GPIO_J0_BASE(DRV_OFFSET) +#define S5P_GPIO_J0_PDNCON S5P_GPIO_J0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J0_PDNPUL S5P_GPIO_J0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_J1_CON S5P_GPIO_J1_BASE(CON_OFFSET) +#define S5P_GPIO_J1_DAT S5P_GPIO_J1_BASE(DAT_OFFSET) +#define S5P_GPIO_J1_PULL S5P_GPIO_J1_BASE(PULL_OFFSET) +#define S5P_GPIO_J1_DRV S5P_GPIO_J1_BASE(DRV_OFFSET) +#define S5P_GPIO_J1_PDNCON S5P_GPIO_J1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J1_PDNPUL S5P_GPIO_J1_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_J2_CON S5P_GPIO_J2_BASE(CON_OFFSET) +#define S5P_GPIO_J2_DAT S5P_GPIO_J2_BASE(DAT_OFFSET) +#define S5P_GPIO_J2_PULL S5P_GPIO_J2_BASE(PULL_OFFSET) +#define S5P_GPIO_J2_DRV S5P_GPIO_J2_BASE(DRV_OFFSET) +#define S5P_GPIO_J2_PDNCON S5P_GPIO_J2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J2_PDNPUL S5P_GPIO_J2_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_J3_CON S5P_GPIO_J3_BASE(CON_OFFSET) +#define S5P_GPIO_J3_DAT S5P_GPIO_J3_BASE(DAT_OFFSET) +#define S5P_GPIO_J3_PULL S5P_GPIO_J3_BASE(PULL_OFFSET) +#define S5P_GPIO_J3_DRV S5P_GPIO_J3_BASE(DRV_OFFSET) +#define S5P_GPIO_J3_PDNCON S5P_GPIO_J3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J3_PDNPUL S5P_GPIO_J3_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_J4_CON S5P_GPIO_J4_BASE(CON_OFFSET) +#define S5P_GPIO_J4_DAT S5P_GPIO_J4_BASE(DAT_OFFSET) +#define S5P_GPIO_J4_PULL S5P_GPIO_J4_BASE(PULL_OFFSET) +#define S5P_GPIO_J4_DRV S5P_GPIO_J4_BASE(DRV_OFFSET) +#define S5P_GPIO_J4_PDNCON S5P_GPIO_J4_BASE(PDNCON_OFFSET) +#define S5P_GPIO_J4_PDNPUL S5P_GPIO_J4_BASE(PDNPULL_OFFSET) + +/* GPIO K Bank Base */ +#define S5P_GPIO_K0_BASE(x) (S5P_GPIO_K_REG(0x0) + (x)) +#define S5P_GPIO_K1_BASE(x) (S5P_GPIO_K_REG(0x20) + (x)) +#define S5P_GPIO_K2_BASE(x) (S5P_GPIO_K_REG(0x40) + (x)) +#define S5P_GPIO_K3_BASE(x) (S5P_GPIO_K_REG(0x60) + (x)) + +#define S5P_GPIO_K0_CON S5P_GPIO_K0_BASE(CON_OFFSET) +#define S5P_GPIO_K0_DAT S5P_GPIO_K0_BASE(DAT_OFFSET) +#define S5P_GPIO_K0_PULL S5P_GPIO_K0_BASE(PULL_OFFSET) +#define S5P_GPIO_K0_DRV S5P_GPIO_K0_BASE(DRV_OFFSET) +#define S5P_GPIO_K0_PDNCON S5P_GPIO_K0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K0_PDNPUL S5P_GPIO_K0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_K1_CON S5P_GPIO_K1_BASE(CON_OFFSET) +#define S5P_GPIO_K1_DAT S5P_GPIO_K1_BASE(DAT_OFFSET) +#define S5P_GPIO_K1_PULL S5P_GPIO_K1_BASE(PULL_OFFSET) +#define S5P_GPIO_K1_DRV S5P_GPIO_K1_BASE(DRV_OFFSET) +#define S5P_GPIO_K1_PDNCON S5P_GPIO_K1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K1_PDNPUL S5P_GPIO_K1_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_K2_CON S5P_GPIO_K2_BASE(CON_OFFSET) +#define S5P_GPIO_K2_DAT S5P_GPIO_K2_BASE(DAT_OFFSET) +#define S5P_GPIO_K2_PULL S5P_GPIO_K2_BASE(PULL_OFFSET) +#define S5P_GPIO_K2_DRV S5P_GPIO_K2_BASE(DRV_OFFSET) +#define S5P_GPIO_K2_PDNCON S5P_GPIO_K2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K2_PDNPUL S5P_GPIO_K2_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_K3_CON S5P_GPIO_K3_BASE(CON_OFFSET) +#define S5P_GPIO_K3_DAT S5P_GPIO_K3_BASE(DAT_OFFSET) +#define S5P_GPIO_K3_PULL S5P_GPIO_K3_BASE(PULL_OFFSET) +#define S5P_GPIO_K3_DRV S5P_GPIO_K3_BASE(DRV_OFFSET) +#define S5P_GPIO_K3_PDNCON S5P_GPIO_K3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_K3_PDNPUL S5P_GPIO_K3_BASE(PDNPULL_OFFSET) + +/* GPIO L Bank */ +#define S5P_GPIO_L0_BASE(x) (S5P_GPIO_L_REG(0x0) + (x)) +#define S5P_GPIO_L1_BASE(x) (S5P_GPIO_L_REG(0x20) + (x)) +#define S5P_GPIO_L2_BASE(x) (S5P_GPIO_L_REG(0x40) + (x)) +#define S5P_GPIO_L3_BASE(x) (S5P_GPIO_L_REG(0x60) + (x)) +#define S5P_GPIO_L4_BASE(x) (S5P_GPIO_L_REG(0x80) + (x)) + +#define S5P_GPIO_L0_CON S5P_GPIO_L0_BASE(CON_OFFSET) +#define S5P_GPIO_L0_DAT S5P_GPIO_L0_BASE(DAT_OFFSET) +#define S5P_GPIO_L0_PULL S5P_GPIO_L0_BASE(PULL_OFFSET) +#define S5P_GPIO_L0_DRV S5P_GPIO_L0_BASE(DRV_OFFSET) +#define S5P_GPIO_L0_PDNCON S5P_GPIO_L0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L0_PDNPUL S5P_GPIO_L0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_L1_CON S5P_GPIO_L1_BASE(CON_OFFSET) +#define S5P_GPIO_L1_DAT S5P_GPIO_L1_BASE(DAT_OFFSET) +#define S5P_GPIO_L1_PULL S5P_GPIO_L1_BASE(PULL_OFFSET) +#define S5P_GPIO_L1_DRV S5P_GPIO_L1_BASE(DRV_OFFSET) +#define S5P_GPIO_L1_PDNCON S5P_GPIO_L1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L1_PDNPUL S5P_GPIO_L1_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_L2_CON S5P_GPIO_L2_BASE(CON_OFFSET) +#define S5P_GPIO_L2_DAT S5P_GPIO_L2_BASE(DAT_OFFSET) +#define S5P_GPIO_L2_PULL S5P_GPIO_L2_BASE(PULL_OFFSET) +#define S5P_GPIO_L2_DRV S5P_GPIO_L2_BASE(DRV_OFFSET) +#define S5P_GPIO_L2_PDNCON S5P_GPIO_L2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L2_PDNPUL S5P_GPIO_L2_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_L3_CON S5P_GPIO_L3_BASE(CON_OFFSET) +#define S5P_GPIO_L3_DAT S5P_GPIO_L3_BASE(DAT_OFFSET) +#define S5P_GPIO_L3_PULL S5P_GPIO_L3_BASE(PULL_OFFSET) +#define S5P_GPIO_L3_DRV S5P_GPIO_L3_BASE(DRV_OFFSET) +#define S5P_GPIO_L3_PDNCON S5P_GPIO_L3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L3_PDNPUL S5P_GPIO_L3_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_L4_CON S5P_GPIO_L4_BASE(CON_OFFSET) +#define S5P_GPIO_L4_DAT S5P_GPIO_L4_BASE(DAT_OFFSET) +#define S5P_GPIO_L4_PULL S5P_GPIO_L4_BASE(PULL_OFFSET) +#define S5P_GPIO_L4_DRV S5P_GPIO_L4_BASE(DRV_OFFSET) +#define S5P_GPIO_L4_PDNCON S5P_GPIO_L4_BASE(PDNCON_OFFSET) +#define S5P_GPIO_L4_PDNPUL S5P_GPIO_L4_BASE(PDNPULL_OFFSET) + +/* GPIO MP Bank */ +#define S5P_MP_0_OFFSET 0x0 +#define S5P_MP_1_OFFSET 0x20 +#define S5P_MP_2_OFFSET 0x40 +#define S5P_MP_3_OFFSET 0x60 +#define S5P_MP_4_OFFSET 0x80 +#define S5P_MP_5_OFFSET 0xa0 +#define S5P_MP_6_OFFSET 0xc0 +#define S5P_MP_7_OFFSET 0xe0 + +#define S5P_MP_0_BASE(x) (S5P_MP_REG(S5P_MP_0_OFFSET) + (x)) +#define S5P_MP_1_BASE(x) (S5P_MP_REG(S5P_MP_1_OFFSET) + (x)) +#define S5P_MP_2_BASE(x) (S5P_MP_REG(S5P_MP_2_OFFSET) + (x)) +#define S5P_MP_3_BASE(x) (S5P_MP_REG(S5P_MP_3_OFFSET) + (x)) +#define S5P_MP_4_BASE(x) (S5P_MP_REG(S5P_MP_4_OFFSET) + (x)) +#define S5P_MP_5_BASE(x) (S5P_MP_REG(S5P_MP_5_OFFSET) + (x)) +#define S5P_MP_6_BASE(x) (S5P_MP_REG(S5P_MP_6_OFFSET) + (x)) +#define S5P_MP_7_BASE(x) (S5P_MP_REG(S5P_MP_7_OFFSET) + (x)) + +#define S5P_MP_0PULL S5P_MP_0_BASE(PULL_OFFSET) +#define S5P_MP_0DRV S5P_MP_0_BASE(DRV_OFFSET) +#define S5P_MP_0PDNPULL S5P_MP_0_BASE(PDNPULL_OFFSET) + +#define S5P_MP_1PULL S5P_MP_1_BASE(PULL_OFFSET) +#define S5P_MP_1DRV S5P_MP_1_BASE(DRV_OFFSET) +#define S5P_MP_1PDNPULL S5P_MP_1_BASE(PDNPULL_OFFSET) + +#define S5P_MP_2PULL S5P_MP_2_BASE(PULL_OFFSET) +#define S5P_MP_2DRV S5P_MP_2_BASE(DRV_OFFSET) +#define S5P_MP_2PDNPULL S5P_MP_2_BASE(PDNPULL_OFFSET) + +#define S5P_MP_3DRV S5P_MP_3_BASE(DRV_OFFSET) +#define S5P_MP_4DRV S5P_MP_4_BASE(DRV_OFFSET) +#define S5P_MP_5DRV S5P_MP_5_BASE(DRV_OFFSET) +#define S5P_MP_6DRV S5P_MP_6_BASE(DRV_OFFSET) +#define S5P_MP_7DRV S5P_MP_7_BASE(DRV_OFFSET) +#define S5P_MP_8DRV S5P_MP_8_BASE(DRV_OFFSET) + +/* GPIO ETC Bank */ +#define S5P_ETC0_BASE(x) (S5P_ETC_REG(0x0) + (x)) +#define S5P_ETC1_BASE(x) (S5P_ETC_REG(0x20) + (x)) +#define S5P_ETC2_BASE(x) (S5P_ETC_REG(0x40) + (x)) +#define S5P_ETC3_BASE(x) (S5P_ETC_REG(0x60) + (x)) +#define S5P_ETC4_BASE(x) (S5P_ETC_REG(0x80) + (x)) + +#define S5P_ETC0PULL S5P_ETC0_BASE(PULL_OFFSET) +#define S5P_ETC0DRV S5P_ETC0_BASE(DRV_OFFSET) +#define S5P_ETC1PULL S5P_ETC1_BASE(PULL_OFFSET) +#define S5P_ETC1DRV S5P_ETC1_BASE(DRV_OFFSET) +#define S5P_ETC2PULL S5P_ETC2_BASE(PULL_OFFSET) +#define S5P_ETC2DRV S5P_ETC2_BASE(DRV_OFFSET) +#define S5P_ETC3PULL S5P_ETC3_BASE(PULL_OFFSET) +#define S5P_ETC3DRV S5P_ETC3_BASE(DRV_OFFSET) +#define S5P_ETC4DRV S5P_ETC4_BASE(DRV_OFFSET) + +/* GPIO External Interrupt */ +#define S5P_GPIO_INT0_CON S5P_GPIO_INT_CON_REG(0x0) +#define S5P_GPIO_INT1_CON S5P_GPIO_INT_CON_REG(0x4) +#define S5P_GPIO_INT2_CON S5P_GPIO_INT_CON_REG(0x8) +#define S5P_GPIO_INT3_CON S5P_GPIO_INT_CON_REG(0xc) +#define S5P_GPIO_INT4_CON S5P_GPIO_INT_CON_REG(0x10) +#define S5P_GPIO_INT5_CON S5P_GPIO_INT_CON_REG(0x14) +#define S5P_GPIO_INT6_CON S5P_GPIO_INT_CON_REG(0x18) +#define S5P_GPIO_INT7_CON S5P_GPIO_INT_CON_REG(0x1c) +#define S5P_GPIO_INT8_CON S5P_GPIO_INT_CON_REG(0x20) +#define S5P_GPIO_INT9_CON S5P_GPIO_INT_CON_REG(0x24) +#define S5P_GPIO_INT10_CON S5P_GPIO_INT_CON_REG(0x28) +#define S5P_GPIO_INT11_CON S5P_GPIO_INT_CON_REG(0x2c) +#define S5P_GPIO_INT12_CON S5P_GPIO_INT_CON_REG(0x30) +#define S5P_GPIO_INT13_CON S5P_GPIO_INT_CON_REG(0x34) +#define S5P_GPIO_INT14_CON S5P_GPIO_INT_CON_REG(0x38) +#define S5P_GPIO_INT15_CON S5P_GPIO_INT_CON_REG(0x3c) +#define S5P_GPIO_INT16_CON S5P_GPIO_INT_CON_REG(0x40) +#define S5P_GPIO_INT17_CON S5P_GPIO_INT_CON_REG(0x44) +#define S5P_GPIO_INT18_CON S5P_GPIO_INT_CON_REG(0x48) +#define S5P_GPIO_INT19_CON S5P_GPIO_INT_CON_REG(0x4c) +#define S5P_GPIO_INT20_CON S5P_GPIO_INT_CON_REG(0x50) + +#define S5P_GPIO_INT0_FLTCON0 S5P_GPIO_INT_CON_REG(0x0) +#define S5P_GPIO_INT0_FLTCON1 S5P_GPIO_INT_CON_REG(0x4) +#define S5P_GPIO_INT1_FLTCON0 S5P_GPIO_INT_CON_REG(0x8) +#define S5P_GPIO_INT1_FLTCON1 S5P_GPIO_INT_CON_REG(0xc) +#define S5P_GPIO_INT2_FLTCON0 S5P_GPIO_INT_CON_REG(0x10) +#define S5P_GPIO_INT2_FLTCON1 S5P_GPIO_INT_CON_REG(0x14) +#define S5P_GPIO_INT3_FLTCON0 S5P_GPIO_INT_CON_REG(0x18) +#define S5P_GPIO_INT3_FLTCON1 S5P_GPIO_INT_CON_REG(0x1c) +#define S5P_GPIO_INT4_FLTCON0 S5P_GPIO_INT_CON_REG(0x20) +#define S5P_GPIO_INT4_FLTCON1 S5P_GPIO_INT_CON_REG(0x24) +#define S5P_GPIO_INT5_FLTCON0 S5P_GPIO_INT_CON_REG(0x28) +#define S5P_GPIO_INT5_FLTCON1 S5P_GPIO_INT_CON_REG(0x2c) +#define S5P_GPIO_INT6_FLTCON0 S5P_GPIO_INT_CON_REG(0x30) +#define S5P_GPIO_INT6_FLTCON1 S5P_GPIO_INT_CON_REG(0x34) +#define S5P_GPIO_INT7_FLTCON0 S5P_GPIO_INT_CON_REG(0x38) +#define S5P_GPIO_INT7_FLTCON1 S5P_GPIO_INT_CON_REG(0x3c) +#define S5P_GPIO_INT8_FLTCON0 S5P_GPIO_INT_CON_REG(0x40) +#define S5P_GPIO_INT8_FLTCON1 S5P_GPIO_INT_CON_REG(0x44) +#define S5P_GPIO_INT9_FLTCON0 S5P_GPIO_INT_CON_REG(0x48) +#define S5P_GPIO_INT9_FLTCON1 S5P_GPIO_INT_CON_REG(0x4c) +#define S5P_GPIO_INT10_FLTCON0 S5P_GPIO_INT_CON_REG(0x50) +#define S5P_GPIO_INT11_FLTCON0 S5P_GPIO_INT_CON_REG(0x58) +#define S5P_GPIO_INT11_FLTCON1 S5P_GPIO_INT_CON_REG(0x5c) +#define S5P_GPIO_INT12_FLTCON0 S5P_GPIO_INT_CON_REG(0x60) +#define S5P_GPIO_INT13_FLTCON0 S5P_GPIO_INT_CON_REG(0x68) +#define S5P_GPIO_INT13_FLTCON1 S5P_GPIO_INT_CON_REG(0x6c) +#define S5P_GPIO_INT14_FLTCON0 S5P_GPIO_INT_CON_REG(0x70) +#define S5P_GPIO_INT14_FLTCON1 S5P_GPIO_INT_CON_REG(0x74) +#define S5P_GPIO_INT15_FLTCON0 S5P_GPIO_INT_CON_REG(0x78) +#define S5P_GPIO_INT15_FLTCON1 S5P_GPIO_INT_CON_REG(0x7c) +#define S5P_GPIO_INT16_FLTCON0 S5P_GPIO_INT_CON_REG(0x80) +#define S5P_GPIO_INT16_FLTCON1 S5P_GPIO_INT_CON_REG(0x84) +#define S5P_GPIO_INT17_FLTCON0 S5P_GPIO_INT_CON_REG(0x88) +#define S5P_GPIO_INT17_FLTCON1 S5P_GPIO_INT_CON_REG(0x8c) +#define S5P_GPIO_INT18_FLTCON0 S5P_GPIO_INT_CON_REG(0x90) +#define S5P_GPIO_INT18_FLTCON1 S5P_GPIO_INT_CON_REG(0x94) +#define S5P_GPIO_INT19_FLTCON0 S5P_GPIO_INT_CON_REG(0x98) +#define S5P_GPIO_INT19_FLTCON1 S5P_GPIO_INT_CON_REG(0x9c) +#define S5P_GPIO_INT20_FLTCON0 S5P_GPIO_INT_CON_REG(0xa0) + +#define S5P_GPIO_INT0_MASK S5P_GPIO_INT_MASK_REG(0x00) +#define S5P_GPIO_INT1_MASK S5P_GPIO_INT_MASK_REG(0x04) +#define S5P_GPIO_INT2_MASK S5P_GPIO_INT_MASK_REG(0x08) +#define S5P_GPIO_INT3_MASK S5P_GPIO_INT_MASK_REG(0x0c) +#define S5P_GPIO_INT4_MASK S5P_GPIO_INT_MASK_REG(0x10) +#define S5P_GPIO_INT5_MASK S5P_GPIO_INT_MASK_REG(0x14) +#define S5P_GPIO_INT6_MASK S5P_GPIO_INT_MASK_REG(0x18) +#define S5P_GPIO_INT7_MASK S5P_GPIO_INT_MASK_REG(0x1c) +#define S5P_GPIO_INT8_MASK S5P_GPIO_INT_MASK_REG(0x20) +#define S5P_GPIO_INT9_MASK S5P_GPIO_INT_MASK_REG(0x24) +#define S5P_GPIO_INT10_MASK S5P_GPIO_INT_MASK_REG(0x28) +#define S5P_GPIO_INT11_MASK S5P_GPIO_INT_MASK_REG(0x2c) +#define S5P_GPIO_INT12_MASK S5P_GPIO_INT_MASK_REG(0x30) +#define S5P_GPIO_INT13_MASK S5P_GPIO_INT_MASK_REG(0x34) +#define S5P_GPIO_INT14_MASK S5P_GPIO_INT_MASK_REG(0x38) +#define S5P_GPIO_INT15_MASK S5P_GPIO_INT_MASK_REG(0x3c) +#define S5P_GPIO_INT16_MASK S5P_GPIO_INT_MASK_REG(0x40) +#define S5P_GPIO_INT17_MASK S5P_GPIO_INT_MASK_REG(0x44) +#define S5P_GPIO_INT18_MASK S5P_GPIO_INT_MASK_REG(0x48) +#define S5P_GPIO_INT19_MASK S5P_GPIO_INT_MASK_REG(0x4c) +#define S5P_GPIO_INT20_MASK S5P_GPIO_INT_MASK_REG(0x50) + +#define S5P_GPIO_INT0_PEND S5P_GPIO_INT_PEND_REG(0x00) +#define S5P_GPIO_INT1_PEND S5P_GPIO_INT_PEND_REG(0x04) +#define S5P_GPIO_INT2_PEND S5P_GPIO_INT_PEND_REG(0x08) +#define S5P_GPIO_INT3_PEND S5P_GPIO_INT_PEND_REG(0x0c) +#define S5P_GPIO_INT4_PEND S5P_GPIO_INT_PEND_REG(0x10) +#define S5P_GPIO_INT5_PEND S5P_GPIO_INT_PEND_REG(0x14) +#define S5P_GPIO_INT6_PEND S5P_GPIO_INT_PEND_REG(0x18) +#define S5P_GPIO_INT7_PEND S5P_GPIO_INT_PEND_REG(0x1c) +#define S5P_GPIO_INT8_PEND S5P_GPIO_INT_PEND_REG(0x20) +#define S5P_GPIO_INT9_PEND S5P_GPIO_INT_PEND_REG(0x24) +#define S5P_GPIO_INT10_PEND S5P_GPIO_INT_PEND_REG(0x28) +#define S5P_GPIO_INT11_PEND S5P_GPIO_INT_PEND_REG(0x2c) +#define S5P_GPIO_INT12_PEND S5P_GPIO_INT_PEND_REG(0x30) +#define S5P_GPIO_INT13_PEND S5P_GPIO_INT_PEND_REG(0x34) +#define S5P_GPIO_INT14_PEND S5P_GPIO_INT_PEND_REG(0x38) +#define S5P_GPIO_INT15_PEND S5P_GPIO_INT_PEND_REG(0x3c) +#define S5P_GPIO_INT16_PEND S5P_GPIO_INT_PEND_REG(0x40) +#define S5P_GPIO_INT17_PEND S5P_GPIO_INT_PEND_REG(0x44) +#define S5P_GPIO_INT18_PEND S5P_GPIO_INT_PEND_REG(0x48) +#define S5P_GPIO_INT19_PEND S5P_GPIO_INT_PEND_REG(0x4c) +#define S5P_GPIO_INT20_PEND S5P_GPIO_INT_PEND_REG(0x50) + +#define S5P_GPIO_INT_GRPPRI S5P_GPIO_INT_PRIO_REG(0x00) +#define S5P_GPIO_INT_PRIORITY S5P_GPIO_INT_PRIO_REG(0x04) +#define S5P_GPIO_INT_SERVICE S5P_GPIO_INT_PRIO_REG(0x08) +#define S5P_GPIO_INT_SERVICE_PEND S5P_GPIO_INT_PRIO_REG(0x0c) +#define S5P_GPIO_INT_GRPFIXPRI S5P_GPIO_INT_PRIO_REG(0x10) + +#define S5P_GPIO_INT0_FIXPRI S5P_GPIO_INT_PRIO_REG(0x14) +#define S5P_GPIO_INT1_FIXPRI S5P_GPIO_INT_PRIO_REG(0x18) +#define S5P_GPIO_INT2_FIXPRI S5P_GPIO_INT_PRIO_REG(0x1c) +#define S5P_GPIO_INT3_FIXPRI S5P_GPIO_INT_PRIO_REG(0x20) +#define S5P_GPIO_INT4_FIXPRI S5P_GPIO_INT_PRIO_REG(0x24) +#define S5P_GPIO_INT5_FIXPRI S5P_GPIO_INT_PRIO_REG(0x28) +#define S5P_GPIO_INT6_FIXPRI S5P_GPIO_INT_PRIO_REG(0x2c) +#define S5P_GPIO_INT7_FIXPRI S5P_GPIO_INT_PRIO_REG(0x30) +#define S5P_GPIO_INT8_FIXPRI S5P_GPIO_INT_PRIO_REG(0x34) +#define S5P_GPIO_INT9_FIXPRI S5P_GPIO_INT_PRIO_REG(0x38) +#define S5P_GPIO_INT10_FIXPRI S5P_GPIO_INT_PRIO_REG(0x3c) +#define S5P_GPIO_INT11_FIXPRI S5P_GPIO_INT_PRIO_REG(0x40) +#define S5P_GPIO_INT12_FIXPRI S5P_GPIO_INT_PRIO_REG(0x44) +#define S5P_GPIO_INT13_FIXPRI S5P_GPIO_INT_PRIO_REG(0x48) +#define S5P_GPIO_INT14_FIXPRI S5P_GPIO_INT_PRIO_REG(0x4c) +#define S5P_GPIO_INT15_FIXPRI S5P_GPIO_INT_PRIO_REG(0x50) +#define S5P_GPIO_INT16_FIXPRI S5P_GPIO_INT_PRIO_REG(0x54) +#define S5P_GPIO_INT17_FIXPRI S5P_GPIO_INT_PRIO_REG(0x58) +#define S5P_GPIO_INT18_FIXPRI S5P_GPIO_INT_PRIO_REG(0x5c) +#define S5P_GPIO_INT19_FIXPRI S5P_GPIO_INT_PRIO_REG(0x60) +#define S5P_GPIO_INT20_FIXPRI S5P_GPIO_INT_PRIO_REG(0x64) + +/* GPIO H Bank Base */ +#define S5P_GPIO_H0_BASE(x) (S5P_GPIO_H_REG(0x0) + (x)) +#define S5P_GPIO_H1_BASE(x) (S5P_GPIO_H_REG(0x20) + (x)) +#define S5P_GPIO_H2_BASE(x) (S5P_GPIO_H_REG(0x40) + (x)) +#define S5P_GPIO_H3_BASE(x) (S5P_GPIO_H_REG(0x60) + (x)) + +#define S5P_GPIO_H0_CON S5P_GPIO_H0_BASE(CON_OFFSET) +#define S5P_GPIO_H0_DAT S5P_GPIO_H0_BASE(DAT_OFFSET) +#define S5P_GPIO_H0_PULL S5P_GPIO_H0_BASE(PULL_OFFSET) +#define S5P_GPIO_H0_DRV S5P_GPIO_H0_BASE(DRV_OFFSET) +#define S5P_GPIO_H0_PDNCON S5P_GPIO_H0_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H0_PDNPUL S5P_GPIO_H0_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_H1_CON S5P_GPIO_H1_BASE(CON_OFFSET) +#define S5P_GPIO_H1_DAT S5P_GPIO_H1_BASE(DAT_OFFSET) +#define S5P_GPIO_H1_PULL S5P_GPIO_H1_BASE(PULL_OFFSET) +#define S5P_GPIO_H1_DRV S5P_GPIO_H1_BASE(DRV_OFFSET) +#define S5P_GPIO_H1_PDNCON S5P_GPIO_H1_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H1_PDNPUL S5P_GPIO_H1_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_H2_CON S5P_GPIO_H2_BASE(CON_OFFSET) +#define S5P_GPIO_H2_DAT S5P_GPIO_H2_BASE(DAT_OFFSET) +#define S5P_GPIO_H2_PULL S5P_GPIO_H2_BASE(PULL_OFFSET) +#define S5P_GPIO_H2_DRV S5P_GPIO_H2_BASE(DRV_OFFSET) +#define S5P_GPIO_H2_PDNCON S5P_GPIO_H2_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H2_PDNPUL S5P_GPIO_H2_BASE(PDNPULL_OFFSET) + +#define S5P_GPIO_H3_CON S5P_GPIO_H3_BASE(CON_OFFSET) +#define S5P_GPIO_H3_DAT S5P_GPIO_H3_BASE(DAT_OFFSET) +#define S5P_GPIO_H3_PULL S5P_GPIO_H3_BASE(PULL_OFFSET) +#define S5P_GPIO_H3_DRV S5P_GPIO_H3_BASE(DRV_OFFSET) +#define S5P_GPIO_H3_PDNCON S5P_GPIO_H3_BASE(PDNCON_OFFSET) +#define S5P_GPIO_H3_PDNPUL S5P_GPIO_H3_BASE(PDNPULL_OFFSET) + +/* GPIO Wakeup Interrupt Configuration */ +#define S5P_GPIO_WAKEUP_INT0_CON S5P_WAKEUP_INT_CON(0x00) +#define S5P_GPIO_WAKEUP_INT1_CON S5P_WAKEUP_INT_CON(0x04) +#define S5P_GPIO_WAKEUP_INT2_CON S5P_WAKEUP_INT_CON(0x08) +#define S5P_GPIO_WAKEUP_INT3_CON S5P_WAKEUP_INT_CON(0x0c) + +/* GPIO Wakeup Interrupt Filter Configuration */ +#define S5P_GPIO_WAKEUP_FLTINT0_CON0 S5P_WAKEUP_FLTINT_CON(0x00) +#define S5P_GPIO_WAKEUP_FLTINT0_CON1 S5P_WAKEUP_FLTINT_CON(0x04) +#define S5P_GPIO_WAKEUP_FLTINT1_CON0 S5P_WAKEUP_FLTINT_CON(0x08) +#define S5P_GPIO_WAKEUP_FLTINT1_CON1 S5P_WAKEUP_FLTINT_CON(0x0c) +#define S5P_GPIO_WAKEUP_FLTINT2_CON0 S5P_WAKEUP_FLTINT_CON(0x10) +#define S5P_GPIO_WAKEUP_FLTINT2_CON1 S5P_WAKEUP_FLTINT_CON(0x14) +#define S5P_GPIO_WAKEUP_FLTINT3_CON0 S5P_WAKEUP_FLTINT_CON(0x18) +#define S5P_GPIO_WAKEUP_FLTINT3_CON1 S5P_WAKEUP_FLTINT_CON(0x1c) + +/* GPIO Wakeup Interrupt Mask */ +#define S5P_GPIO_WAKEUP_INT0_MASK S5P_WAKEUP_INT_MASK(0x00) +#define S5P_GPIO_WAKEUP_INT1_MASK S5P_WAKEUP_INT_MASK(0x04) +#define S5P_GPIO_WAKEUP_INT2_MASK S5P_WAKEUP_INT_MASK(0x08) +#define S5P_GPIO_WAKEUP_INT3_MASK S5P_WAKEUP_INT_MASK(0x0c) + +/* GPIO Wakeup Interrupt Pend */ +#define S5P_GPIO_WAKEUP_INT0_PEND S5P_WAKEUP_INT_PEND(0x00) +#define S5P_GPIO_WAKEUP_INT1_PEND S5P_WAKEUP_INT_PEND(0x04) +#define S5P_GPIO_WAKEUP_INT2_PEND S5P_WAKEUP_INT_PEND(0x08) +#define S5P_GPIO_WAKEUP_INT3_PEND S5P_WAKEUP_INT_PEND(0x0c) + diff --git a/include/asm-arm/arch-s5pc100/uart.h b/include/asm-arm/arch-s5pc100/uart.h new file mode 100644 index 0000000..4d2482a --- /dev/null +++ b/include/asm-arm/arch-s5pc100/uart.h @@ -0,0 +1,68 @@ + +/* + * UART + */ +/* uart base address */ +#define S5P_PA_UART S5P_ADDR(0x0c000000) /* UART */ +#define UARTx_OFFSET(x) (S5P_PA_UART + x * 0x400) +#define S5P_UART_BASE (S5P_PA_UART) +/* uart offset */ +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UMCON_OFFSET 0x0C +#define UTRSTAT_OFFSET 0x10 +#define UERSTAT_OFFSET 0x14 +#define UFSTAT_OFFSET 0x18 +#define UMSTAT_OFFSET 0x1C +#define UTXH_OFFSET 0x20 +#define URXH_OFFSET 0x24 +#define UBRDIV_OFFSET 0x28 +#define UDIVSLOT_OFFSET 0x2C +#define UINTP_OFFSET 0x30 +#define UINTSP_OFFSET 0x34 +#define UINTM_OFFSET 0x38 + +#define UTRSTAT_TX_EMPTY (1 << 2) +#define UTRSTAT_RX_READY (1 << 0) +#define UART_ERR_MASK 0xF + +#ifndef __ASSEMBLY__ +typedef struct s5pc1xx_uart { + volatile unsigned long ULCON; + volatile unsigned long UCON; + volatile unsigned long UFCON; + volatile unsigned long UMCON; + volatile unsigned long UTRSTAT; + volatile unsigned long UERSTAT; + volatile unsigned long UFSTAT; + volatile unsigned long UMSTAT; +#ifdef __BIG_ENDIAN + volatile unsigned char res1[3]; + volatile unsigned char UTXH; + volatile unsigned char res2[3]; + volatile unsigned char URXH; +#else /* Little Endian */ + volatile unsigned char UTXH; + volatile unsigned char res1[3]; + volatile unsigned char URXH; + volatile unsigned char res2[3]; +#endif + volatile unsigned long UBRDIV; +#ifdef __BIG_ENDIAN + volatile unsigned char res3[2]; + volatile unsigned short UDIVSLOT; +#else + volatile unsigned short UDIVSLOT; + volatile unsigned char res3[2]; +#endif +} s5pc1xx_uart_t; + +enum s5pc1xx_uarts_nr { + S5PC1XX_UART0, + S5PC1XX_UART1, + S5PC1XX_UART2, + S5PC1XX_UART3, +}; +#endif /* __ASSEMBLY__ */ + diff --git a/include/asm-arm/arch-s5pc100/watchdog.h b/include/asm-arm/arch-s5pc100/watchdog.h new file mode 100644 index 0000000..668bb09 --- /dev/null +++ b/include/asm-arm/arch-s5pc100/watchdog.h @@ -0,0 +1,16 @@ + +/* + * Watchdog + */ +#define S5P_WATCHDOG_BASE(x) (S5P_PA_WATCHDOG + (x)) + +#define WTCON_OFFSET 0x0 +#define WTDAT_OFFSET 0x4 +#define WTCNT_OFFSET 0x8 +#define WTCLRINT_OFFSET 0xc + +#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET) +#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET) +#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET) +#define S5P_WTCLRINT S5P_WATCHDOG_BASE(WTCLRINT_OFFSET) + diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h index 8954184..67f1bd3 100644 --- a/include/s5pc1xx.h +++ b/include/s5pc1xx.h @@ -1262,276 +1262,276 @@ /* SROM Base */ #define S5P_SROMC_BASE(x) (S5P_PA_SROMC + (x)) -/* SROM offset */ -#define SROM_BW_OFFSET 0x0 -#define SROM_BC0_OFFSET 0x04 -#define SROM_BC1_OFFSET 0x08 -#define SROM_BC2_OFFSET 0x0c -#define SROM_BC3_OFFSET 0x10 -#define SROM_BC4_OFFSET 0x14 -#define SROM_BC5_OFFSET 0x18 - -/* SROM Register */ -#define S5P_SROM_BW S5P_SROMC_BASE(SROM_BW_OFFSET) -#define S5P_SROM_BC0 S5P_SROMC_BASE(SROM_BC0_OFFSET) -#define S5P_SROM_BC1 S5P_SROMC_BASE(SROM_BC1_OFFSET) -#define S5P_SROM_BC2 S5P_SROMC_BASE(SROM_BC2_OFFSET) -#define S5P_SROM_BC3 S5P_SROMC_BASE(SROM_BC3_OFFSET) -#define S5P_SROM_BC4 S5P_SROMC_BASE(SROM_BC4_OFFSET) -#define S5P_SROM_BC5 S5P_SROMC_BASE(SROM_BC5_OFFSET) - -/* SROM Addressing */ -#define S5P_SROM_BW_REG __REG(S5P_SROM_BW) -#define S5P_SROM_BC0_REG __REG(S5P_SROM_BC0) -#define S5P_SROM_BC1_REG __REG(S5P_SROM_BC1) -#define S5P_SROM_BC2_REG __REG(S5P_SROM_BC2) -#define S5P_SROM_BC3_REG __REG(S5P_SROM_BC3) -#define S5P_SROM_BC4_REG __REG(S5P_SROM_BC4) -#define S5P_SROM_BC5_REG __REG(S5P_SROM_BC5) - -/* OneNAND */ -#define S5P_ONENANDC_BASE(x) (S5P_PA_ONENANDC + (x)) - -/* OneNAND offset */ -#define MEM_CFG_OFFSET 0x0 -#define BURST_LEN_OFFSET 0x10 -#define MEM_RESET_OFFSET 0x20 -#define INT_ERR_STAT_OFFSET 0x30 -#define INT_ERR_MASK_OFFSET 0x40 -#define INT_ERR_ACK_OFFSET 0x50 -#define ECC_ERR_STAT_1_OFFSET 0x60 -#define MANUFACT_ID_OFFSET 0x70 -#define DEVICE_ID_OFFSET 0x80 -#define DATA_BUF_SIZE_OFFSET 0x90 -#define BOOT_BUF_SIZE_OFFSET 0xa0 -#define BUF_AMOUNT_OFFSET 0xb0 -#define TECH_OFFSET 0xc0 -#define FBA_WIDTH_OFFSET 0xd0 -#define FPA_WIDTH_OFFSET 0xe0 -#define FSA_WIDTH_OFFSET 0xf0 -#define REVISION_OFFSET 0x100 -#define SYNC_MODE_OFFSET 0x130 -#define TRANS_SPARE_OFFSET 0x140 -#define PAGE_CNT_OFFSET 0x170 -#define ERR_PAGE_ADDR_OFFSET 0x180 -#define BURST_RD_LAT_OFFSET 0x190 -#define INT_PIN_ENABLE_OFFSET 0x1a0 -#define INT_MON_CYC_OFFSET 0x1b0 -#define ACC_CLOCK_OFFSET 0x1c0 -#define ERR_BLK_ADDR_OFFSET 0x1e0 -#define FLASH_VER_ID_OFFSET 0x1f0 -#define BANK_EN_OFFSET 0x220 -#define WTCHDG_RST_L_OFFSET 0x260 -#define WTCHDG_RST_H_OFFSET 0x270 -#define SYNC_WRITE_OFFSET 0x280 -#define CACHE_READ_OFFSET 0x290 -#define COLD_RST_DLY_OFFSET 0x2a0 -#define DDP_DEVICE_OFFSET 0x2b0 -#define MULTI_PLANE_OFFSET 0x2c0 -#define TRANS_MODE_OFFSET 0x2e0 -#define DEV_STAT_OFFSET 0x2f0 -#define ECC_ERR_STAT_2_OFFSET 0x300 -#define ECC_ERR_STAT_3_OFFSET 0x310 -#define ECC_ERR_STAT_4_OFFSET 0x320 -#define EFCT_BUF_CNT_OFFSET 0x330 -#define DEV_PAGE_SIZE_OFFSET 0x340 -#define SUPERLOAD_EN_OFFSET 0x350 -#define CACHE_PRG_EN_OFFSET 0x360 -#define SINGLE_PAGE_BUF_OFFSET 0x370 -#define OFFSET_ADDR_OFFSET 0x380 -#define INT_MON_STATUS_OFFSET 0x390 - -/* OneNAND register */ -#define S5P_MEM_CFG S5P_ONENANDC_BASE(MEM_CFG_OFFSET) -#define S5P_BURST_LEN S5P_ONENANDC_BASE(BURST_LEN_OFFSET) -#define S5P_MEM_RESET S5P_ONENANDC_BASE(MEM_RESET_OFFSET) -#define S5P_INT_ERR_STAT S5P_ONENANDC_BASE(INT_ERR_STAT_OFFSET) -#define S5P_INT_ERR_MASK S5P_ONENANDC_BASE(INT_ERR_MASK_OFFSET) -#define S5P_INT_ERR_ACK S5P_ONENANDC_BASE(INT_ERR_ACK_OFFSET) -#define S5P_ECC_ERR_STAT_1 S5P_ONENANDC_BASE(ECC_ERR_STAT_1_OFFSET) -#define S5P_MANUFACT_ID S5P_ONENANDC_BASE(MANUFACT_ID_OFFSET) -#define S5P_DEVICE_ID S5P_ONENANDC_BASE(DEVICE_ID_OFFSET) -#define S5P_DATA_BUF_SIZE S5P_ONENANDC_BASE(DATA_BUF_SIZE_OFFSET) -#define S5P_BOOT_BUF_SIZE S5P_ONENANDC_BASE(BOOT_BUF_SIZE_OFFSET) -#define S5P_BUF_AMOUNT S5P_ONENANDC_BASE(BUF_AMOUNT_OFFSET) -#define S5P_TECH S5P_ONENANDC_BASE(TECH_OFFSET) -#define S5P_FBA_WIDTH S5P_ONENANDC_BASE(FBA_WIDTH_OFFSET) -#define S5P_FPA_WIDTH S5P_ONENANDC_BASE(FPA_WIDTH_OFFSET) -#define S5P_FSA_WIDTH S5P_ONENANDC_BASE(FSA_WIDTH_OFFSET) -#define S5P_REVISION S5P_ONENANDC_BASE(REVISION_OFFSET) -#define S5P_SYNC_MODE S5P_ONENANDC_BASE(SYNC_MODE_OFFSET) -#define S5P_TRANS_SPARE S5P_ONENANDC_BASE(TRANS_SPARE_OFFSET) -#define S5P_PAGE_CNT S5P_ONENANDC_BASE(PAGE_CNT_OFFSET) -#define S5P_ERR_PAGE_ADDR S5P_ONENANDC_BASE(ERR_PAGE_ADDR_OFFSET) -#define S5P_BURST_RD_LAT S5P_ONENANDC_BASE(BURST_RD_LAT_OFFSET) -#define S5P_INT_PIN_ENABLE S5P_ONENANDC_BASE(INT_PIN_ENABLE_OFFSET) -#define S5P_INT_MON_CYC S5P_ONENANDC_BASE(INT_MON_CYC_OFFSET) -#define S5P_ACC_CLOCK S5P_ONENANDC_BASE(ACC_CLOCK_OFFSET) -#define S5P_ERR_BLK_ADDR S5P_ONENANDC_BASE(ERR_BLK_ADDR_OFFSET) -#define S5P_FLASH_VER_ID S5P_ONENANDC_BASE(FLASH_VER_ID_OFFSET) -#define S5P_BANK_EN S5P_ONENANDC_BASE(BANK_EN_OFFSET) -#define S5P_WTCHDG_RST_L S5P_ONENANDC_BASE(WTCHDG_RST_L_OFFSET) -#define S5P_WTCHDG_RST_H S5P_ONENANDC_BASE(WTCHDG_RST_H_OFFSET) -#define S5P_SYNC_WRITE S5P_ONENANDC_BASE(SYNC_WRITE_OFFSET) -#define S5P_CACHE_READ S5P_ONENANDC_BASE(CACHE_READ_OFFSET) -#define S5P_COLD_RST_DLY S5P_ONENANDC_BASE(COLD_RST_DLY_OFFSET) -#define S5P_DDP_DEVICE S5P_ONENANDC_BASE(DDP_DEVICE_OFFSET) -#define S5P_MULTI_PLANE S5P_ONENANDC_BASE(MULTI_PLANE_OFFSET) -#define S5P_MEM_CNT S5P_ONENANDC_BASE(MEM_CNT_OFFSET) -#define S5P_TRANS_MODE S5P_ONENANDC_BASE(TRANS_MODE_OFFSET) -#define S5P_DEV_START S5P_ONENANDC_BASE(DEV_START_OFFSET) -#define S5P_ECC_ERR_STAT_2 S5P_ONENANDC_BASE(ECC_ERR_STAT_2_OFFSET) -#define S5P_ECC_ERR_STAT_3 S5P_ONENANDC_BASE(ECC_ERR_STAT_3_OFFSET) -#define S5P_ECC_ERR_STAT_4 S5P_ONENANDC_BASE(ECC_ERR_STAT_4_OFFSET) -#define S5P_EFCT_BUF_CNT S5P_ONENANDC_BASE(EFCT_BUF_CNT_OFFSET) -#define S5P_DEV_PAGE_SIZE S5P_ONENANDC_BASE(DEV_PAGE_SIZE_OFFSET) -#define S5P_SUPERLOAD_EN S5P_ONENANDC_BASE(SUPERLOAD_EN_OFFSET) -#define S5P_CACHE_PRG_EN S5P_ONENANDC_BASE(CACHE_PRG_EN_OFFSET) -#define S5P_SINGLE_PAGE_BUF S5P_ONENANDC_BASE(SINGLE_PAGE_BUF_OFFSET) -#define S5P_OFFSET_ADDR S5P_ONENANDC_BASE(OFFSET_ADDR_OFFSET) -#define S5P_INT_MON_STATUS S5P_ONENANDC_BASE(INT_MON_STATUS_OFFSET) +/* srom offset */ +#define srom_bw_offset 0x0 +#define srom_bc0_offset 0x04 +#define srom_bc1_offset 0x08 +#define srom_bc2_offset 0x0c +#define srom_bc3_offset 0x10 +#define srom_bc4_offset 0x14 +#define srom_bc5_offset 0x18 + +/* srom register */ +#define s5p_srom_bw s5p_sromc_base(srom_bw_offset) +#define s5p_srom_bc0 s5p_sromc_base(srom_bc0_offset) +#define s5p_srom_bc1 s5p_sromc_base(srom_bc1_offset) +#define s5p_srom_bc2 s5p_sromc_base(srom_bc2_offset) +#define s5p_srom_bc3 s5p_sromc_base(srom_bc3_offset) +#define s5p_srom_bc4 s5p_sromc_base(srom_bc4_offset) +#define s5p_srom_bc5 s5p_sromc_base(srom_bc5_offset) + +/* srom addressing */ +#define s5p_srom_bw_reg __reg(s5p_srom_bw) +#define s5p_srom_bc0_reg __reg(s5p_srom_bc0) +#define s5p_srom_bc1_reg __reg(s5p_srom_bc1) +#define s5p_srom_bc2_reg __reg(s5p_srom_bc2) +#define s5p_srom_bc3_reg __reg(s5p_srom_bc3) +#define s5p_srom_bc4_reg __reg(s5p_srom_bc4) +#define s5p_srom_bc5_reg __reg(s5p_srom_bc5) + +/* onenand */ +#define s5p_onenandc_base(x) (s5p_pa_onenandc + (x)) + +/* onenand offset */ +#define mem_cfg_offset 0x0 +#define burst_len_offset 0x10 +#define mem_reset_offset 0x20 +#define int_err_stat_offset 0x30 +#define int_err_mask_offset 0x40 +#define int_err_ack_offset 0x50 +#define ecc_err_stat_1_offset 0x60 +#define manufact_id_offset 0x70 +#define device_id_offset 0x80 +#define data_buf_size_offset 0x90 +#define boot_buf_size_offset 0xa0 +#define buf_amount_offset 0xb0 +#define tech_offset 0xc0 +#define fba_width_offset 0xd0 +#define fpa_width_offset 0xe0 +#define fsa_width_offset 0xf0 +#define revision_offset 0x100 +#define sync_mode_offset 0x130 +#define trans_spare_offset 0x140 +#define page_cnt_offset 0x170 +#define err_page_addr_offset 0x180 +#define burst_rd_lat_offset 0x190 +#define int_pin_enable_offset 0x1a0 +#define int_mon_cyc_offset 0x1b0 +#define acc_clock_offset 0x1c0 +#define err_blk_addr_offset 0x1e0 +#define flash_ver_id_offset 0x1f0 +#define bank_en_offset 0x220 +#define wtchdg_rst_l_offset 0x260 +#define wtchdg_rst_h_offset 0x270 +#define sync_write_offset 0x280 +#define cache_read_offset 0x290 +#define cold_rst_dly_offset 0x2a0 +#define ddp_device_offset 0x2b0 +#define multi_plane_offset 0x2c0 +#define trans_mode_offset 0x2e0 +#define dev_stat_offset 0x2f0 +#define ecc_err_stat_2_offset 0x300 +#define ecc_err_stat_3_offset 0x310 +#define ecc_err_stat_4_offset 0x320 +#define efct_buf_cnt_offset 0x330 +#define dev_page_size_offset 0x340 +#define superload_en_offset 0x350 +#define cache_prg_en_offset 0x360 +#define single_page_buf_offset 0x370 +#define offset_addr_offset 0x380 +#define int_mon_status_offset 0x390 + +/* onenand register */ +#define s5p_mem_cfg s5p_onenandc_base(mem_cfg_offset) +#define s5p_burst_len s5p_onenandc_base(burst_len_offset) +#define s5p_mem_reset s5p_onenandc_base(mem_reset_offset) +#define s5p_int_err_stat s5p_onenandc_base(int_err_stat_offset) +#define s5p_int_err_mask s5p_onenandc_base(int_err_mask_offset) +#define s5p_int_err_ack s5p_onenandc_base(int_err_ack_offset) +#define s5p_ecc_err_stat_1 s5p_onenandc_base(ecc_err_stat_1_offset) +#define s5p_manufact_id s5p_onenandc_base(manufact_id_offset) +#define s5p_device_id s5p_onenandc_base(device_id_offset) +#define s5p_data_buf_size s5p_onenandc_base(data_buf_size_offset) +#define s5p_boot_buf_size s5p_onenandc_base(boot_buf_size_offset) +#define s5p_buf_amount s5p_onenandc_base(buf_amount_offset) +#define s5p_tech s5p_onenandc_base(tech_offset) +#define s5p_fba_width s5p_onenandc_base(fba_width_offset) +#define s5p_fpa_width s5p_onenandc_base(fpa_width_offset) +#define s5p_fsa_width s5p_onenandc_base(fsa_width_offset) +#define s5p_revision s5p_onenandc_base(revision_offset) +#define s5p_sync_mode s5p_onenandc_base(sync_mode_offset) +#define s5p_trans_spare s5p_onenandc_base(trans_spare_offset) +#define s5p_page_cnt s5p_onenandc_base(page_cnt_offset) +#define s5p_err_page_addr s5p_onenandc_base(err_page_addr_offset) +#define s5p_burst_rd_lat s5p_onenandc_base(burst_rd_lat_offset) +#define s5p_int_pin_enable s5p_onenandc_base(int_pin_enable_offset) +#define s5p_int_mon_cyc s5p_onenandc_base(int_mon_cyc_offset) +#define s5p_acc_clock s5p_onenandc_base(acc_clock_offset) +#define s5p_err_blk_addr s5p_onenandc_base(err_blk_addr_offset) +#define s5p_flash_ver_id s5p_onenandc_base(flash_ver_id_offset) +#define s5p_bank_en s5p_onenandc_base(bank_en_offset) +#define s5p_wtchdg_rst_l s5p_onenandc_base(wtchdg_rst_l_offset) +#define s5p_wtchdg_rst_h s5p_onenandc_base(wtchdg_rst_h_offset) +#define s5p_sync_write s5p_onenandc_base(sync_write_offset) +#define s5p_cache_read s5p_onenandc_base(cache_read_offset) +#define s5p_cold_rst_dly s5p_onenandc_base(cold_rst_dly_offset) +#define s5p_ddp_device s5p_onenandc_base(ddp_device_offset) +#define s5p_multi_plane s5p_onenandc_base(multi_plane_offset) +#define s5p_mem_cnt s5p_onenandc_base(mem_cnt_offset) +#define s5p_trans_mode s5p_onenandc_base(trans_mode_offset) +#define s5p_dev_start s5p_onenandc_base(dev_start_offset) +#define s5p_ecc_err_stat_2 s5p_onenandc_base(ecc_err_stat_2_offset) +#define s5p_ecc_err_stat_3 s5p_onenandc_base(ecc_err_stat_3_offset) +#define s5p_ecc_err_stat_4 s5p_onenandc_base(ecc_err_stat_4_offset) +#define s5p_efct_buf_cnt s5p_onenandc_base(efct_buf_cnt_offset) +#define s5p_dev_page_size s5p_onenandc_base(dev_page_size_offset) +#define s5p_superload_en s5p_onenandc_base(superload_en_offset) +#define s5p_cache_prg_en s5p_onenandc_base(cache_prg_en_offset) +#define s5p_single_page_buf s5p_onenandc_base(single_page_buf_offset) +#define s5p_offset_addr s5p_onenandc_base(offset_addr_offset) +#define s5p_int_mon_status s5p_onenandc_base(int_mon_status_offset) /* - * Timer - * : PWM, Watchdog, System timer, RTC + * timer + * : pwm, watchdog, system timer, rtc */ -/* PWM */ -#define S5P_PWMTIMER_BASE(x) (S5P_PA_PWMTIMER + (x)) - -/* PWM timer offset */ -#define PWM_TCFG0_OFFSET 0x0 -#define PWM_TCFG1_OFFSET 0x04 -#define PWM_TCON_OFFSET 0x08 -#define PWM_TCNTB0_OFFSET 0x0c -#define PWM_TCMPB0_OFFSET 0x10 -#define PWM_TCNTO0_OFFSET 0x14 -#define PWM_TCNTB1_OFFSET 0x18 -#define PWM_TCMPB1_OFFSET 0x1c -#define PWM_TCNTO1_OFFSET 0x20 -#define PWM_TCNTB2_OFFSET 0x24 -#define PWM_TCMPB2_OFFSET 0x28 -#define PWM_TCNTO2_OFFSET 0x2c -#define PWM_TCNTB3_OFFSET 0x30 -#define PWM_TCNTO3_OFFSET 0x38 -#define PWM_TCNTB4_OFFSET 0x3c -#define PWM_TCNTO4_OFFSET 0x40 -#define PWM_TINT_CSTAT_OFFSET 0x44 - -/* PWM timer register */ -#define S5P_PWM_TCFG0 S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET) -#define S5P_PWM_TCFG1 S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET) -#define S5P_PWM_TCON S5P_PWMTIMER_BASE(PWM_TCON_OFFSET) -#define S5P_PWM_TCNTB0 S5P_PWMTIMER_BASE(PWM_TCNTB0_OFFSET) -#define S5P_PWM_TCMPB0 S5P_PWMTIMER_BASE(PWM_TCMPB0_OFFSET) -#define S5P_PWM_TCNTO0 S5P_PWMTIMER_BASE(PWM_TCNTO0_OFFSET) -#define S5P_PWM_TCNTB1 S5P_PWMTIMER_BASE(PWM_TCNTB1_OFFSET) -#define S5P_PWM_TCMPB1 S5P_PWMTIMER_BASE(PWM_TCMPB1_OFFSET) -#define S5P_PWM_TCNTO1 S5P_PWMTIMER_BASE(PWM_TCNTO1_OFFSET) -#define S5P_PWM_TCNTB2 S5P_PWMTIMER_BASE(PWM_TCNTB2_OFFSET) -#define S5P_PWM_TCMPB2 S5P_PWMTIMER_BASE(PWM_TCMPB2_OFFSET) -#define S5P_PWM_TCNTO2 S5P_PWMTIMER_BASE(PWM_TCNTO2_OFFSET) -#define S5P_PWM_TCNTB3 S5P_PWMTIMER_BASE(PWM_TCNTB3_OFFSET) -#define S5P_PWM_TCNTO3 S5P_PWMTIMER_BASE(PWM_TCNTO3_OFFSET) -#define S5P_PWM_TCNTB4 S5P_PWMTIMER_BASE(PWM_TCNTB4_OFFSET) -#define S5P_PWM_TCNTO4 S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET) -#define S5P_PWM_TINT_CSTAT S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET) - -/* PWM timer addressing */ -#define S5P_TIMER_BASE S5P_PWMTIMER_BASE(0x0) -#define S5P_PWMTIMER_BASE_REG __REG(S5P_PWMTIMER_BASE(0x0)) -#define S5P_PWM_TCFG0_REG __REG(S5P_PWM_TCFG0) -#define S5P_PWM_TCFG1_REG __REG(S5P_PWM_TCFG1) -#define S5P_PWM_TCON_REG __REG(S5P_PWM_TCON) -#define S5P_PWM_TCNTB0_REG __REG(S5P_PWM_TCNTB0) -#define S5P_PWM_TCMPB0_REG __REG(S5P_PWM_TCMPB0) -#define S5P_PWM_TCNTO0_REG __REG(S5P_PWM_TCNTO0) -#define S5P_PWM_TCNTB1_REG __REG(S5P_PWM_TCNTB1) -#define S5P_PWM_TCMPB1_REG __REG(S5P_PWM_TCMPB1) -#define S5P_PWM_TCNTO1_REG __REG(S5P_PWM_TCNTO1) -#define S5P_PWM_TCNTB2_REG __REG(S5P_PWM_TCNTB2) -#define S5P_PWM_TCMPB2_REG __REG(S5P_PWM_TCMPB2) -#define S5P_PWM_TCNTO2_REG __REG(S5P_PWM_TCNTO2) -#define S5P_PWM_TCNTB3_REG __REG(S5P_PWM_TCNTB3) -#define S5P_PWM_TCNTO3_REG __REG(S5P_PWM_TCNTO3) -#define S5P_PWM_TCNTB4_REG __REG(S5P_PWM_TCNTB4) -#define S5P_PWM_TCNTO4_REG __REG(S5P_PWM_TCNTO4) -#define S5P_PWM_TINT_CSTAT_REG __REG(S5P_PWM_TINT_CSTAT) - -/* PWM timer value */ -#define S5P_TCON4_AUTO_RELOAD (1 << 22) /* Interval mode(Auto Reload) of PWM Timer 4 */ -#define S5P_TCON4_UPDATE (1 << 21) /* Update TCNTB4 */ -#define S5P_TCON4_ON (1 << 20) /* start bit of PWM Timer 4 */ - - - -/* System Timer */ -#define S5P_SYSTIMER_BASE(x) (S5P_PA_SYSTEM + (x)) - -#define SYS_TCFG_OFFSET 0x0 -#define SYS_TCON_OFFSET 0x04 -#define SYS_TCNTB_OFFSET 0x08 -#define SYS_TCNTO_OFFSET 0x0c -#define SYS_ICNTB_OFFSET 0x10 -#define SYS_ICNTO_OFFSET 0x14 -#define SYS_INT_CSTAT_OFFSET 0x18 - -#define S5P_SYS_TCFG S5P_SYSTIMER_BASE(SYS_TCFG_OFFSET) -#define S5P_SYS_TCON S5P_SYSTIMER_BASE(SYS_TCON_OFFSET) -#define S5P_SYS_TCNTB S5P_SYSTIMER_BASE(SYS_TCNTB_OFFSET) -#define S5P_SYS_TCNTO S5P_SYSTIMER_BASE(SYS_TCNTO_OFFSET) -#define S5P_SYS_ICNTB S5P_SYSTIMER_BASE(SYS_ICNTB_OFFSET) -#define S5P_SYS_ICNTO S5P_SYSTIMER_BASE(SYS_ICNTO_OFFSET) -#define S5P_SYS_INT_CSTAT S5P_SYSTIMER_BASE(SYS_INT_CSTAT_OFFSET) - - -/* Watchdog */ -#define S5P_WATCHDOG_BASE(x) (S5P_PA_WATCHDOG + (x)) - -#define WTCON_OFFSET 0x0 -#define WTDAT_OFFSET 0x4 -#define WTCNT_OFFSET 0x8 -#define WTCLRINT_OFFSET 0xc - -#define S5P_WTCON S5P_WATCHDOG_BASE(WTCON_OFFSET) -#define S5P_WTDAT S5P_WATCHDOG_BASE(WTDAT_OFFSET) -#define S5P_WTCNT S5P_WATCHDOG_BASE(WTCNT_OFFSET) -#define S5P_WTCLRINT S5P_WATCHDOG_BASE(WTCLRINT_OFFSET) - -/* RTC */ -#define S5P_RTC_BASE(x) (S5P_PA_RTC + (x)) - -#define INTP_OFFSET 0x30 -#define RTCCON_OFFSET 0x40 -#define TICCNT_OFFSET 0x44 -#define RTCALM_OFFSET 0x50 - -#define ALMSEC_OFFSET 0x54 -#define ALMMIN_OFFSET 0x58 -#define ALMHOUR_OFFSET 0x5c -#define ALMDATE_OFFSET 0x60 -#define ALMMON_OFFSET 0x64 -#define ALMYEAR_OFFSET 0x68 - -#define BCDSEC_OFFSET 0x70 -#define BCDMIN_OFFSET 0x74 -#define BCDHOUR_OFFSET 0x78 -#define BCDDATE_OFFSET 0x7c -#define BCDDAY_OFFSET 0x80 -#define BCDMON_OFFSET 0x84 -#define BCDYEAR_OFFSET 0x88 - -#define CURTICCNT 0x90 - -#define S5P_INTP S5P_RTC_BASE(INTP_OFFSET) -#define S5P_RTCCON S5P_RTC_BASE(RTCCON_OFFSET) -#define S5P_TICCNT S5P_RTC_BASE(TICCNT_OFFSET) -#define S5P_RTCALM S5P_RTC_BASE(RTCALM_OFFSET) - -#define S5P_ALMSEC S5P_RTC_BASE(ALMSEC_OFFSET) -#define S5P_ALMMIN S5P_RTC_BASE(ALMMIN_OFFSET) -#define S5P_ALMHOUR S5P_RTC_BASE(ALMHOUR_OFFSET) -#define S5P_ALMDATE S5P_RTC_BASE(ALMDATE_OFFSET) +/* pwm */ +#define s5p_pwmtimer_base(x) (s5p_pa_pwmtimer + (x)) + +/* pwm timer offset */ +#define pwm_tcfg0_offset 0x0 +#define pwm_tcfg1_offset 0x04 +#define pwm_tcon_offset 0x08 +#define pwm_tcntb0_offset 0x0c +#define pwm_tcmpb0_offset 0x10 +#define pwm_tcnto0_offset 0x14 +#define pwm_tcntb1_offset 0x18 +#define pwm_tcmpb1_offset 0x1c +#define pwm_tcnto1_offset 0x20 +#define pwm_tcntb2_offset 0x24 +#define pwm_tcmpb2_offset 0x28 +#define pwm_tcnto2_offset 0x2c +#define pwm_tcntb3_offset 0x30 +#define pwm_tcnto3_offset 0x38 +#define pwm_tcntb4_offset 0x3c +#define pwm_tcnto4_offset 0x40 +#define pwm_tint_cstat_offset 0x44 + +/* pwm timer register */ +#define s5p_pwm_tcfg0 s5p_pwmtimer_base(pwm_tcfg0_offset) +#define s5p_pwm_tcfg1 s5p_pwmtimer_base(pwm_tcfg1_offset) +#define s5p_pwm_tcon s5p_pwmtimer_base(pwm_tcon_offset) +#define s5p_pwm_tcntb0 s5p_pwmtimer_base(pwm_tcntb0_offset) +#define s5p_pwm_tcmpb0 s5p_pwmtimer_base(pwm_tcmpb0_offset) +#define s5p_pwm_tcnto0 s5p_pwmtimer_base(pwm_tcnto0_offset) +#define s5p_pwm_tcntb1 s5p_pwmtimer_base(pwm_tcntb1_offset) +#define s5p_pwm_tcmpb1 s5p_pwmtimer_base(pwm_tcmpb1_offset) +#define s5p_pwm_tcnto1 s5p_pwmtimer_base(pwm_tcnto1_offset) +#define s5p_pwm_tcntb2 s5p_pwmtimer_base(pwm_tcntb2_offset) +#define s5p_pwm_tcmpb2 s5p_pwmtimer_base(pwm_tcmpb2_offset) +#define s5p_pwm_tcnto2 s5p_pwmtimer_base(pwm_tcnto2_offset) +#define s5p_pwm_tcntb3 s5p_pwmtimer_base(pwm_tcntb3_offset) +#define s5p_pwm_tcnto3 s5p_pwmtimer_base(pwm_tcnto3_offset) +#define s5p_pwm_tcntb4 s5p_pwmtimer_base(pwm_tcntb4_offset) +#define s5p_pwm_tcnto4 s5p_pwmtimer_base(pwm_tcnto4_offset) +#define s5p_pwm_tint_cstat s5p_pwmtimer_base(pwm_tint_cstat_offset) + +/* pwm timer addressing */ +#define s5p_timer_base s5p_pwmtimer_base(0x0) +#define s5p_pwmtimer_base_reg __reg(s5p_pwmtimer_base(0x0)) +#define s5p_pwm_tcfg0_reg __reg(s5p_pwm_tcfg0) +#define s5p_pwm_tcfg1_reg __reg(s5p_pwm_tcfg1) +#define s5p_pwm_tcon_reg __reg(s5p_pwm_tcon) +#define s5p_pwm_tcntb0_reg __reg(s5p_pwm_tcntb0) +#define s5p_pwm_tcmpb0_reg __reg(s5p_pwm_tcmpb0) +#define s5p_pwm_tcnto0_reg __reg(s5p_pwm_tcnto0) +#define s5p_pwm_tcntb1_reg __reg(s5p_pwm_tcntb1) +#define s5p_pwm_tcmpb1_reg __reg(s5p_pwm_tcmpb1) +#define s5p_pwm_tcnto1_reg __reg(s5p_pwm_tcnto1) +#define s5p_pwm_tcntb2_reg __reg(s5p_pwm_tcntb2) +#define s5p_pwm_tcmpb2_reg __reg(s5p_pwm_tcmpb2) +#define s5p_pwm_tcnto2_reg __reg(s5p_pwm_tcnto2) +#define s5p_pwm_tcntb3_reg __reg(s5p_pwm_tcntb3) +#define s5p_pwm_tcnto3_reg __reg(s5p_pwm_tcnto3) +#define s5p_pwm_tcntb4_reg __reg(s5p_pwm_tcntb4) +#define s5p_pwm_tcnto4_reg __reg(s5p_pwm_tcnto4) +#define s5p_pwm_tint_cstat_reg __reg(s5p_pwm_tint_cstat) + +/* pwm timer value */ +#define s5p_tcon4_auto_reload (1 << 22) /* interval mode(auto reload) of pwm timer 4 */ +#define s5p_tcon4_update (1 << 21) /* update tcntb4 */ +#define s5p_tcon4_on (1 << 20) /* start bit of pwm timer 4 */ + + + +/* system timer */ +#define s5p_systimer_base(x) (s5p_pa_system + (x)) + +#define sys_tcfg_offset 0x0 +#define sys_tcon_offset 0x04 +#define sys_tcntb_offset 0x08 +#define sys_tcnto_offset 0x0c +#define sys_icntb_offset 0x10 +#define sys_icnto_offset 0x14 +#define sys_int_cstat_offset 0x18 + +#define s5p_sys_tcfg s5p_systimer_base(sys_tcfg_offset) +#define s5p_sys_tcon s5p_systimer_base(sys_tcon_offset) +#define s5p_sys_tcntb s5p_systimer_base(sys_tcntb_offset) +#define s5p_sys_tcnto s5p_systimer_base(sys_tcnto_offset) +#define s5p_sys_icntb s5p_systimer_base(sys_icntb_offset) +#define s5p_sys_icnto s5p_systimer_base(sys_icnto_offset) +#define s5p_sys_int_cstat s5p_systimer_base(sys_int_cstat_offset) + + +/* watchdog */ +#define s5p_watchdog_base(x) (s5p_pa_watchdog + (x)) + +#define wtcon_offset 0x0 +#define wtdat_offset 0x4 +#define wtcnt_offset 0x8 +#define wtclrint_offset 0xc + +#define s5p_wtcon s5p_watchdog_base(wtcon_offset) +#define s5p_wtdat s5p_watchdog_base(wtdat_offset) +#define s5p_wtcnt s5p_watchdog_base(wtcnt_offset) +#define s5p_wtclrint s5p_watchdog_base(wtclrint_offset) + +/* rtc */ +#define s5p_rtc_base(x) (s5p_pa_rtc + (x)) + +#define intp_offset 0x30 +#define rtccon_offset 0x40 +#define ticcnt_offset 0x44 +#define rtcalm_offset 0x50 + +#define almsec_offset 0x54 +#define almmin_offset 0x58 +#define almhour_offset 0x5c +#define almdate_offset 0x60 +#define almmon_offset 0x64 +#define almyear_offset 0x68 + +#define bcdsec_offset 0x70 +#define bcdmin_offset 0x74 +#define bcdhour_offset 0x78 +#define bcddate_offset 0x7c +#define bcdday_offset 0x80 +#define bcdmon_offset 0x84 +#define bcdyear_offset 0x88 + +#define curticcnt 0x90 + +#define s5p_intp s5p_rtc_base(intp_offset) +#define s5p_rtccon s5p_rtc_base(rtccon_offset) +#define s5p_ticcnt s5p_rtc_base(ticcnt_offset) +#define s5p_rtcalm s5p_rtc_base(rtcalm_offset) + +#define s5p_almsec s5p_rtc_base(almsec_offset) +#define s5p_almmin s5p_rtc_base(almmin_offset) +#define s5p_almhour s5p_rtc_base(almhour_offset) +#define s5p_almdate s5p_rtc_base(almdate_offset) #define S5P_ALMMON S5P_RTC_BASE(ALMMON_OFFSET) #define S5P_ALMYEAR S5P_RTC_BASE(ALMYEAR_OFFSET) -- 2.7.4